JP3322731B2 - A loop detection method in the subscriber circuit of the exchange. - Google Patents

A loop detection method in the subscriber circuit of the exchange.

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Publication number
JP3322731B2
JP3322731B2 JP23145493A JP23145493A JP3322731B2 JP 3322731 B2 JP3322731 B2 JP 3322731B2 JP 23145493 A JP23145493 A JP 23145493A JP 23145493 A JP23145493 A JP 23145493A JP 3322731 B2 JP3322731 B2 JP 3322731B2
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JP
Japan
Prior art keywords
line
power supply
circuit
current
sum
Prior art date
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Expired - Fee Related
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JP23145493A
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Japanese (ja)
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JPH0787534A (en
Inventor
雄三 山本
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Fujitsu Ltd
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Fujitsu Ltd
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Publication of JPH0787534A publication Critical patent/JPH0787534A/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は交換機の加入者回路にお
けるループ検出方式に関する。交換機の加入者回路は交
換機から電話機等の端末に直流給電を行うと共に,加入
者線のループ電流(直流ループ電流)の状態を監視して
端末のオンフック・オフフック(発信時及び着信時の応
答)やダイヤル信号(DP信号,PB信号)を検出して
いる。ところが,ループ検出回路には端末の接続形態
や,線路に誘導される雑音の発生によって正確に検出動
作を行うことができない場合があり,その改善が望まれ
ている。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loop detection system in a subscriber circuit of an exchange. The subscriber's circuit of the exchange supplies DC power from the exchange to terminals such as telephones, monitors the state of the loop current (DC loop current) of the subscriber line, and on-hook / off-hooks the terminal (responses at origination and termination). And dial signals (DP signal, PB signal). However, there are cases where the loop detection circuit cannot accurately perform the detection operation due to the connection form of the terminal or the generation of noise induced in the line, and improvement thereof is desired.

【0002】[0002]

【従来の技術】図11は従来例1及び従来例2の構成
図,図12は従来例3及び従来例4の構成図,図13は
給電回路の具体例を示す図,図14は従来例の動作波形
の例を示す図,図15は同相交流信号時の給電電流また
は電圧の波形を示す図である。
2. Description of the Related Art FIG. 11 is a block diagram of Conventional Examples 1 and 2, FIG. 12 is a block diagram of Conventional Examples 3 and 4, FIG. 13 is a diagram showing a specific example of a power supply circuit, and FIG. FIG. 15 is a diagram showing a waveform of a supply current or a voltage at the time of an in-phase AC signal.

【0003】図11のA.及びB.に示す従来例1及び
従来例2の構成では,加入者端末として電話機(TEL
で表示)が設けられ,チップ線(T線という)とリング
線(R線という)の2本の加入者線により電話機TEL
は交換機と接続されている。交換機の加入者回路には給
電回路が設けられ,T線は地気(Gで表示)を介するT
線側給電回路100に接続され,R線はR線側給電回路
101を介して電源(VBBで表示し,一般には−48
Vが使用される)が接続される。
FIG. And B. In the configurations of Conventional Example 1 and Conventional Example 2 shown in FIG.
And a telephone line TEL by two subscriber lines, a tip line (referred to as T line) and a ring line (referred to as R line).
Is connected to the exchange. A power supply circuit is provided in the subscriber circuit of the exchange, and the T line is connected to the ground through the ground (indicated by G).
The R line is connected to a line-side power supply circuit 100, and the R line is supplied with a power supply (indicated by VBB, generally −48
V is used).

【0004】A.の例ではR線給電電流検出回路とフィ
ルタ回路とによりループ検出回路102が構成され,そ
の出力は,交換機の制御装置の図示されない走査回路
(SCN)へ供給される。B.の例ではR線給電電圧検
出回路とフィルタ回路とでループ検出回路103が構成
されている。
A. In the example, the loop detection circuit 102 is constituted by the R line supply current detection circuit and the filter circuit, and the output is supplied to a scanning circuit (SCN) (not shown) of the control device of the exchange. B. In the example, the loop detection circuit 103 is configured by the R-line power supply voltage detection circuit and the filter circuit.

【0005】給電回路の具体例は図13に示され,その
上側の回路が上記T線側給電回路100,下側の回路が
上記R線側給電回路101に相当する。この回路ではト
ランジスタTR1,TR2がそれぞれの演算増幅器OP
1,OP2(オペレーショナルアンプ)の出力により一
定電流が流れるよう制御される。各演算増幅器OP1,
OP2はそれぞれT線,R線の電圧状態の変化に対して
中点となる電圧を発生して線路への給電電流を制御す
る。また,各コンデンサCや,抵抗RT2〜RT5,R
R2〜RR5等の複数の抵抗を含む回路は,音声信号の
様な差動信号に対しハイインピーダンス,その他の誘導
信号の様な同相信号に対しローインピーダンスになるよ
う構成されている。
FIG. 13 shows a specific example of the power supply circuit. The upper circuit corresponds to the T-line power supply circuit 100, and the lower circuit corresponds to the R-line power supply circuit 101. In this circuit, transistors TR1 and TR2 are connected to respective operational amplifiers OP.
1, a control is made so that a constant current flows by the output of OP2 (operational amplifier). Each operational amplifier OP1,
OP2 generates a voltage at the middle point with respect to the change in the voltage state of the T line and the R line, and controls the power supply current to the line. Also, each capacitor C, resistors RT2 to RT5, R
A circuit including a plurality of resistors such as R2 to RR5 is configured to have a high impedance for a differential signal such as an audio signal and a low impedance for an in-phase signal such as another induction signal.

【0006】図11のA.のループ検出回路102は,
図13の給電回路のトランジスタTR1のエミッタの電
流に比例する電圧を発生するで示す端子の電圧を取り
出してR線給電電流の検出を行うことができる。また,
B.のループ検出回路103は,図13の給電回路の抵
抗RR3と抵抗RR4による分圧電圧が発生するで示
す端子の電圧を取り出してR線給電電圧の検出を行うこ
とができる。
FIG. The loop detection circuit 102 of
The R-line power supply current can be detected by extracting the voltage at the terminal indicated by the symbol "1" which generates a voltage proportional to the current of the emitter of the transistor TR1 in the power supply circuit of FIG. Also,
B. The loop detection circuit 103 can detect the R line supply voltage by extracting the voltage of the terminal indicated by the divided voltage generated by the resistors RR3 and RR4 of the power supply circuit of FIG.

【0007】図11のA.による電流検出の場合,端末
側に複数の電話機等が並列接続された場合,例えば,複
数の電話機に一つの電話番号が付されているような場
合,その中の1台が直流信号のオン・オフ(メーク・ブ
レーク)によるダイヤル(DPダイヤル)を行うと,並
列に接続された他の電話機のベル回路のインピーダンス
(主にインダクタンスL)によりフライバック電流が流
れ,このフライバック電流の誤検出をするという問題が
ある。
FIG. In the case of the current detection by the above, when a plurality of telephones or the like are connected in parallel to the terminal side, for example, when one telephone number is assigned to a plurality of telephones, one of the telephones turns on / off the DC signal. When the dial (DP dial) is turned off (make break), flyback current flows due to the impedance (mainly inductance L) of the bell circuit of another telephone connected in parallel, and false detection of this flyback current may occur. There is a problem of doing.

【0008】この状態を図14に示す従来例の動作波形
の例を用いて説明すると,図14のA.はDPダイヤル
時のフライバック電流の影響を示し,に従来例1の電
流検出におけるフライバック電流の波形が示され,メー
クからブレークになった時フライバック電流が流れ,そ
の電流値がスレッショルド電圧を越えると,メークした
ものと誤って判定される。
This state will be described with reference to an example of an operation waveform of a conventional example shown in FIG. Shows the effect of the flyback current at the time of the DP dial, and shows the waveform of the flyback current in the current detection of the conventional example 1. The flyback current flows when the make breaks, and the current value indicates the threshold voltage. If it exceeds, it is erroneously determined to be a make.

【0009】また,交流誘導等の同相交流信号がT線・
R線に誘導すると,給電回路は同相交流信号に対してロ
ーインピーダンスのため,誘導電流が給電回路に流れル
ープ検出回路が誤検出してしまう。
[0009] Further, the in-phase AC signal such as AC induction is applied to a T-line.
When the power supply circuit is guided to the R line, the power supply circuit has a low impedance with respect to the in-phase AC signal.

【0010】この様子は図15に示され,G(地気)と
VBB(−48V)の間のT線とR線の電圧に対し実線
で示す同相交流が重畳されると,ループ検出のスレッシ
ョルド電圧を越える期間(図中太線で示す)が発生して
誤検出が起きる。これを避けるため図11に示す各ルー
プ検出回路内にフィルタ回路が設けられており,フィル
タにより図15の点線で示すように同相交流による影響
を小さくすることができる。
This situation is shown in FIG. 15. When the in-phase alternating current shown by the solid line is superimposed on the voltage of the T line and the R line between G (ground) and VBB (-48 V), the threshold for loop detection is obtained. A period exceeding the voltage (shown by a bold line in the figure) occurs and erroneous detection occurs. To avoid this, a filter circuit is provided in each loop detection circuit shown in FIG. 11, and the influence of the in-phase alternating current can be reduced by the filter as shown by the dotted line in FIG.

【0011】次に図11のB.に示す従来例2(電圧検
出)の場合,フライバック電流は図14のA.のに示
すように電流のレベルが極めて低いため問題にならな
い。しかし,ループ抵抗の急激な変化の時には,電圧が
落ち込んで誤検出してしまうという問題がある。
Next, FIG. In the case of Conventional Example 2 (voltage detection) shown in FIG. Since the current level is extremely low as shown in FIG. However, when the loop resistance changes abruptly, there is a problem that the voltage drops and erroneous detection is performed.

【0012】このループ抵抗の急激な変化とは,ダイヤ
ル電話機(DP)の場合,DP送出時は送話器の抵抗が
無くなり0Ωとなってしまうこと,及びPB電話器(D
TMF信号を発生する電話器)の場合は,キーを押して
いる時は直流抵抗が増加すること等である。この場合の
電圧の落ち込みを図14のB.にインピーダンス変化時
の波形として示す。このB.のに示す電流値は,イン
ピーダンスが変化した時に時定数によりゆったり下降す
るが,に示す電圧値はループが断になった時に瞬時に
ドロップしてスレッショルド電圧を越えてしまうため,
ループ断として誤検出が発生する。
[0012] The rapid change of the loop resistance means that, in the case of a dial telephone (DP), the resistance of the transmitter is lost when the DP is transmitted and becomes 0Ω, and the PB telephone (D
In the case of a telephone which generates a TMF signal), the DC resistance increases when a key is pressed. The voltage drop in this case is represented by B. in FIG. The waveforms at the time of impedance change are shown in FIG. This B. The current value shown in (1) slowly falls due to the time constant when the impedance changes, but the voltage value shown in (2) drops instantaneously when the loop is broken and exceeds the threshold voltage.
An erroneous detection occurs as a loop break.

【0013】次に図12のA.及びB.に示す従来例3
及び従来例4の構成は,従来例3がT線給電電流検出部
とR線給電電流検出部を備え各回路の出力を加算するル
ープ検出回路104を備え,従来例4がT線給電電圧検
出部とR線給電電圧検出部を備え各回路の出力を加算す
るループ検出回路105を備えている。
Next, FIG. And B. Conventional example 3 shown in
In the configuration of the conventional example 4, the conventional example 3 includes a T-line power supply current detecting unit and an R-line power supply current detecting unit, and includes a loop detection circuit 104 for adding the outputs of the respective circuits. And a loop detection circuit 105 that includes an R-line power supply voltage detection unit and adds the outputs of the respective circuits.

【0014】従来例3の場合,T線・R線の給電電流の
和を検出するので,交流誘導等の同相交流が誘導しても
両者の電流の和をとっているのでフィルタを設けないで
もループ検出回路104は誤検出しないが,電流検出の
ためフライバック電流を検出してしまう。
In the case of the conventional example 3, since the sum of the supply currents of the T line and the R line is detected, even if in-phase AC such as AC induction is induced, the sum of both currents is obtained. The loop detection circuit 104 does not erroneously detect, but detects a flyback current for current detection.

【0015】従来例4の場合,交流誘導等の同相交流が
誘導してもT線とR線の電圧の和をとっているため,フ
ィルタを設けないでもループ検出回路105は誤検出し
ない。しかし,電圧検出のため,ループ抵抗の急激な変
化の時には誤検出してしまう。
In the case of the conventional example 4, since the sum of the voltages of the T line and the R line is obtained even when an in-phase AC such as an AC induction is induced, the loop detection circuit 105 does not erroneously detect without a filter. However, due to the voltage detection, erroneous detection is performed when the loop resistance changes abruptly.

【0016】[0016]

【発明が解決しようとする課題】上記したように,従来
例1,従来例3はダイヤルパルス時のフライバック電流
による誤検出という問題,従来例2及び従来例4はルー
プ抵抗の急激な変化による誤検出という問題があった。
As described above, the prior arts 1 and 3 have a problem of erroneous detection due to a flyback current at the time of a dial pulse, and the prior arts 2 and 4 have a problem due to a sudden change in loop resistance. There was a problem of false detection.

【0017】本発明はダイヤルパルス時のフライバック
電流の誤検出や,線路抵抗の急激な変化時の誤検出を防
止することができる交換機の加入者回路におけるループ
検出方式を提供することを目的とする。
An object of the present invention is to provide a loop detection method in a subscriber circuit of an exchange which can prevent erroneous detection of a flyback current at the time of a dial pulse and erroneous detection at the time of a rapid change in line resistance. I do.

【0018】[0018]

【課題を解決するための手段】図1は本発明の第1の基
本構成図,図2は本発明の第2の基本構成図,図3は本
発明の第3の基本構成図,図4は本発明の第4の基本構
成図,図5は本発明の第5の基本構成図である。
FIG. 1 is a first basic configuration diagram of the present invention, FIG. 2 is a second basic configuration diagram of the present invention, FIG. 3 is a third basic configuration diagram of the present invention, and FIG. Is a fourth basic configuration diagram of the present invention, and FIG. 5 is a fifth basic configuration diagram of the present invention.

【0019】図1において,1は加入者線のT線へ給電
を行うT線側給電回路,2は加入者のR線へ給電を行う
R線側給電回路,3はループ検出回路,3aはR線給電
電圧検出部,3bはR線給電電流検出部,3cは3aと
3bの出力の和を発生する加算部,3dはフィルタ回路
である。
In FIG. 1, reference numeral 1 denotes a T-line side power supply circuit for supplying power to a subscriber line T line, 2 denotes an R line side power supply circuit for supplying power to a subscriber R line, 3 denotes a loop detection circuit, and 3a denotes a loop detection circuit. An R-line power supply voltage detector, 3b is an R-line power supply current detector, 3c is an adder that generates the sum of the outputs of 3a and 3b, and 3d is a filter circuit.

【0020】図2乃至図5に示す各回路において,1,
2は上記図1の各符号と同じ回路であり,4〜7はそれ
ぞれ第2乃至第5の原理による各ループ検出回路であ
る。図2のループ検出回路4において,4aはT線給電
電流検出部,4bはT線給電電圧検出部,4cは加算
部,4dはフィルタ回路である。
In each of the circuits shown in FIGS.
Reference numeral 2 denotes the same circuits as those in FIG. 1, and reference numerals 4 to 7 denote loop detection circuits according to the second to fifth principles, respectively. In the loop detection circuit 4 of FIG. 2, reference numeral 4a denotes a T-line power supply current detector, 4b denotes a T-line power supply voltage detector, 4c denotes an adder, and 4d denotes a filter circuit.

【0021】図3のループ検出回路5において,5aは
T線給電電流検出部,5bはR線給電電圧検出部,5c
は加算部である。また,図4のループ検出回路6におい
て,6aはT線給電電圧検出部,6bはR線給電電流検
出部,6cは加算部である。次に図5のループ検出回路
7において,7aはR・T線の給電電圧の和検出部,7
bはR・T線の給電電流の和検出部,7cは加算部であ
る。
In the loop detection circuit 5 of FIG. 3, 5a is a T-line power supply current detector, 5b is an R-line power supply voltage detector, 5c
Is an adder. In the loop detection circuit 6 of FIG. 4, reference numeral 6a denotes a T-line power supply voltage detector, 6b denotes an R-line power supply current detector, and 6c denotes an adder. Next, in the loop detection circuit 7 shown in FIG.
b is a sum detection unit for the supply current of the R / T line, and 7c is an addition unit.

【0022】本発明はR線側の給電回路とT線側の給電
回路からその何れか一方の線路への給電電圧と給電電流
の和を発生してループ検出を行うものである。また,一
方の線路への給電電流と他方の線路の給電電圧の和を発
生してループ検出を行うものである。更に,一方の線路
への給電電圧と他方の線路への給電電流の和と,他方の
線路の給電電流と一方の線路への給電電流の和とを求
め,両者の和を発生してループ検出を行うものである。
According to the present invention, the loop detection is performed by generating the sum of the power supply voltage and the power supply current from the power supply circuit on the R line side and the power supply circuit on the T line side to one of the lines. Further, the loop detection is performed by generating the sum of the supply current to one line and the supply voltage to the other line. Furthermore, the sum of the supply voltage to one line and the supply current to the other line, and the sum of the supply current to the other line and the supply current to one line are obtained, and the sum of both is generated to detect a loop. Is what you do.

【0023】[0023]

【作用】図1の構成では,R線への給電電圧をループ検
出回路3のR線給電電圧検出部3aで検出し,R線への
給電電流をR線給電電流検出部3bで検出し,両検出部
3a,3bの出力の和を加算部3cで発生する。この加
算部3cの出力信号は,電圧と電流の和に対応する一定
の閾値(スレッショルド電圧)と比較(比較器は図示省
略)されてループ検出出力となる。その閾値は,電流ま
たは電圧の一方の場合のレベルに比べて高くする(約2
倍にする)ため,ダイヤルパルス時のフライバック電流
は検出しない。また,ループ抵抗の急激な変化時も電流
と電圧の和のため,抵抗が小から大になる時は打ち消し
合って誤検出しない。フィルタ回路3dは,交流誘導に
よる同相交流信号の影響を除去する場合に加算部3cの
後段に付加され,その出力がスレッショルド電圧と比較
される。
In the configuration of FIG. 1, the supply voltage to the R line is detected by the R line supply voltage detector 3a of the loop detection circuit 3, and the supply current to the R line is detected by the R line supply current detector 3b. The sum of the outputs of the two detectors 3a and 3b is generated by an adder 3c. The output signal of the adder 3c is compared with a fixed threshold value (threshold voltage) corresponding to the sum of the voltage and the current (a comparator is not shown) and becomes a loop detection output. The threshold value is set higher than the level in one of the current and the voltage (about 2).
Therefore, flyback current at the time of dial pulse is not detected. Further, even when the loop resistance changes abruptly, since the current and the voltage are summed, when the resistance increases from small to large, the resistances cancel each other out and no erroneous detection is performed. The filter circuit 3d is added to the subsequent stage of the adder 3c when removing the influence of the in-phase AC signal due to the AC induction, and its output is compared with the threshold voltage.

【0024】図2の構成は,上記図1の構成がR線への
給電電圧と給電電流を検出しているのに対し,T線への
給電電圧と給電電流を検出する点が相違し,ループ検出
回路4の作用は図1と同様である。すなわち,T線給電
電流検出部4aとT線給電電圧検出部4bの各出力の和
を加算部4cで発生し,一定の閾値と比較される。フィ
ルタ回路4dも,図1の場合と同様に同相交流信号の影
響を除去する時に付加される。
The configuration of FIG. 2 is different from the configuration of FIG. 1 in that the configuration detects the supply voltage and the supply current to the R line, whereas the configuration of FIG. 1 detects the supply voltage and the supply current to the T line. The operation of the loop detection circuit 4 is the same as in FIG. That is, the sum of the respective outputs of the T-line power supply current detector 4a and the T-line power supply voltage detector 4b is generated by the adder 4c and compared with a fixed threshold. The filter circuit 4d is also added when removing the influence of the in-phase AC signal, as in the case of FIG.

【0025】次に図3の構成の場合,ループ検出回路5
はT線給電電流検出部5aでT線の給電電流を検出し,
R線給電電圧検出部5bでR線の給電電圧を検出し,両
検出部5a,5bの出力の和を加算部5cで発生する。
この加算部5cの出力信号は図1と同様に高い一定の閾
値と比較される。この場合も,ダイヤルパルス時のフラ
イバック電流及びループ抵抗の急激な変化に対しても誤
検出が起きない。また,T線の電流とR線の電圧の和の
ため交流誘導による同相交流信号は打ち消し合って検出
されない。
Next, in the case of the configuration of FIG.
Indicates the T-line feed current detected by the T-line feed current detector 5a,
The R line supply voltage detector 5b detects the supply voltage of the R line, and the sum of the outputs of the two detectors 5a and 5b is generated by the adder 5c.
The output signal of the adder 5c is compared with a high constant threshold value as in FIG. Also in this case, erroneous detection does not occur even for a rapid change in the flyback current and loop resistance at the time of the dial pulse. In addition, because of the sum of the current on the T line and the voltage on the R line, the in-phase AC signal due to AC induction is canceled out and not detected.

【0026】また,図4の構成は,ループ検出回路6
は,T線給電電圧検出部6aとR線給電電流検出部6b
を備え,両検出部6a,6bの出力の和を加算部6cで
発生し,一定の高い閾値と比較される。このループ検出
回路6は上記図3のループ検出回路5とはR線とT線の
電圧,電流の関係が逆である点を除き,同様の作用を行
う。
The configuration shown in FIG.
Are the T-line feed voltage detector 6a and the R-line feed current detector 6b
The sum of the outputs of the two detectors 6a and 6b is generated by the adder 6c and compared with a fixed high threshold. The loop detection circuit 6 performs the same operation as the loop detection circuit 5 of FIG. 3 except that the relationship between the voltage and current of the R line and the T line is opposite.

【0027】更に,図5の構成は,ループ検出回路7
は,T線の給電電圧とR線の給電電圧の和をR・T線給
電電圧の和検出部7aで求め,T線の給電電流とR線の
給電電流の和をR・T線給電電流の和検出部7bで求め
て,両検出部の和を加算部7cで発生する。この場合,
ダイヤル発生時のフライバック電流及びループ抵抗の急
激な変化時にも上記図1の場合と同様に誤検出をしな
い。また,交流誘導時には,片線の電流と他方の片線の
和だけ電流と電圧の位相のズレにより完全に同相信号を
除去できないが,TR線の電流和とTR線の電圧和によ
り電流と電圧の同相信号を完全に打ち消した後に和をと
るため,交流誘導による影響がなくなる。
Further, the configuration of FIG.
Calculates the sum of the supply voltage of the T line and the supply voltage of the R line by an R / T line supply voltage sum detector 7a, and calculates the sum of the supply current of the T line and the supply current of the R line by the R / T line supply current. The sum of the two detectors is obtained by an adder 7c. in this case,
As in the case of FIG. 1, erroneous detection is not performed even when the flyback current and the loop resistance suddenly change when a dial is generated. In addition, at the time of AC induction, the in-phase signal cannot be completely removed due to the phase difference between the current and the voltage by the sum of the current of one line and the other line. Since the sum is obtained after completely canceling the common mode signal of the voltage, the influence of the AC induction is eliminated.

【0028】[0028]

【実施例】図6は実施例1の構成図,図7は実施例1の
動作波形を示す図である。この図6の構成は,上記本発
明の第1の基本構成図のループ検出回路の実施例であ
る。図中,OP3,OP4はそれぞれ演算増幅器,TR
3,TR4はトランジスタ,CMPはコンパレータ(比
較器)であり,フィルタはバッファ,抵抗R4とコンデ
ンサCとで構成する。
FIG. 6 is a block diagram of the first embodiment, and FIG. 7 is a diagram showing operation waveforms of the first embodiment. The configuration of FIG. 6 is an embodiment of the loop detection circuit of the first basic configuration diagram of the present invention. In the figure, OP3 and OP4 are operational amplifiers and TR, respectively.
3, TR4 is a transistor, CMP is a comparator, and a filter is composed of a buffer, a resistor R4 and a capacitor C.

【0029】また,グランドから抵抗R3を介してトラ
ンジスタTR3のコレクタとトランジスタTR4のコレ
クタが接続され,フィルタへ入力される。フィルタを使
用しないで構成することもできるが,その場合はコンパ
レータCMPへ入力する。トランジスタTR3のエミッ
タは抵抗R1を介して負電源(VBB)に接続され,ト
ランジスタTR4のエミッタは抵抗R2を介して負電源
(VBB)に接続される。
The collector of the transistor TR3 and the collector of the transistor TR4 are connected from the ground via the resistor R3, and are input to the filter. It is also possible to configure without using a filter, but in that case, it is input to the comparator CMP. The emitter of the transistor TR3 is connected to a negative power supply (VBB) via a resistor R1, and the emitter of the transistor TR4 is connected to a negative power supply (VBB) via a resistor R2.

【0030】図6の構成により図1のループ検出回路3
を構成する場合,演算増幅器OP3ので示す入力とし
てR線の供給電流に対応する電圧が供給され,演算増幅
器OP4ので示す入力としてR線の供給電圧を表す信
号が供給される。
With the configuration of FIG. 6, the loop detection circuit 3 of FIG.
, The voltage corresponding to the supply current of the R line is supplied as an input indicated by the operational amplifier OP3, and a signal representing the supply voltage of the R line is supplied as an input indicated by the operational amplifier OP4.

【0031】の信号は演算増幅器(オペアンプ)のイ
マジナリショートにより,演算増幅器OP3の−端子に
発生し,の信号はV1(抵抗R1の両端の電圧)と等
しくなり,I1(抵抗R1を流れる電流)=V1/R1
となる。の信号は演算増幅器のイマジナリショートに
より演算増幅器OP4の−端子に発生し,の信号はV
2(抵抗R2の両端の電圧)と等しくなり,I2(抵抗
R2を流れる電流)=V2/R2となる。
Is generated at the minus terminal of the operational amplifier OP3 due to the imaginary short-circuit of the operational amplifier (op-amp), the signal becomes equal to V1 (the voltage across the resistor R1), and I1 (current flowing through the resistor R1) = V1 / R1
Becomes Is generated at the minus terminal of the operational amplifier OP4 due to the imaginary short circuit of the operational amplifier.
2 (the voltage across the resistor R2), and I2 (current flowing through the resistor R2) = V2 / R2.

【0032】抵抗R3に流れる電流I3は,上記電流の
和(I1+I2)となり,R1=R2=R3の場合,R
3の電圧は,のR線の供給電流とのR線の供給電圧
の和に相当する電圧が発生する。
The current I3 flowing through the resistor R3 is the sum of the above currents (I1 + I2). When R1 = R2 = R3, the current I3
As the voltage 3, a voltage corresponding to the sum of the supply current of the R line and the supply voltage of the R line is generated.

【0033】この信号は,同相交流信号を除去する必要
がある場合,フィルタを通って,必要が無い場合は,直
接コンパレータCMPへ供給される。ここで電圧または
電流の一方だけで検出する場合に比べて2倍の値を持つ
スレッショルド電圧(Vthで示す)と比較して,比較
結果は図示されない走査回路(SCN)へ出力される。
This signal passes through a filter when it is necessary to remove the in-phase AC signal, and is directly supplied to the comparator CMP when not necessary. Here, a comparison result is output to a scanning circuit (SCN) (not shown) in comparison with a threshold voltage (indicated by Vth) having a value twice as large as that in the case of detecting only one of the voltage and the current.

【0034】この構成によりダイアルパルス時の電流と
電圧の和の特性は,図7のA.に示され,スレッショル
ド電圧(Vth)も高く設定されるため,上記図14の
A.に示す従来例に比べてフライバック電流による誤検
出が発生しない。
According to this configuration, the characteristic of the sum of the current and the voltage at the time of the dial pulse is shown in FIG. Since the threshold voltage (Vth) is also set high, As compared with the conventional example shown in FIG.

【0035】また,ループ抵抗の急激な変更に対して
も,図7のB.に示すように,電流と電圧の和の出力に
より上記図14のB.に示す従来のような誤検出を起こ
さない。
In addition, even when the loop resistance is suddenly changed, the operation of FIG. As shown in FIG. 14, B. in FIG. Does not cause erroneous detection as in the prior art shown in FIG.

【0036】次に図8は実施例2の構成図であり,上記
本発明の第2の基本構成図のループ検出回路4の実施例
である。この構成では,負電源(VBB)が抵抗R7を
介してトランジスタTR5,TR6のコレクタの接続点
(フィルタへの入力)へ供給されている。
FIG. 8 is a block diagram of the second embodiment, which is an embodiment of the loop detection circuit 4 of the second basic block diagram of the present invention. In this configuration, a negative power supply (VBB) is supplied to the connection point (input to the filter) between the collectors of the transistors TR5 and TR6 via the resistor R7.

【0037】上記実施例1の構成と異なり,演算増幅器
OP5のの入力にT線の供給電流に対応する電圧が供
給され,演算増幅器OP6のの入力にT線の供給電圧
を表す信号が供給される。の信号は,演算増幅器のイ
マジナリショートにより演算増幅器OP5の−端子に発
生し,の信号が電圧V5と等しくなって,電流I5
(抵抗R5を流れる電流)=V5/R5となる。の信
号は,演算増幅器のイマジナリショートにより演算増幅
器OP6の−端子に発生し,の信号は電圧V6と等し
くなって,電流I6(抵抗R6を流れる電流)=V6/
R6となる。
Unlike the configuration of the first embodiment, a voltage corresponding to the supply current of the T line is supplied to the input of the operational amplifier OP5, and a signal representing the supply voltage of the T line is supplied to the input of the operational amplifier OP6. You. Is generated at the negative terminal of the operational amplifier OP5 due to the imaginary short-circuit of the operational amplifier, the signal becomes equal to the voltage V5, and the current I5
(Current flowing through the resistor R5) = V5 / R5. Is generated at the negative terminal of the operational amplifier OP6 due to the imaginary short-circuit of the operational amplifier. The signal becomes equal to the voltage V6, and the current I6 (current flowing through the resistor R6) = V6 /
R6.

【0038】また,抵抗R7に流れる電流I7は上記の
電流の和(=I5+I6)となり,R5=R6=R7の
場合,抵抗R7の電圧は,のT線の供給電流とのT
線の供給電圧の和に相当する電圧が発生する。
The current I7 flowing through the resistor R7 is the sum of the above currents (= I5 + I6). When R5 = R6 = R7, the voltage of the resistor R7 is equal to T
A voltage corresponding to the sum of the supply voltages of the lines is generated.

【0039】この信号が,同相交流信号を除去する必要
がある場合は,図8に示すフィルタを通って,必要がな
い場合は直接コンパレータCOPへ供給され,ここで電
圧または電流の一方だけで検出する場合に比べて2倍の
値を持つスレッショルド電圧(Vth)と比較して,比
較結果は図示されない走査回路(SCN)へ出力され
る。
This signal passes through the filter shown in FIG. 8 when it is necessary to remove the in-phase AC signal, and when it is not necessary, it is directly supplied to the comparator COP, where it is detected by only one of the voltage and the current. The comparison result is output to a scanning circuit (SCN) (not shown) in comparison with a threshold voltage (Vth) having a value twice as large as that in the case where the threshold voltage is higher than the threshold voltage (Vth).

【0040】次に図9は実施例3の構成図である。この
構成は上記本発明の第3の基本構成(図3)のループ検
出回路5及び上記第4の基本構成(図4)のループ検出
回路6の実施例である。
FIG. 9 is a block diagram of the third embodiment. This configuration is an embodiment of the loop detection circuit 5 of the third basic configuration (FIG. 3) and the loop detection circuit 6 of the fourth basic configuration (FIG. 4) of the present invention.

【0041】図9の回路により第3のループ検出回路5
(図3)を構成する場合,入力1にT線の供給電流に対
応する電圧が供給され,入力2にR線の供給電圧を表す
信号が供給される。入力1の信号は演算増幅器OP7の
出力に発生し(電圧V8で表す),入力2の信号は演算
増幅器のイマジナリショートにより演算増幅器OP8の
−端子に発生し,入力2=電圧V9となり,I9=V9
/R9となる。R8=R9の場合,抵抗R8の両端電圧
はV9となり,この結果,トランジスタTR3のコレク
タには,入力1のT線の供給電流と入力2のR線の供給
電圧の和に相当する電圧が発生する。
The circuit shown in FIG.
In the configuration shown in FIG. 3, a voltage corresponding to the supply current of the T line is supplied to the input 1 and a signal representing the supply voltage of the R line is supplied to the input 2. The signal of input 1 is generated at the output of operational amplifier OP7 (represented by voltage V8), and the signal of input 2 is generated at the negative terminal of operational amplifier OP8 due to the imaginary shortage of the operational amplifier, so that input 2 = voltage V9 and I9 = V9
/ R9. When R8 = R9, the voltage across the resistor R8 becomes V9. As a result, a voltage corresponding to the sum of the supply current of the T line of the input 1 and the supply voltage of the R line of the input 2 is generated at the collector of the transistor TR3. I do.

【0042】このループ検出回路5の場合は,フィルタ
を介すること無く直接コンパレータCMPへ入力してス
レッショルド電圧(Vth)と比較される。次に図9の
回路により第4のループ検出回路6(図4)を構成する
場合,入力1にT線の供給電圧を表す信号が供給され,
入力2にR線の供給電流に対応する電圧が供給される。
この場合,上記のループ検出回路5と同様に動作し,T
線供給電圧とR線の供給電流の和に相当する電圧が発生
する。和の出力はフィルタを介すること無く直接コンパ
レータCMPへ入力してスレッショルド電圧(Vth)
と比較される。
In the case of this loop detection circuit 5, the signal is directly input to the comparator CMP without passing through a filter and compared with a threshold voltage (Vth). Next, when the fourth loop detection circuit 6 (FIG. 4) is configured by the circuit of FIG. 9, a signal representing the supply voltage of the T line is supplied to the input 1;
The input 2 is supplied with a voltage corresponding to the supply current of the R line.
In this case, the operation is similar to that of the loop detection circuit 5 described above, and T
A voltage corresponding to the sum of the line supply voltage and the supply current of the R line is generated. The output of the sum is directly input to the comparator CMP without passing through a filter, and the threshold voltage (Vth)
Is compared to

【0043】図10は実施例4の構成図である。この構
成は上記図5に示す本発明の第5の基本構成のループ検
出回路7の実施例である。図10において,演算増幅器
OP7〜OP10は,それぞれ上記13に示す給電回路
から給電電圧に対応する電圧または給電電流に対応する
電圧が入力される演算増幅器である。すなわち,演算増
幅器OP7の入力には図13ので表す端子からT線の
給電電流に対応する電圧が供給され,演算増幅器OP8
の入力には図13ので表す端子からR線の給電電圧に
対応する電圧が供給され,2つの給電電圧の和を表す信
号がトランジスタTR9のコレクタ側から発生し,バッ
ファ1に入力する。
FIG. 10 is a block diagram of the fourth embodiment. This configuration is an embodiment of the loop detection circuit 7 having the fifth basic configuration of the present invention shown in FIG. In FIG. 10, operational amplifiers OP7 to OP10 are operational amplifiers to which a voltage corresponding to the power supply voltage or a voltage corresponding to the power supply current is input from the power supply circuit shown in FIG. That is, a voltage corresponding to the supply current of the T line is supplied to the input of the operational amplifier OP7 from the terminal indicated by the symbol in FIG.
13, a voltage corresponding to the supply voltage of the R line is supplied from the terminal indicated by FIG. 13, and a signal representing the sum of the two supply voltages is generated from the collector side of the transistor TR9 and input to the buffer 1.

【0044】また,演算増幅器OP9の入力には,図1
3ので表す端子からT線の給電電流に対応する電圧が
供給され,演算増幅器OP10の入力には図13ので
表す端子からR線の給電電流に対応する電圧が供給さ
れ,2つの給電電流の和を表す信号がトランジスタTR
10のコレクタ側から発生し,バッファ2に入力する。
Also, the input of the operational amplifier OP9 is shown in FIG.
A voltage corresponding to the supply current of the T line is supplied from a terminal indicated by 3 and a voltage corresponding to the supply current of the R line is supplied to the input of the operational amplifier OP10 from the terminal indicated by FIG. Is a transistor TR
It is generated from the collector side of No. 10 and input to the buffer 2.

【0045】バッファ1とバッファ2の2つの信号は,
トランジスタTR1を含む加算回路において加算され,
加算結果を表す信号はトランジスタTR11のコレクタ
側からコンパレータCMPへ入力され,ここで電圧また
は電流の値を単独で比較する場合に比べて約4倍のレベ
ルを持つスレッショルド電圧(Vth)と比べられる。
この比較結果は,走査回路(SCN)へ供給される。
The two signals of buffer 1 and buffer 2 are
The addition is performed in the addition circuit including the transistor TR1,
A signal representing the result of the addition is input from the collector of the transistor TR11 to the comparator CMP, where it is compared with a threshold voltage (Vth) having a level approximately four times as high as that when comparing the voltage or current value alone.
This comparison result is supplied to the scanning circuit (SCN).

【0046】[0046]

【発明の効果】本発明によれば交換機の加入者回路にお
けるループ検出において,ダイヤルパルス時のフライバ
ック電流の誤検出や,線路抵抗の急激な変化時における
誤検出を防止することができる。また,本発明の第3及
び第4の構成(上記の図3,図4の構成)により更に同
相交流信号による誤検出を防止することができる。更
に,第5の構成により同相交流信号による影響を完全に
除去することができる。
According to the present invention, in the loop detection in the subscriber circuit of the exchange, erroneous detection of a flyback current at the time of a dial pulse and erroneous detection at the time of a rapid change in line resistance can be prevented. Further, the third and fourth configurations (the configurations in FIGS. 3 and 4 described above) of the present invention can further prevent erroneous detection due to the in-phase AC signal. Furthermore, the fifth configuration makes it possible to completely eliminate the influence of the in-phase AC signal.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の基本構成図である。FIG. 1 is a first basic configuration diagram of the present invention.

【図2】本発明の第2の基本構成図である。FIG. 2 is a second basic configuration diagram of the present invention.

【図3】本発明の第3の基本構成図である。FIG. 3 is a third basic configuration diagram of the present invention.

【図4】本発明の第4の基本構成図である。FIG. 4 is a fourth basic configuration diagram of the present invention.

【図5】本発明の第5の基本構成図である。FIG. 5 is a fifth basic configuration diagram of the present invention.

【図6】実施例1の構成図である。FIG. 6 is a configuration diagram of a first embodiment.

【図7】実施例1の動作波形を示す図である。FIG. 7 is a diagram showing operation waveforms of the first embodiment.

【図8】実施例2の構成図である。FIG. 8 is a configuration diagram of a second embodiment.

【図9】実施例3の構成図である。FIG. 9 is a configuration diagram of a third embodiment.

【図10】実施例4の構成図である。FIG. 10 is a configuration diagram of a fourth embodiment.

【図11】従来例1及び従来例2の構成図である。FIG. 11 is a configuration diagram of Conventional Example 1 and Conventional Example 2.

【図12】従来例3及び従来例4の構成図である。FIG. 12 is a configuration diagram of Conventional Example 3 and Conventional Example 4.

【図13】給電回路の具体例を示す図である。FIG. 13 is a diagram illustrating a specific example of a power supply circuit.

【図14】従来例の動作波形の例を示す図である。FIG. 14 is a diagram showing an example of an operation waveform of a conventional example.

【図15】同相交流信号時の給電電流または電圧の波形
を示す図である。
FIG. 15 is a diagram showing a waveform of a supply current or a voltage during an in-phase AC signal.

【符号の説明】[Explanation of symbols]

1 T線側給電回路 2 R線側給電回路 3 ループ検出回路 3a R線給電電圧検出部 3b R線給電電流検出部 3c 加算部 3d フィルタ回路 DESCRIPTION OF SYMBOLS 1 T-line side power supply circuit 2 R-line side power supply circuit 3 Loop detection circuit 3a R-line power supply voltage detection part 3b R-line power supply current detection part 3c Addition part 3d Filter circuit

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平4−241595(JP,A) 特開 昭63−304793(JP,A) 特開 平1−314093(JP,A) 特開 昭63−308496(JP,A) 特開 平5−219537(JP,A) 特開 平5−145957(JP,A) ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-241595 (JP, A) JP-A-63-304793 (JP, A) JP-A-1-314093 (JP, A) JP-A 63-304 308496 (JP, A) JP-A-5-219537 (JP, A) JP-A-5-145957 (JP, A)

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 加入者線のT線とR線にそれぞれ接続さ
れたT線側給電回路とR線側給電回路を備えた交換機の
加入者回路において, R線の給電電流検出部とR線の給電電圧検出部及び前記
R線の給電電流検出部の出力と前記R線の給電電圧検出
部の出力の和を発生する加算部を設け,前記加算部から発生する値を 指定された閾値と比較して
ループ検出信号を出力することを特徴とする交換機の加
入者回路におけるループ検出方式。
In a subscriber circuit of an exchange having a T-line power supply circuit and an R-line power supply circuit connected to a T-line and an R-line of a subscriber line, respectively, a feed current detection unit for an R line and an R line Power supply voltage detector and the
Output of R-line power supply current detection unit and detection of R-line power supply voltage
A loop detection method in a subscriber circuit of an exchange, comprising: an adder for generating a sum of outputs from the adders , and comparing a value generated from the adder with a designated threshold to output a loop detection signal.
【請求項2】 加入者線のT線とR線にそれぞれ接続さ
れたT線側給電回路とR線側給電回路を備えた交換機の
加入者回路において, T線の給電電流検出部とT線の給電電圧検出部及び前記
T線の給電電流検出部の出力と前記T線の給電電圧検出
部の出力の和を発生する加算部を設け,前記加算部から発生する値を 指定された閾値と比較して
ループ検出信号を出力することを特徴とする交換機の加
入者回路におけるループ検出方式。
2. A subscriber line connected to a T line and an R line, respectively.
Of an exchange equipped with a T-line feed circuit and an R-line feed circuit
In the subscriber circuit, a T-line power supply current detector, a T-line power supply voltage detector,
Output of T-line power supply current detection unit and detection of T-line power supply voltage
A loop detection method in a subscriber circuit of an exchange, comprising: an adder for generating a sum of outputs from the adders , and comparing a value generated from the adder with a designated threshold to output a loop detection signal.
【請求項3】 請求項1または2の何れかにおいて, 前記加算部の 後段に誘導交流成分を減衰させるフィルタ
を設け,同相交流信号による誤検出を防止することを特
徴とする交換機の加入者回路におけるループ検出方式。
3. The subscriber circuit of an exchange according to claim 1 , wherein a filter for attenuating an induced AC component is provided at a stage subsequent to said adding section to prevent erroneous detection by an in-phase AC signal. Loop detection method.
【請求項4】 加入者線のT線とR線にそれぞれ接続さ
れたT線側給電回路とR線側給電回路を備えた交換機の
加入者回路において, T線の給電電圧検出部とR線の給電電流検出部及び前記
T線の給電電圧検出部の出力とR線の給電電流検出部の
出力の和を発生する加算部を設け,前記加算部から発生
する値を指定された閾値と比較してループ検出信号を出
力することを特徴とする交換機の加入者回路におけるル
ープ検出方式。
4. A subscriber line connected to a T line and an R line, respectively.
Of an exchange equipped with a T-line feed circuit and an R-line feed circuit
In the subscriber circuit, a T-line feed voltage detecting unit, an R-line feed current detecting unit,
The output of the power supply voltage detector of the T line and the power supply current detector of the R line
An addition unit for generating a sum of the outputs provided, generated from the addition unit
Lulu put the subscriber circuit of the exchange, characterized in that as compared with the specified value of threshold and outputs a loop detection signal <br/>-loop detection method.
【請求項5】 加入者線のT線とR線にそれぞれ接続さ
れたT線側給電回路とR線側給電回路を備えた交換機の
加入者回路において, T線の給電電流検出部とR線の給電電圧検出部及び前記
T線の給電電流検出部の出力とR線の給電電圧検出部の
出力の和を発生する加算部を設け,前記加算部から発生
する値を指定された閾値と比較してループ検出信号を出
力することを特徴とする交換機の加入者回路におけるル
ープ検出方式。
5. A subscriber line connected to a T line and an R line, respectively.
Of an exchange equipped with a T-line feed circuit and an R-line feed circuit
In the subscriber circuit, a T-line feed current detecting unit, an R-line feed voltage detecting unit,
The output of the feed current detector of the T line and the feed voltage detector of the R line
An addition unit for generating a sum of the outputs provided, generated from the addition unit
A loop detection method in a subscriber circuit of an exchange, wherein a loop detection signal is output by comparing a value to be performed with a specified threshold value.
【請求項6】 加入者線のT線とR線にそれぞれ接続さ
れたT線側給電回路とR線側給電回路を備えた交換機の
加入者回路において, T線の給電電流検出部とR線の給電電流検出部及び前記
T線の給電電流検出部の出力とR線の給電電流検出部の
出力の和を発生する給電電流の和検出部と, T線の給電電圧検出部とR線の給電電圧検出部及び前記
T線の給電電圧検出部の出力とR線の給電電圧検出部の
出力の和を発生する給電電圧の和検出部と,前記給電電流の和検出部と前記給電電圧の和検出部の
つの回路の出力の和を発生する加算部とを設け,前記加
算部から発生する値を指定された閾値と比較してループ
検出信号を出力することを特徴とする交換機の加入者回
路におけるループ検出方式。
6. A subscriber line connected to a T line and an R line, respectively.
Of an exchange equipped with a T-line feed circuit and an R-line feed circuit
In the subscriber circuit, a T-line feed current detecting unit, an R-line feed current detecting unit,
The output of the T line feed current detector and the output of the R line feed current detector
A power supply current sum detector for generating a sum of outputs , a T line power supply voltage detector, an R line power supply voltage detector, and
The output of the T-line power supply voltage detector and the R-line power supply voltage detector
A power supply voltage sum detector that generates a sum of outputs, a power supply current sum detector, and a power supply voltage sum detector.
One of providing an addition unit for generating a sum of the output of the circuit, the pressurized
A loop detection method in a subscriber circuit of an exchange, wherein a loop detection signal is output by comparing a value generated by a calculation unit with a specified threshold value.
JP23145493A 1993-09-17 1993-09-17 A loop detection method in the subscriber circuit of the exchange. Expired - Fee Related JP3322731B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23145493A JP3322731B2 (en) 1993-09-17 1993-09-17 A loop detection method in the subscriber circuit of the exchange.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23145493A JP3322731B2 (en) 1993-09-17 1993-09-17 A loop detection method in the subscriber circuit of the exchange.

Publications (2)

Publication Number Publication Date
JPH0787534A JPH0787534A (en) 1995-03-31
JP3322731B2 true JP3322731B2 (en) 2002-09-09

Family

ID=16923776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23145493A Expired - Fee Related JP3322731B2 (en) 1993-09-17 1993-09-17 A loop detection method in the subscriber circuit of the exchange.

Country Status (1)

Country Link
JP (1) JP3322731B2 (en)

Also Published As

Publication number Publication date
JPH0787534A (en) 1995-03-31

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