JP3321265B2 - Communication processing apparatus and debugging method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debugging technique for a communication processing apparatus, and more particularly to an exchange, a private branch exchange (PBX), and the like.
xchange), a digital communication processing device that realizes a network such as a LAN (Local Area Network), and the like, using a high-level data link control procedure (HDLC).
The present invention relates to a communication processing device which is suitable for a verification of a control device incorporating a protocol having an error detection function such as es) or a protocol analyzer for checking these devices, and a technique effective when applied to a debugging method thereof.

[0002]

2. Description of the Related Art For example, in a communication processing apparatus for realizing a network, a message format (frame) used in the HDLC protocol has an address portion, an information portion surrounded by start and stop flags of the same pattern as shown in FIG. It is composed of an FCS (Frame Check Sequence) section, and a CRC (Cyclic Redundancy Check) calculation result is sent out as FCS section data. In most recent communication processing apparatuses, the flag section and the FCS section are realized by hardware in most cases. .

As a known example corresponding to a wide range of protocols, a communication microprocessor HD64 manufactured by Hitachi, Ltd. as shown in a transmission block diagram in FIG.
180S (hereinafter referred to as NPU), and the MSCI transmitting unit of the multiprotocol serial communication interface (MSCI) unit is a FIFO (Fi
It has a three-stage transmission buffer (rst-in first-out) format and one transmission shift register. This transmission unit has a built-in function to support protocols such as a CRC calculator and an error check function. . For this CRC,
It is possible to select two types of CRC codes, CRC-16 and CRC-CCITT, and all initial values "1" and "0".

[0004]

However, in the above-mentioned multi-protocol compatible communication processing apparatus, C
It is possible to generate an error frame by changing the RC code. However, in the case of a processing device specialized in functions such as HDLC, CRC is automatically generated, and an error frame cannot be generated intentionally.

That is, when debugging a protocol process using a communication processing device, there is a case where an error frame is required to be generated and checked reliably. When a transmission process is performed using the device having the above-described configuration, selection of a CRC is required. It is considered that a protocol conforming to the adopted protocol is set in the initialization process and is not changed.

Therefore, in order to cause an error in the specified frame, it is necessary to set a different CRC mode after confirming that the frame has not been transmitted and to return after confirming the end of the transmission. In the case of the processing device described above, since a CRC error cannot be intentionally generated, a situation for verifying the protocol processing cannot be reliably created.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a communication processing apparatus capable of causing an error in an intended frame without confirming a transmission state and verifying a protocol reliably, and a debugging method thereof. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the communication processing apparatus of the present invention is a communication processing apparatus for realizing a network by a protocol, and generates an initial value data for CRC calculation when generating a CRC check code used for error detection in serial communication processing. Setting control means for setting the initial value data to an abnormal initial value for each frame transmission, storage means for holding initial value selection information, and selection control means for selecting initial value data based on the initial value selection information. It is provided.

Further, according to the debugging method of the communication processing apparatus of the present invention, the initial value data for CRC calculation is set to an abnormal initial value every frame transmission, and the selection of the initial value data is controlled and specified by the initial value selection information. In this case, a CRC error is generated in the transmission frame, and the verification of the protocol processing caused by the error is realized.

In this case, the control for generating a CRC error of the communication processing apparatus is not performed by selecting the initialization data, but is performed when the CRC transmission request information is requested.
A set value is selected, and the CRC transmission request information is changed to an abnormal value to cause an error in a specific transmission frame.

Further, information for selecting whether the CRC is normal or abnormal is set in a storage means in advance, and this information is fetched and selected at the time of execution of transmission processing.

[0014]

According to the communication processing apparatus and the debugging method thereof, the initial value data for CRC calculation, the setting control means, the storage means, and the selection control means are provided.
Initial value selection information for designating normal / abnormal CRC can be set, a CRC error can be generated in a specific transmission frame, and an error frame can be generated.

That is, the initial value of the CRC shift register used for the CRC calculation can be set in a normal case or an abnormal case. The data is also fetched at the time of data fetching, and the initial value selection information is referred to each time frame transmission is started. By selecting the CRC initial value, an error can be generated in a specific frame.

[0016] In addition, a normal / abnormal CRC can be set, the data is also taken in at the time of taking in the data, and an error is generated in a specific frame by changing the CRC control by referring to the CRC sending request information every frame sending. Can be done.

In this CRC control, an initial value of a CRC shift register used for error check data calculation can be set in a normal case and an abnormal case, and a method of selecting a CRC initial value or referring to a set value when a CRC output request is made. And changing the output signal.

In such a case, the initial value selection information is set before writing the head data of the frame, is simultaneously fetched when the data is fetched into the buffer, and holds the data until the start of frame transmission. Furthermore, the start of frame transmission is detected, and the CRC initial value is set with reference to the initial value selection information held when the CRC data is initialized.

Then, after transmitting the address part and the information part,
Whether to automatically send the calculated CRC as FCS part,
Alternatively, an error can be generated by referring to the calculated CRC data at the time of sending it out as an FCS unit and changing the output signal. In the case of a method described as a descriptor in the storage means, it can be realized by having CRC setting information and adding control for setting.

Thus, an error can be generated in a specific frame without confirming whether a frame is being transmitted or not, so that the protocol can be reliably verified and the protocol processing can be easily verified. Since it can be realized, the efficiency of protocol verification work can be improved.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a main part of a communication processing apparatus according to a first embodiment of the present invention. FIG. 2 shows a communication processing apparatus according to this embodiment in which a CRC calculator is changed by changing an initial value. It is a block diagram showing the case of realizing.

First, the main configuration of the communication processing apparatus of this embodiment will be described with reference to FIG.

The communication processing device of the present embodiment is, for example, an HD
An internal data bus 1 for setting data from the CPU, a CRC selection register 2 for setting selection of initial value data, and a transmission data stored in a FIFO format. A transmission buffer 3, a CRC buffer 4 for storing a CRC initial value in a similar FIFO format, a transmission shift register 6 for outputting transmission data from lower bits to a transmission output terminal 5, a CRC for calculating a CRC to be added to a frame Calculator 7, TX pattern register 8 for sending start flag, stop flag, etc., "0" required for HDLC protocol
An insertion unit 9 includes a state transition control unit 10 for sequentially controlling transmission according to a frame format.

That is, the difference from the transmission unit of the ordinary communication processing device is that the C for specifying and holding the CRC is set.
RC selection register 2, CRC buffer 4, and CRC
A selection signal (initial value selection information) 11 for notifying the information of the buffer 4 to the CRC calculator 7, similarly, a flag transmission signal 12 for notifying the transmission of the start and stop flags 12
Is provided.

As shown in FIG. 2, the CRC calculator 7 has a CRC shift register 71 for holding input data.
And a CRC initialization data section 7 for holding initial value data for CRC calculation set in the CRC shift register 71.
2, the initial value data is set to an abnormal initial value for each frame transmission, the selection signal 11 is held in a flip-flop circuit (storage means), and a selection signal control unit (setting , Selection control means) 73, and the CRC to be added to the frame is calculated.

Next, the operation of this embodiment will be described.

First, when a frame data transmission request occurs, the CPU sets the CRC selection register 2 via the internal data bus 1 and selects a normal frame or an abnormal frame. At this time, when transmitting the same frame type as the previous time, there is no need to set.

After the selection of the initial value is completed, the transmission data is written into the transmission buffer 3. At this time,
At the same time, the contents of the CRC selection register 2 are stored in the CRC buffer 4
Take in. When the transmission buffer 3 is of the FIFO format, the CRC buffer 4 also has the same number of FIFOs.

Further, the contents of the transmission buffer 3 are sequentially sent to the transmission shift register 6, while the contents of the CRC buffer 4 are output as a selection signal 11. Therefore, the content of the CRC selection register 2 one byte before is reflected on the selection signal 11. In this embodiment, the CRC calculator 7
And its initialization control.

When the data at the head of the frame is transferred from the transmission buffer 3 to the transmission shift register 6, or when the transfer of one frame is completed and the next frame is transmitted, the start flag is transmitted from the TX pattern register 8. Is sent. This start flag transmission is notified to the CRC calculator 7 as the flag transmission signal 12, and the initialization processing can be changed.

Further, the transmission data of the transmission shift register 6 is also input to the CRC calculator 7 shown in FIG. 2 on a bit-by-bit basis, and this input data is transmitted through the CRC shift register 71 while performing the EOR operation using the designated bits. Shift right. When the CRC calculation method is different, the EOR operation position is different.

At this time, the initial value data of the CRC initialization data section 72 is all "1" in the case of the HDLC control, and the CRC shift register 71 sets the initial value every time the start flag is sent out. Is output to the transmission output terminal 5 following transmission of the information section. In this embodiment, normal / abnormal control is performed by inverting bit 7 of the CRC initial value.

Further, the initial value selection information can be designated by a program by providing a register or the like, and the designated result is used to control the selection signal control unit 73 by the selection signal 11. At this time, actually, the start flag transmission signal 12
At the timing of.

Therefore, according to the communication processing apparatus of the present embodiment, the CRC calculator 7 stores the CRC initialization data section 72 for storing the initial value data for CRC calculation, and the selection signal 11 for storing the initial value data. And a selection signal control unit 73 for selecting the initial value of the CRC shift register 71 used for the CRC calculation can be set in a normal case or an abnormal case. By selecting the CRC initial value with reference to the selection signal 11 and generating an error in a specific transmission frame, an error frame can be generated.

(Embodiment 2) FIG. 3 is a configuration diagram showing a case where output data at the time of a CRC output request is inverted in a communication processing apparatus according to Embodiment 2 of the present invention.

As in the first embodiment, the communication processing apparatus of this embodiment has a transmission unit of the communication processing apparatus specialized for the HDLC protocol, and calculates the CRC to be added to the frame.
It is composed of a calculator 7a and the like.
Normal / abnormal CR by changing CRC initialization data
This is different from the first embodiment in which C can be selected, in that an error is generated by inverting output data at the time of CRC output.

That is, the CRC calculator 7a of this embodiment
Is a C for holding the input data, as shown in FIG.
An RC shift register 71, a selection signal controller 73a for holding a selection signal 11 as initial value selection information in a flip-flop and selecting a CRC set value when a CRC transmission signal (CRC transmission request information) 13 is requested; Signal 13
And a transmission data control unit 74 that changes the value to an abnormal value.
The output data is inverted by the selection signal 11 when the CRC transmission signal 13 is requested.

Next, the operation of this embodiment will be described.

First, the input data is shifted to the right in the CRC shift register 71 while performing the EOR operation, and when the transfer of the information section is completed, the state transition control section 10 prompts the transmission of the FCS section and transmits the CRC transmission signal. 13 is notified to the CRC calculator 7a. Then, in response to this request, the CRC calculator 7a outputs while shifting the upper bits of the CRC shift register 71 to the left.

Further, the selection signal 11 specified in the same manner as in the first embodiment is a CRC transmission signal 13 which is a CRC transmission request.
And sent to the transmission data control unit 74.
At this time, when the selection signal 11 is “1”, the transmission data control unit 74 outputs the data of the CRC shift register 71 as it is. However, when the selection signal 11 is changed to "0", the output data is inverted, which may cause a CRC error.

Therefore, according to the communication processing apparatus of this embodiment, the CRC calculator 7a stores the selection signal 11 to select the initial value data and the selection signal control unit 73a, Transmission data control unit 74 to change to
Since the output data can be inverted with reference to the CRC transmission signal 13 every frame transmission, an error can be generated in a specific transmission frame as in the first embodiment to generate an error frame. Becomes

(Embodiment 3) FIG. 4 is a block diagram showing a case where output data at the time of a CRC output request is changed in a communication processing apparatus according to Embodiment 3 of the present invention.

The communication processing apparatus of the present embodiment has a transmission unit of a communication processing apparatus specialized for the HDLC protocol similarly to the first and second embodiments, and includes a CRC calculator 7b for calculating a CRC to be added to a frame. The second embodiment is different from the first embodiment in that output data is changed at the time of CRC output. The second embodiment is different from the second embodiment in that the output data is inverted. The difference is that an error is generated by directly changing the bit of the shift register 71.

That is, the CRC calculator 7b of this embodiment
Is a C for holding input data, as shown in FIG.
An RC shift register 71, a selection signal controller 73b for holding a selection signal 11 as initial value selection information in a flip-flop, and selecting a CRC setting value when requesting a CRC transmission signal 13 as CRC transmission request information; And a selector 75 for selecting output data by the selector 11.

Further, outside the CRC calculator 7b, a setting CRC shift register 14 connected to the selector 75 of the CRC calculator 7b for outputting arbitrary data as a CRC is provided, and connected to the CPU by the internal data bus 1. Thus, the CRC data can be set arbitrarily.

Thus, the selector 75 is controlled by the control of the selection signal 11, and the output data is selected. At this time, if the selection signal 11 is “1”, the contents of the CRC shift register 71 in which the result of the normal operation is stored are output.
Is output as CRC data, thereby changing the output data and generating a CRC error.

Therefore, according to the communication processing apparatus of the present embodiment, the setting CRC shift register 14 which is connected to the selector 75 of the CRC calculator 7b and outputs arbitrary data as a CRC is provided, so that every time a frame is transmitted, C
Since output data can be changed with reference to the RC transmission signal 13, an error can be generated in a specific transmission frame as in the first and second embodiments to generate an error frame.

(Embodiment 4) A communication processing apparatus according to Embodiment 4 of the present invention differs from Embodiments 1 to 3 in that
rect Memory Access Controller), and is applied to a communication processing device having an automatic setting control function of a chain method using a chain method.
The use of automatic setting control called the chain method that uses a network is increasing, and these methods are realized by storing transfer data information in a predetermined format in a memory and starting up after setting the storage address. ing.

Therefore, in this embodiment, CRC selection information is added as transfer data information to a communication processing apparatus having an automatic setting control function, and the information is automatically set before data transfer by DMAC by setting the information in a memory in advance. This can be achieved by:

Therefore, according to the communication processing apparatus of the present embodiment, by adding the CRC selection information as the transfer data information to the communication processing apparatus having the automatic setting control function, the control of the DMAC is more complicated than in the first embodiment. However, since processing can be left to the DMAC, program processing can be easily performed.

As described above, the invention made by the inventor has been specifically described based on the first to fourth embodiments. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, the communication processing apparatus of the above-described embodiment has been described in the case where the transmission buffer 3 and the CRC buffer 4 of the FIFO format are provided, but the present invention is not limited to the above-described embodiment. The basic configuration and operation are not changed in this case.

Further, even when the bits of the CRC shift register 71 are changed as in the third embodiment, an error can be generated by changing or inverting a designated bit instead of all the bits. .

In the above description, the case where the invention made mainly by the present inventor is applied to a communication processing apparatus specialized in the HDLC protocol, which is a field of use, has been described. However, the present invention is not limited to this. The present invention is also widely applicable to communication processing devices that implement other networks that perform checks.

[0056]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, when generating a CRC check code used for detecting an error in the serial communication processing, the CR
Initial value data for C calculation, setting control means for setting the initial value data to an abnormal initial value for each frame transmission, storage means for holding initial value selection information, and initial value data based on the initial value selection information. By providing selection control means for selecting, it is possible to set initial value selection information for designating normal / abnormal CRC and to generate a CRC error in a specific transmission frame, so that an error frame can be reliably generated. It is possible to do.

As a result, an error can be generated in a specific frame without confirming whether or not the frame is being transmitted, so that the protocol can be reliably verified and the protocol processing can be easily verified. Therefore, it is possible to obtain a method of debugging a communication processing device that can improve the efficiency of protocol verification work.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main part of a communication processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a case where a CRC calculator is realized by changing an initial value in the communication processing device of the present embodiment.

FIG. 3 is a configuration diagram showing a case in which output data at the time of a CRC output request is inverted in the communication processing apparatus according to the second embodiment of the present invention.

FIG. 4 is a configuration diagram showing a case where output data at the time of a CRC output request is changed in the communication processing apparatus according to the third embodiment of the present invention.

FIG. 5 illustrates a communication processing apparatus as an example of the related art.
FIG. 4 is an explanatory diagram showing a format of an HDLC frame.

FIG. 6 is a block diagram illustrating a transmission unit of a communication processing device that is an example of the related art.

[Explanation of symbols]

Reference Signs List 1 internal data bus 2 CRC selection register 3 transmission buffer 4 CRC buffer 5 transmission output terminal 6 transmission shift register 7, 7a, 7b CRC calculator 8 TX pattern register 9 "0" insertion unit 10 state transition control unit 11 selection signal (initial Value selection information) 12 flag transmission signal 13 CRC transmission signal (CRC transmission request information) 14 setting CRC shift register 71 CRC shift register 72 CRC initialization data section 73, 73a, 73b selection signal control section (setting, selection control means) 74 Transmission data control unit 75 Selector

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-364620 (JP, A) JP-A-6-177864 (JP, A) JP-A-6-85793 (JP, A) JP-A-2- 179043 (JP, A) JP-A-63-224447 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 29/14 H04L 12/26 G06F 11/10 330 G06F 13/00 353 H04L 1/00

Claims (5)

(57) [Claims] 1. A communication processing device for realizing a network by a protocol, comprising: generating a CRC check code used for detecting an error in serial communication processing;
Initial value data for RC calculation, setting control means for setting the initial value data to an abnormal initial value for each frame transmission, storage means for holding initial value selection information, and the initial value data according to the initial value selection information. And a selection control means for selecting the communication processing. 2. Use for detecting errors in serial communication processing.
For CRC calculation when generating CRC check code
Initial value data and the initial value data for each frame transmission.
Setting control means for setting an abnormal initial value and initial value selection information
And a storage unit for storing the initial value according to the initial value selection information.
Selection control means for selecting term value data;
A method for debugging a communication processing device that realizes a network by using a default setting, wherein initial value data for the CRC calculation is set to an abnormal initial value every frame transmission, and selection of the initial value data is controlled by the initial value selection information. And send a CRC to a specific transmission frame.
A method for debugging a communication processing device, wherein an error is generated and verification of protocol processing caused by the error is realized. 3. The debugging method for a communication processing device according to claim 2, wherein control for generating a CRC error in said communication processing device is performed by using initial value data for said CRC calculation.
Instead of setting an abnormal initial value every frame transmission
A method for inverting output data at the time of CRC output to generate an error in a specific transmission frame. 4. The debugging method for a communication processing device according to claim 2, wherein information for selecting whether the CRC is normal or abnormal is set in a storage unit in advance, and the information is taken in at the time of executing a transmission process. A debugging method for a communication processing device, wherein the debugging method is selected. (5) Frame initial value data for CRC calculation
Setting control means for setting an abnormal initial value for each transmission, and an initial value
Storage means for holding the selection information;
Selection control means for selecting the initial value data.
Characterized by Communication processing device.