JP3318948B2 - Video camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera, and more particularly, to a video camera having a circuit for reducing flicker.

[0002]

2. Description of the Related Art When a vertical synchronizing signal frequency is 60 Hz, N
When a subject is photographed using a TSC video camera under fluorescent lamp lighting using an AC power supply of 50 Hz and the image is reproduced on a television or the like, the screen may flicker. This is caused by the difference between the vertical synchronization signal frequency of the video camera and the power frequency of the fluorescent lamp,
This is generally called a flicker phenomenon.

FIG. 5 is a block diagram of a video camera including a flicker reduction circuit as a means for eliminating the flicker phenomenon. The flicker reduction circuit includes a flicker component detection circuit 73 and a phase component circuit 75.
In FIG. 5, a light source is incident on a lens 51. This light source forms an image on the light receiving surface of the CCD image sensor 53 as an image signal, and is supplied to the AGC amplifier 55. The output gain of the AGC amplifier 55 is controlled by a D / A converter 7 described later.
1 is set. An image signal output from the AGC amplifier 55 is supplied to an A / D converter 57 and digitized. This digital signal is supplied to a signal processing circuit 59.
And supplied to the detection circuit 61. A predetermined process is performed on the digital signal by the signal processing circuit 59, and thereafter, the digital signal is extracted from the output terminal 60.

The digital signal detected by the detection circuit 61 is supplied to a comparator 63 and a flicker component detection circuit 7.
3 is supplied. The comparator 63 is supplied with a reference level from a reference level input terminal 65. The comparator 63 compares the detected digital signal with the reference level, and compares the detected value with the adder / subtractor 6.
7 is supplied. The flicker component detection circuit 73 detects the frequency band of the flicker component included in the supplied signal, and the flicker component is supplied to the addition / subtraction calculator 67 via the phase integration circuit 75.

The adder / subtractor 67 adds / subtracts the output signal of the phase integrator 75 to / from the output signal of the comparator 63. From the output signal of the addition / subtraction operation unit 67, the control amount operation unit 69 calculates the gain control amount of the AGC amplifier 55 according to the imaging signal level and the flicker component signal level. The output signal of the control amount calculator 69 is D /
The signal is converted into an analog signal by the A converter 71 and supplied to the AGC amplifier 55. As described above, the AGC amplifier 5
The gain of 5 is controlled by an analog signal supplied from the D / A converter 71.

FIG. 6 is a waveform diagram related to the flicker reduction circuit in FIG. FIG. 6A is a waveform diagram of an imaging signal (light amount) when the power frequency of the fluorescent lamp is 50 Hz, and one cycle is 20 ms. FIG. 6B shows an integrated value when the light quantity at 50 Hz is sampled at 60 Hz.
Time _T 0 ~T ₁ is a 16.6ms. FIG. 6B
The average value of the imaging signal in FIG. 6A is shown between the dotted line and the procedure level on the horizontal axis. FIG. 6C shows the difference between the average value and the integrated value.
A waveform diagram as shown in FIG. This waveform causes a flicker phenomenon, which causes the screen to flicker. The flicker component that causes the flicker phenomenon is the least common multiple (20H) on the time axis between the vertical synchronization frequency of the video camera and the power supply frequency of the fluorescent lamp.
The periods coincide with each other in z), and are thereafter repeated in the same period. That is, in a video camera, the time T
₀ ~T _{3, T 3} will be repeated at 3V period of through T _6.

[0007]

The occurrence of the flicker phenomenon is eliminated by the flicker reduction circuit comprising the flicker component detection circuit and the phase integration circuit. The flicker reduction circuit is
A flicker component is detected for an input signal in a steady state. However, since the flicker reduction circuit has the characteristics of a band-pass filter in which the peak of the frequency of the flicker component is set, in a transient state (for example, a sharp change in brightness) in which an impulse-like signal is input,
An image pickup signal having the same frequency component as the flicker component included in the input signal is also detected.

As described above, components other than the flicker component are output to the phase component circuit, and the output signal of the adder / subtractor increases due to this component. The level of the unnecessary signal component is often considerably larger than the originally required flicker component, and as a result, the gain of the AGC amplifier is modulated more than necessary, which adversely affects the video signal.

Accordingly, it is an object of the present invention to prevent a signal having the same frequency component as a flicker component from being supplied to a phase integrator circuit, thereby preventing an influence on a video output signal in a transient state and a steady state. It is an object of the present invention to provide a video camera having a flicker reduction circuit capable of maintaining the characteristics of flicker reduction in the above.

[0010]

SUMMARY OF THE INVENTION The present invention relates to a video camera having a flicker reduction circuit, a flicker component detection circuit for detecting a flicker component, a limiter circuit to which an output signal of the flicker component detection circuit is supplied, A video camera comprising a phase integration circuit to which an output signal of a limiter circuit is supplied.

[0011]

A limiter circuit is inserted between the flicker component detection circuit and the phase integration circuit. This limiter circuit prevents an imaging signal having the same or similar frequency as the flicker component from being supplied to the phase integration circuit.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a video camera to which a flicker reduction circuit according to the present invention is applied will be described with reference to the drawings. FIG. 1 is a block diagram of a video camera according to a first embodiment of the present invention. It is assumed that the flicker reduction circuit includes a flicker component detection circuit, a limiter circuit, and a phase integration circuit.

In FIG. 1, a light source enters a lens 1. The light source forms an image on the light receiving surface of the CCD image sensor 3 as an image signal, and is supplied to the AGC amplifier 5. A
The output gain of the GC amplifier 5 is set by a D / A converter 23 described later. An image signal output from the AGC amplifier 5 is supplied to an A / D converter 7 and digitized. This digital signal is supplied to the signal processing circuit 9 and the detection circuit 13. The digital signal is subjected to predetermined processing by the signal processing circuit 9 and is taken out from the output terminal 11.

The digital signal detected by the detection circuit 13 is supplied to a comparator 15 and a flicker component detection circuit 2.
5 is supplied. The reference level is supplied to the comparator 15 from the reference level input terminal 17. The comparator 15 compares the detected digital signal with the reference level, and compares the detected value with the adder / subtractor 1.
9.

The flicker component detection circuit 25 detects the frequency band of the flicker component contained in the supplied signal,
The flicker component is supplied to the limiter circuit 27. The output signal of the flicker component detection circuit 25 is supplied to a phase integration circuit 29 after being limited by a limiter circuit 27. The output signal of the phase integration circuit 29 is supplied to the addition calculator 19.

In the adder / subtractor 19, the signal from the phase integrator 29 is added to the signal from the comparator 15.
Is subtracted. The output signal of the addition / subtraction operation unit 19 is supplied to a gain control amount operation unit 21 of the AGC amplifier 5, and the gain control amount of the AGC amplifier according to the image signal level and the flicker component signal level is calculated. This operation output signal is supplied to the D / A converter 23, and after being converted into an analog signal, is supplied to the AGC circuit 5. The gain of the AGC circuit 5 is controlled according to the supplied gain control amount.

FIG. 2 is a detailed block diagram of a flicker reduction circuit including a flicker component detection circuit 25, a limiter circuit 27, and a phase integration circuit 29. In FIG. 2, a flicker component detection circuit 25 is a digital filter.
Memory 31, adder 33, subtractor 35 and multiplier 3
Consists of seven.

The digital filter memory 31 of the flicker component detection circuit 25 has three memories 31a, 31b and 31c.
, Each of which holds an input value of 1 V before the input signal. Digital filter memory 31a
Are connected in series to the digital filter memories 31b and 31c. The output signal of each digital filter memory is added by the adder 33. The output signal of the digital filter 31b is multiplied by the multiplier 37 three times. The addition value of the adder 33 and the multiplication value of the multiplier 37 are subtracted in the subtractor 35. This subtraction value is supplied to the limiter circuit 27. In the limiter circuit 27,
The large amplitude 20 Hz component is limited.

The output value from the limiter circuit 27 is supplied to an adder 39 of the phase integration circuit 29. The phase integration circuit 29 includes an adder 39, a multiplier 41, and a digital filter memory 43. The output value of the adder 39 is supplied to the digital filter memory 43.
The digital filter memory 43 comprises three stages of digital filter memories 43a, 43b and 43c connected in series. Each of the digital filters 43 holds the input value 1 V before the input signal. The output value from the digital filter memory 43 c is multiplied by a constant k in a multiplier 41 and supplied to an adder 39. The output value of the adder 39 is supplied to the addition / subtraction unit 19.

Assuming that the output value of the detection circuit 13 is X and the output value of the flicker reduction circuit is Y, the characteristics of the flicker reduction circuit are as follows.

It is represented by the following equation.

That is, a flicker component is detected by the flicker component detection circuit 25, and the phase of the detected value is adjusted by a phase integrator at a cycle of 3 V (20 Hz), and the flicker component is integrated. For example, when the angle of view of the video camera is switched from a light source having no flicker phenomenon to a light source that generates flicker, a large amount of flicker is detected by the flicker component detection circuit 25 in the first part. the value of the filter 43 becomes 0
Have . However, since the flicker is gradually reduced, the detection value of the flicker component detection circuit 25 returns to the reference level,
Also, the digital filter memory of the phase integration circuit 29
Value of over 43 approaches the output value to reduce flicker.

At the time of general photographing, the flicker phenomenon is reduced by the above relationship. FIG. 3 shows the characteristics of the flicker reduction circuit. As is clear from FIG. 3, the flicker reduction circuit is a band-pass filter having a peak value at 20 Hz. For this reason, when the output of the detection circuit, that is, the input signal of the flicker component detection circuit 25 includes an input signal including a 20 Hz component other than the flicker component depending on the shooting situation, the flicker reduction circuit having the characteristic shown in FIG. In this case, it is impossible to remove this input signal. Therefore, it affects the gain control output of the AGC amplifier. However, as shown in FIG.
By arranging the limiter circuit 27 between the flicker component detection circuit 25 and the phase integration circuit 29, the imaging signal including the 20 Hz component other than the flicker component is supplied to the phase integration circuit 29.
I try not to be supplied much . Therefore, AGC
An appropriate gain control signal can be supplied to the amplifier 5. In addition, it is clear from the above description that the flicker component generated every 3V cycle is supplied to the phase integration circuit 29.

FIG. 4 shows an output waveform diagram of the flicker component reduction circuit in FIG. 4A shows the flicker component detection circuit 25, and FIG. 4B shows the limiter circuit 27.
FIG. 4C is an output waveform diagram when the flicker reduction of the phase integrator 29 is started. The flicker component detected by the flicker component detection circuit 25 is supplied to a limiter circuit 27. FIG. 4A
, The range indicated by the dotted line centered on the reference level 0 is the limiter set value of the limiter circuit 27, which is smaller than the conventional set value. A range A indicated by a shaded line is a 20 Hz component (which is a frequency component of the image signal) other than the flicker component. Impulsive 2
When an image signal including a 0 Hz component is input, the limiter circuit 27 limits the 20 Hz component of the image signal. Therefore, the output waveform of the limiter circuit 27 is as shown in FIG.
It looks like B. Accordingly, as shown in FIG. 4C, the input level to the phase integration circuit 29 is the same as the conventional level, and it is possible to control the output of the AGC amplifier 5, that is, to limit the influence on the video signal. Become.

[0024]

According to the present invention, by inserting a limiter circuit between the flicker component detection circuit and the phase integrator circuit, an imaging signal having the same frequency or an approximate frequency as the flicker component, which is generated in a transient state, is generated. It is possible to minimize supply to the phase integration circuit. Further, the conventional flicker component is supplied to the phase integration circuit in the same manner as before.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video camera according to a first embodiment of the present invention.

FIG. 2 is a detailed block diagram of a flicker reduction circuit.

FIG. 3 is a diagram illustrating characteristics of a flicker reduction circuit.

FIG. 4 is an output waveform diagram of a flicker component reduction circuit.

FIG. 5 is a block diagram for explaining a conventional technique.

FIG. 6 is a waveform diagram related to a conventional flicker reduction circuit.

[Explanation of symbols]

 25 Flicker component detection circuit 27 Limiter circuit 29 Phase integration circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/217 H04N 5/335

Claims (1)

(57) [Claims] 1. A video camera having a flicker reduction circuit, wherein the flicker reduction circuit comprises: a flicker component detection unit for detecting a flicker component; a limiter to which an output signal of the flicker component detection unit is supplied; Phase integration means to which the output of
Video camera, characterized in that that.