JP3318786B2 - Multi-chip module structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a multi-chip module in which a central processing unit of an information processing device such as an engineering workstation or a personal computer is integrated with a semiconductor main storage device around the central processing unit.

[0002]

2. Description of the Related Art Conventionally, in the process of configuring an LSI module, when a semiconductor chip is mounted on a bare chip and a defective chip is confirmed in a subsequent burn-in test, it is necessary to replace the defective chip by repair.

[0003] For example, in the case of mounting using a flip chip, replacement of the chip requires advanced technology, and the man-hour thereof becomes enormous.

[0004] Further, in the case of replacing a chip in response to a failure occurring after shipment of an LSI module, the user is required to pay a high repair cost for the above-described reason.

Therefore, a test for confirming the operation of the semiconductor chip can be performed in advance with the wafer being lifted. In this case, the wafer check (Wafer
A device for performing such a check is required. However, in order to manufacture such a wafer check device, advanced technology is required, and therefore, the device is expensive and the number of times the probe portion can be used is low.

That is, a large investment and a large amount of labor are required to perform a test of a semiconductor chip in an ascending wafer state.

Furthermore, if the pads of the LSI module are damaged during this test, the reliability after flip-chip solder reflow may be greatly affected.

[0008] Therefore, as shown in FIG.
An LSI module in which an MPU (MPU block) 91, a controller (controller block) 92, and memories (memory blocks) 93 to 95 are formed on the device 6 is known.

Here, according to the prior art shown in FIG.
By setting one of the memory blocks 93 to 95 as a redundant memory block, for example, when any of the other memory blocks fails,
In this way, alternative relief is performed to improve the overall yield.

[0010]

By the way, assuming that the yield of memory is 98%, for example,
When a large number of memory chips are mounted, the probability that all the chips operate normally is 0.98 ²⁰ ≒ 0.67
(= 67%). Further, the yield is, for example, 95
%, 80%, the probability that all chips operate normally is approximately 36%, 1.2%.

The above-mentioned LSI module is composed of one wafer, and further, since a redundant memory is mounted on the wafer, that is, a large number of memories are mounted.
There has been a problem that the cost is increased due to a decrease in the yield.

That is, on a wafer scale as shown in FIG.
When integrating a PU, a controller, and a large number of memory blocks, the MPU block generally requires various logic components of tens to hundreds of thousands of gates,
The probability that there is no defect in the MPU block is considerably low. If the operation of the MPU block is defective,
Even if only the memory blocks are rescued, the entire LSI module is not rescued, and the profitability of the LSI module is inevitably reduced.

The present invention has been made in view of such circumstances, and provides a low-cost and highly reliable module.

[0014]

The structure of the multi-chip module according to the present invention comprises an SRAM Si substrate 1 as one wafer-level substrate layer in which a memory having a redundant capacity is integrated, For example, polyimide insulating film 18
And the like, a Cu / polyimide multilayer wiring section 2 as a wiring layer in which conductors such as Cu wiring 16 are combined in multiple layers, a processor unit such as MPU4, and a connection between the memory of the substrate layer and the MPU4. Switch,
For example, an integrated circuit layer (for example, a layer composed of the address decoder / controller 3 and the MPU 4) on which a switching unit such as an address decoder / controller 3 is formed.
The address decoder / controller 3 and the MPU 4 are formed on the Si substrate 1 and are hybridized on the Cu / polyimide multilayer wiring section 2.

According to a second aspect of the present invention, there is provided a multi-chip module having an integrated circuit layer in which a processor unit is formed, a memory having a redundant capacity, and a switching unit for switching a connection between the processor unit and the memory in the integrated circuit layer. And a wiring layer in which an insulator and a conductor are combined in multiple layers. The wiring layer is formed on the substrate layer, and the integrated circuit layer is formed by wiring. It is characterized in that it is configured as a hybrid on the upper part of the layer.

The structure of the multichip module according to the third aspect is characterized in that the conductor of the wiring layer is copper.

[0017]

In the structure of the multi-chip module according to the first aspect, the Cu / polyimide multilayer wiring section 2 is formed on a single wafer-level SRAM Si substrate 1 on which a memory having a redundant capacity is integrated. And the address decoder / controller 3 and the MPU 4
A hybrid structure is provided above the polyimide multilayer wiring section 2. Therefore, a highly reliable and inexpensive multi-chip module can be provided.

In the structure of the multi-chip module according to the present invention, the wiring layer in which the insulator and the conductor are combined in a multi-layer structure is a memory having a redundant capacity and a connection between the memory and the processor unit of the integrated circuit layer. An integrated circuit layer on which a processor unit is formed is formed on a single wafer-level substrate layer in which a switching unit for switching is integrated, and a hybrid unit is formed on a wiring layer. Therefore, a highly reliable and inexpensive multi-chip module can be provided.

In the structure of the multi-chip module according to the third aspect, since the conductor of the wiring layer is made of copper, a more inexpensive multi-chip module can be provided.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the accompanying drawings. Prior to the preparation, a technique as a background of the present invention will be described first.

In recent years, in information processing apparatuses such as engineering workstations and personal computers, for example, in order to respond to the miniaturization and personalization of the apparatuses from users, parallel processing and improvement in processing capacity by increasing the speed of clocks have been increasing. Have been.

Accordingly, a multi-chip module (hereinafter, referred to as a semiconductor chip) to which a semiconductor integration technology capable of handling a high-speed signal and a high-density mounting technology of a semiconductor LSI are applied.
MCM: Multi-Chip Module).

In the MCM, in order to achieve high-density mounting of a semiconductor integrated circuit, mounting techniques such as wire bonding and flip chip method are usually mounted on a substrate on which a transmission line in which characteristic impedance is considered is formed. Thus, the LSI chip is mounted in a bare chip state.

By the way, in the MCM, as a substrate material,
For example, inexpensive glass epoxy or ceramic multilayer boards, S
Some use an i (silicon) substrate or the like.

Among these, MCM using Si substrate
Is SOS (Si On Si) or COW (Ch
It is called “ip on wafer”, and since the Si semiconductor process technology can be applied as it is, that is, it is possible to form and control a fine pattern, it is sufficiently fast.
Since high-density signal transmission can be performed, it is expected that the MPU will be equipped with an MPU technology that is expected to increase in speed in the future.

Furthermore, since the same Si is used for the substrate material and the LSI substrate material,
Since there is no difference in the coefficient of thermal expansion from the substrate material, there is an advantage that high reliability can be obtained when bare chip mounting is performed by, for example, a flip chip method.

FIG. 1 shows an MPU created by SOS.
FIG. 3 is a perspective view illustrating a configuration example of a module. In this MPU module, a wiring section 60 in which, for example, Cu (copper) as a wiring material and polyimide, for example, as an insulating film are formed in multiple layers is formed on a Si substrate 11. Is an MPU chip 4 or SRAM (Static RA)
M) While the chip 51 is mounted, the decoupling capacitor 5 and the module pad (connection pad)
6 are provided.

Further, the structure will be described in detail with reference to the cross-sectional view shown in FIG. 2. An SiO ₂ insulating film 15 is formed on a Si substrate 11 via a GND (ground) wiring (GND electrode) 61. Then, a polyimide insulating film 18 is formed thereon. Polyimide insulation film 18
Has a via hole 17 at a desired position, and further has a Cu signal wiring 62 and a Cu power supply wiring 63.
It is formed as needed.

The GND wiring 61, the SiO2 insulating film 15,
Wiring portion 60 including via hole 17, polyimide insulating film 18, Cu signal wiring 62, and Cu power supply wiring 63
An opening is provided at a position corresponding to the chip pad 20 of the semiconductor chip (the MPU chip 4 and the SRAM chip 51 in FIG. 1) mounted thereon, and a BLM ( Ball Limit
ting Metalization) electrode 21 is provided.

Then, the MPU chip 4 and the SRAM chip 51 as semiconductor chips are mounted on the Si substrate 11 via the solder bumps 19 and the wiring portions 60 by a flip chip method.

The above-described SOS MPU module is mounted on a motherboard, for example, as shown in FIG.

That is, the MPU module is connected to the module pad 6 via the conductive interposer 78 and the LG.
It is electrically connected to an A (Land Grid Array) package 81, and is sandwiched between the heat sink 72 and the LGA package 81 using a mounting screw 73 and a spacer 77 as shown in FIG. It is fixed to the LGA package 81.

At this time, in order to promote heat dissipation from the MPU chip 4 and the SRAM chip 51 as the semiconductor chips, between the Si substrate 11 and the heat sink 72 of the MPU module and the semiconductor chip (the MPU chip 4,
Between the RAM chip 51) and the LGA package 81,
An interposer 71 having good thermal conductivity is inserted.

Further, the LGA package 81 is an LGA package.
Arranged on a motherboard 71 provided with a conductive interposer 82 for electrically connecting the lands 79 to each other, a suitable pressure is applied by screwing a mounting bracket 74 with a mounting screw 75 and a spacer 76, and 71.

With the above configuration, the MP
The U (MPU chip) 4 can exchange signals with the SRAM (SRAM chip) 51 at a high speed via the wiring section 60 in which the transmission impedance is considered at high density. Furthermore, it is possible to provide a module that is very compact and has excellent heat dispersibility.

With the above as background art, according to the present invention, a module with higher reliability can be provided at low cost.

FIG. 4 is a perspective view showing the structure of an embodiment of a multichip module to which the present invention is applied.
Is a sectional view of the same. In FIG. 4 or FIG.
Or, portions corresponding to those in FIG. 2 are denoted by the same reference numerals. This multi-chip module has a memory capacity required by the MPU 4 and an S layer as a substrate layer on which a memory having a redundant memory capacity is formed.
A Cu / polyimide multilayer wiring portion 2 as a wiring layer is formed on a RAM Si substrate 1, and an MP
An address decoder / controller 3 for controlling connection between the U chip 4 and the MPU chip 4 and each memory block formed on the SRAM Si substrate 1 is mounted, and a decoupling capacitor 5 and a module pad (connection pad) 6 Is provided.

Further, referring to the cross-sectional view of FIG. 5, the structure will be described in detail. On the Si substrate 11, a memory cell structure, a sense amplifier section, an address A CMOS active layer 12 including a decoding unit (none of which is shown) is formed, and a conductor such as Poly Si or Al and a wiring unit 13 including an insulating layer such as SiO ₂ are formed thereon. .

That is, the SRAM Si substrate 1 including the Si substrate 11, the CMOS active layer 12, and the wiring portion 13 has a row address and a column address (Column Address), similarly to the CMOS one-chip memory.
It consists of a memory block that can be specified by.

An insulating film 14 made of, for example, polyimide is formed on the upper portion of the wiring portion 13 to improve its flatness. On the upper portion, an insulating film 15, a Cu wiring 16, a via hole 17, and an insulating film 18 are formed. And a Cu / polyimide multilayer wiring portion 2 as a wiring layer in consideration of characteristic impedance.

That is, on the polyimide insulating film 14,
In order to avoid a defect such as a pinhole, an SiO ₂ insulating film 15 is formed, and a polyimide insulating film 18 having a via hole 17 at a desired position, and a Cu wiring (Cu signal wiring or Cu power supply) are formed thereon. Are formed in multiple layers.

An MPU (MPU chip) 4 as an integrated circuit layer, an address decoder / controller 3 and the like are mounted in a flip-chip manner on the upper portion of the Cu / polyimide multilayer wiring section 2 by using solder bumps 19 via a BLM 21. ing.

The terminals of each memory block on the SRAM Si substrate 1 are connected and controlled to the terminals of the MPU 4 by the address decoder / controller 3 via the Cu / polyimide multilayer wiring section 2.

FIG. 6 is a block diagram for explaining the electrical configuration of the embodiment of FIG. 4 (FIG. 5). SRA
The MSi substrate 1 has a number N of memory blocks B _{1 to} B _N which are redundant, for example, about 1.2 times the number of memory blocks corresponding to the memory capacity required by the MPU 4.

That is, for example, if the memory capacity required by the MPU 4 is 20 Mbits and the memory capacity of one memory block is 1 Mbits, the number of memory blocks required by the MPU 4 is 20, and in this case, S
The RAM Si substrate 1 has 24 (= 20 × 1.2) memory blocks, and four memory blocks are redundant memory blocks.

Each memory block B _n (n = 1, 2,...)
·, N), the switch SWd _n, the data bus through SWa _n, are the address bus and the respective connection, a data bus, an address bus, a data buffer 32, respectively connected to MPU4 through an address buffer 33 I have.

The upper L bits of the address bus from the MPU 4 are connected to the address decoder / controller 3, and the address decoder / controller 3
Decodes the upper L-bit address from MPU4,
Based on the decoding result, the switch SWd _n of the memory blocks B _n, SWa _n, and SWb _n of ON / O
Controls FF.

[0048] In each memory block B _n, the signal from the address decoder / controller 3, the switch SWd _n, SWa _n, and all is ON SWb _n
/ OFF, for example, when turned on, MP
Reading and writing of data from and to the address from U4 are performed.

The bad block storage memory 31 is, for example, a non-volatile memory, and is _one of the memory blocks B _{1 to} B _N.
The address corresponding to the bad block is stored.

In the multichip module configured as described above, first, an address is output from the MPU 4 and the upper L bits are decoded by the address decoder / controller 3 in the same manner as in a normal memory test. , based on the decoding result, the switch SWd _n memory blocks B _n, SW
a _n and SWb _n are turned on.

That is, the memory block B _n to be tested is selected.

Then, data is written to and read from the memory block _Bn corresponding to the address output from the MPU 4, and the write data and the read data are read by a comparator (not shown) incorporated in the MPU 4.
The output data is compared, and the quality of the memory block _Bn is determined. In the MPU 4, the memory block B _n
Is determined to be operating normally, the memory test of the next memory block B _{n + 1} is performed as described above.

On the other hand, when the MPU 4 determines that the memory block _Bn is not operating normally and is a defective block, as described in, for example, Japanese Patent Laid-Open No. 4-152565, B
_A setting is made so that a redundant block is used instead of _n .

That is, the address of the defective block is written into the defective block storage memory 31 by the MPU 4. Thereby, in the address decoder / controller 3, the defective block storage memory 31 is appropriately referred to,
When the memory block B _n corresponding to the address stored in the bad block memory 31, that is, the bad block is selected by the MPU 4, the bad block is not used,
The connection between the MPU 4 and the memory block is controlled so that one of the redundant memory blocks that has not been used is validated and used.

When the minimum memory capacity required by the MPU 4 has been secured, the memory test ends.

The memory test can be performed at any time, such as immediately after completion of the module, after shipment as a product, or every time the power is turned on.

Here, each memory block _Bn can be composed of cells C _{1 to} C _M , a data buffer 41, an address buffer 42, and an address decoder / controller 43, as shown in FIG. .

The cells C _{1 to} C _M are arranged in a hierarchical structure, and some of them are provided as redundant cells.

When a defective cell is found from among the cells C _{1 to} C _M , the address of the defective cell is stored in the defective block storage memory 31. Thereby, when the address corresponding to the defective cell is output by the MPU 4, the defective block storage memory 31 is referred to by the address decoder / controller 43 and the defective cell is replaced in the same manner as in the above-described defective block. One of the redundant cells
One is made to be selected.

By configuring each memory block _Bn as described above, its effective utilization efficiency can be improved.

Incidentally, in order to further improve the effective use efficiency of each memory block _Bn , it is sufficient to further advance the hierarchical structure of the cells. However, if it proceeds too much, the load on the address decoder / controller 43 increases, and Since the circuit becomes large-scale and the effective utilization efficiency decreases, it is necessary to balance and advance the hierarchical structure.

As described above, the Cu / polyimide multilayer wiring section 2 is formed on the SRAM Si substrate 1 on which the memory having the redundant memory capacity is formed with respect to the memory capacity required by the MPU 4, In addition, since the MPU 4 and the address decoder / controller 3 are mounted, the memory capacity required by the MPU 4 can be secured by using redundant memory blocks while avoiding defective memory blocks. Self-healing ability,
It is possible to provide a very reliable and compact MCM at low cost.

Further, an MPU is provided above the memory block.
4, the average wiring length is shortened.
It is possible to increase the density of the MCM and increase the speed of its operation.

In FIG. 6, the defective block storage memory 31 or the address decoder / controller 3
Represents the Cu / polyimide multilayer wiring section 2 as in the case of the MPU 4.
Is mounted as an integrated circuit layer on the top of the SRAM Si substrate 1, but can be integrated on a part of the SRAM Si substrate 1.

In this embodiment, the bad block storage memory 31 is provided independently. However, the bad block storage memory 31 can be built in the MPU 4 or the address decoder / controller 3, for example. .

Further, in this embodiment, polyimide (polyimide insulating film 18) is used as an insulator of the Cu / polyimide multilayer wiring portion 2, but for example, Si is used.
O _2, etc. can be made to use other insulator.

In forming the film, for example, spin coating, bias sputtering, Plasma CV
Any film forming method such as the method D can be applied.

Further, in this embodiment, Cu is used as the conductor of the Cu / polyimide multilayer wiring section 2.
For example, various metals such as Al (aluminum) and Au (gold) can be used.

Further, in this embodiment, by storing the address corresponding to the defective block in the defective block storage memory 31, a redundant block that operates normally can be selected and used instead of the defective block. However, the same can be done by other methods.

That is, for example, a fuse line is provided on an address decode line (a line connecting the address decoder / controller 3 and each memory block) connected to each memory block, and the block is determined as a defective block. The fuse line connected to the memory block can be burned out by overcurrent.

Further, the address decode line connected to the defective block can be trimmed by a laser beam or the like.

However, any of the methods can be executed on a test bench, and if it is performed after assembling a module, it takes too many steps and is not practical.

Further, the maximum value of the memory capacity of each memory block depends on the average defect density of the process of manufacturing the memory (SRAM Si substrate 1), the minimum memory capacity required by the MPU 4, and the subdivision of the memory block. It is necessary to balance the burden on the address decoder / controller 3 before deciding.

In this embodiment, when a defective cell is found from the cells C _{1 to} C _M constituting the memory block, the address of the defective cell is stored in the defective block storage memory 31. However, a memory for storing a defective cell can be provided in each memory block.

Further, in the present embodiment, the memory capacity including the redundant memory capacity is 1.2 times the memory capacity required by the MPU 4, but the present invention is not limited to this.

However, in consideration of the balance between circuit scale and reliability, the redundant memory capacity is a value obtained by dividing the memory capacity required by the MPU 4 by the yield of memory blocks expected from the defect density of the memory creation process. of,
About 1.1 to 1.2 times is appropriate.

[0077]

According to the structure of the multi-chip module according to the first aspect, the wiring layer is formed on a single wafer-level substrate layer in which a memory having a redundant capacity is integrated. The switching unit and the processor unit are configured in a hybrid manner above the wiring layer.
Therefore, a highly reliable and inexpensive multi-chip module can be provided.

According to the structure of the multi-chip module of the present invention, a wiring layer is formed on a single wafer-level substrate layer on which a memory having a redundant capacity and a switching unit are integrated. The integrated circuit layer on which the processor unit is formed is configured in a hybrid manner above the wiring layer. Therefore, a highly reliable and inexpensive multi-chip module can be provided.

According to the structure of the multi-chip module according to the third aspect, since the conductor of the wiring layer is made of copper, a more inexpensive multi-chip module can be provided.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration example of a multichip module as a background art of the present invention.

FIG. 2 is a cross-sectional view of the multi-chip module of FIG.

FIG. 3 is a cross-sectional view illustrating a state in which the multichip module of FIG. 1 is mounted on a motherboard 71.

FIG. 4 is a perspective view showing a configuration of one embodiment of a multi-chip module to which the structure of the multi-chip module of the present invention is applied.

FIG. 5 is a sectional view of the embodiment of FIG.

FIG. 6 is a block diagram showing an electrical configuration of the embodiment of FIG.

FIG. 7 is a block diagram showing a configuration of a memory block in the SRAM Si substrate 1 of the embodiment of FIG.

FIG. 8 is a plan view showing a configuration of an example of a conventional LSI module.

[Explanation of symbols]

1 SRAM Si substrate 2 Cu / polyimide multilayer wiring section 3 address decoder / controller 4 MPU 5 decoupling capacitor 6 modules pad 11 Si substrate 12 CMOS active layer 13 wiring portion 14 polyimide insulating layer 15 SiO ₂ insulating film 16 Cu wiring 17 via hole 18 Polyimide insulating film 19 Solder bump 20 Chip pad 21 BLM (Ball Limiting Metalization) 31 Bad block storage memory 32 Data buffer 33 Address buffer 41 Data buffer 42 Address buffer 43 Address decoder / controller

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takashi Akasaka 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-5-190758 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 23/522 H01L 25/04 H01L 25/18 H01L 21/60

Claims (3)

(57) [Claims] 1. A wafer-level substrate layer in which a memory having a redundant capacity is integrated, a wiring layer in which insulators and conductors are combined in multiple layers, a processor unit, and a memory in the substrate layer. And an integrated circuit layer on which a switching unit for switching connection with the processor unit is formed. The wiring layer is formed on the substrate layer, and the integrated circuit layer is hybrid on the wiring layer. A structure of a multi-chip module characterized by being constituted. 2. An integrated circuit layer on which a processor unit is formed, a memory having a redundant capacity, and a switching unit for switching a connection between the processor unit of the integrated circuit layer and the memory are integrated. A substrate layer at a wafer level; and a wiring layer in which an insulator and a conductor are combined in a multilayer. The wiring layer is formed on the substrate layer, and the integrated circuit layer is hybridized on the wiring layer. A structure of a multi-chip module, characterized in that it is configured as follows. 3. The structure of the multichip module according to claim 1, wherein the conductor of the wiring layer is copper.