JP3318229B2 - Transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting apparatus used for digital mobile communication and the like, and more particularly to a transmitting apparatus capable of reducing a circuit scale and power consumption.

[0002]

2. Description of the Related Art A mobile station performing TDMA mobile communication receives only its own time slot from among TDM signals transmitted from a base station, and periodically transmits a burst signal as a transmission signal to the base station. Send. The mobile station data transmission device has a burst transmission control function to obtain a desired burst transmission waveform. Also, CDMA
In some systems, burst transmission control is performed depending on the data rate of the mobile station.

As described above, in digital mobile communication, burst transmission control is performed in various systems, but a conventional transmission device with a burst transmission control function has an input terminal 81 to which transmission data is input, as shown in FIG. An input terminal 82 to which a burst transmission ON / OFF signal is input, a mapping circuit 83 which outputs mapping data according to the transmission data when the burst transmission is ON, and outputs 0 when the burst transmission is OFF, and a band of the mapped signal. FIR filter circuit 84 that limits the signal to form a desired waveform, and D / D that converts the output signal of FIR filter circuit 84 to an analog signal.
The A / D converter includes A converters 92 and 95, post filters 93 and 96 for smoothing output signals of the D / A converters 92 and 95, and output terminals 94 and 97 for outputting transmission signals.

[0004] As an example, a case where QPSK modulation is performed will be described. Further, the FIR filter circuit 84
Impulse response length is ± N symbol, 4 for input signal
It is assumed that a filter operation of double oversampling (the number of taps: 8N) is performed.

[0005] The mapping circuit 83 performs QPSK mapping on the transmission data 81, and when a burst transmission ON signal is input, as the in-phase (I) component and the quadrature (Q) component, the QPSK mapping data "1" or When a burst transmission off signal is input, "-1" is output as 2-bit data as an I component and a Q component, respectively.

The FIR filter circuit 84 includes shift register circuits 85 and 88 for storing transmission data after mapping, and FIR filter circuits 84 and 88.
An impulse response coefficient generation circuit 91 for generating an IR filter coefficient h (k), transmission data after mapping stored in the shift register circuits 85 and 88, and an FIR filter coefficient h
(K), and adders 87 and 90 for cumulatively adding the multiplication results.

Next, the operation of this device will be described.

Digital data to be transmitted is applied to an input terminal 81 of this device at a symbol time point nT (n: positive integer, T: symbol period).
A burst transmission on / off signal is applied.

The digital data applied to the input terminal 81 is converted by the mapping circuit 83 into QPSK mapping data "1" or "-1" corresponding to the transmission data when the burst transmission ON signal is input to the input terminal 82. When the burst transmission off signal is input to the input terminal 82, it is converted to "0" and converted to 2-bit data I (nT) and Q (nT) by the FIR filter circuit 84.
Supplied to

Here, the principle of the filter operation in the FIR filter circuit 84 will be described. In the FIR filter circuit 84, a filter operation of 4 times oversampling is performed on the input data, so that the filter input I (n
T) and Q (nT) are respectively I ((4n + m) T _S ),
Q ((4n + m) T _S ) (m: 0, 1, 2, 3, T _S = T
/ 4: sample period). However, when m ≠ 0, I ((4n + m) T _S ) = Q ((4n + m) T _S ) =
0.

At this time, the FIR filter coefficient is set to h (pT
_S ) (p: positive integer), the sample time (4n +
m) I-side FIR filter output YI at T _S
((4n + m) T _S ), Q side FIR filter output YQ
((4n + m) T _S ) can be expressed as (Equation 1). YI ((4n + m) T _s ) = Σh (pT _s ) ・ I ((4n + mp) T _s ) YQ ((4n + m) T _s ) = Σh (pT _s ) ・ Q ((4n + mp ) T _s ) (Equation 1) (Σ is added from p = 0 to 8N-1)

Here, only when | m−p | is a multiple of 4, I ((4n + m−p) T _S ) ≠ 0, Q ((4n + m−
p) Considering that T _s ) ≠ 0, p−m = 4 k
Substituting (k: integer) into (Equation 1) gives (Equation 2). YI ((4n + m) T _s ) = Σh ((4k + m) T _s ) ・ I (4 (nk) T _s ) = Σh ((4k + m) T _s ) ・ I ((nk) T) YQ ((4n + m) T _s ) = (h ((4k + m) T _s ) · Q ((nk) T) (Equation 2) (All Σs are added from k = 0 to 2N-1)

The output of the FIR filter shown in (Expression 2) is output to the shift register circuit 85 of the FIR filter circuit 84 by the shift register circuit 85.
((N−k) T) and Q
((Nk) T) are respectively stored, and the impulse response coefficient generation circuit 91 stores the filter coefficient h ((4k + m)
T _s ), and h ((4k + m) T _s ) · I
((N−k) T) multiplication, and h ((4k
+ M) T _s ) · Q ((n−k) T), and the result of the multiplication can be obtained by accumulative addition in adders 87 and 90. At this time, the FIR filter circuit
In 84, 2 × 2N multipliers and 2 × (2N−1)
Adders are required.

The output of the FIR filter circuit 84 is converted into an analog sample value signal by a D / A converter 92 and a D / A converter 95, and then smoothed by a post filter 93 and a post filter 96. Output terminal as the output of the transmitting device
94 and an output terminal 97.

As described above, in the conventional transmission device with a burst transmission control function, the FIR filter circuit uses the shift register, the multiplier, and the adder to perform the filter operation shown in (Equation 2) to obtain the desired signal. Is obtained.

[0016]

However, in this conventional transmission device with a burst transmission control function, the product-sum operation for each sample of the filter input data and the impulse response coefficient is actually performed using a multiplier and an adder. Therefore, a large number of multipliers and adders are required, resulting in a problem that current consumption and a circuit scale increase.

The present invention is to solve such a conventional problem. By forming the FIR filter circuit without using a multiplier, the burst size can be reduced and the power consumption can be reduced. It is an object of the present invention to provide a transmission device with a transmission control function.

[0018]

Therefore, in the transmitting apparatus with burst transmission control function of the present invention, the mapping circuit comprises:
The in-phase component and quadrature component data are output in two's complement format, and the FIR filter circuit uses an address generation circuit, a memory, a bit shift circuit, an adder, and a selector circuit to input data input from a mapping circuit. The convolution operation with the impulse response coefficient is performed.

Since this transmission device does not have a multiplier in the FIR filter circuit, the circuit scale can be reduced and the power consumption can be reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention provides a mapping circuit for outputting quadrature in-phase impulse data corresponding to transmission data when burst transmission is on, and "0" when burst transmission is off. , A transmission device having a burst transmission control function including a FIR filter circuit for limiting a band of a burst waveform, wherein a mapping circuit outputs each data of an in-phase component and a quadrature component in a two's complement format, and the FIR filter circuit comprises: An address generating circuit, a memory, a bit shift circuit, an adder, and a selector circuit are used to perform a convolution operation on input data input from a mapping circuit and an impulse response coefficient. Small,
Power consumption can be reduced.

According to a second aspect of the present invention, in the FIR filter circuit, there are provided an address generation circuit for generating the same number of memory addresses as the number of bits of input data, and a plurality of memories for generating the address generation circuit. 1 from address
A selector circuit for sequentially selecting each system, a memory storing a convolution operation result of input data and an impulse response coefficient, and a bit shift operation of a convolution operation result read from the memory by a memory address selected by the selector circuit , And an adder for adding the output of the bit shift circuit,
An FIR filter circuit can be configured without using a multiplier.

According to a third aspect of the present invention, an address generation circuit, a selector circuit, a memory, a bit shift circuit, and an adder of an FIR filter circuit are associated with input data of an in-phase component and a quadrature component input from a mapping circuit. Since two systems are provided, it can be applied to a quadrature modulator.

According to a fourth aspect of the present invention, in the FIR filter circuit, the number of systems (A ×
B) an address generating circuit for generating a memory address;
A memory address of the number of systems A is inputted from the address generating circuit, and B selector circuits for sequentially selecting one system at a time from these memory addresses, and a convolution operation result of the input data and the impulse response coefficient are divided and stored. B
Memories, a first adder for adding data read from each memory by a memory address selected by each selector circuit to obtain a convolution operation result, and a convolution operation result output from the first adder And a second adder for adding the output of the bit shift circuit. The FIR filter circuit can be configured by a memory having a small number of words.

According to a fifth aspect of the present invention, an address generation circuit of an FIR filter circuit, B selector circuits, B memories, and a second memory correspond to input data of an in-phase component and a quadrature component input from a mapping circuit. This is provided with two systems of one adder, bit shift circuit and second adder, and can be applied to a quadrature modulator.

According to the present invention, in accordance with the data of the in-phase component and the quadrature component input from the mapping circuit, the FIR filter circuit generates the same number of memory addresses as the number of bits of the input data. Two address generation circuits and one system is sequentially selected from a plurality of memory addresses generated by each of the address generation circuits.
Pieces of first selector circuits, a second selector circuit that alternately selects a memory address output from each of the first selector circuits, and one piece of memory that stores a result of convolution of input data and an impulse response coefficient. A memory, a bit shift circuit for performing a bit shift operation of a convolution operation result read from the memory by the memory address selected by the second selector circuit, and an output of the bit shift circuit added to correspond to an in-phase component and a quadrature component An adder for obtaining output data by time-division processing is provided, and the number of memories used can be reduced.

According to a seventh aspect of the present invention, the FIR filter circuit has a bit number A of input data corresponding to in-phase component and quadrature component data input from the mapping circuit.
Address generation circuits for generating a memory address of B times the number of systems (A × B), and a memory address of the number of systems A from one of the address generation circuits, and one system from each of these memory addresses 2 × B first to sequentially select
A selector circuit, B second selector circuits for alternately selecting memory addresses output from two first selector circuits connected to separate address generation circuits, and a convolution operation result of input data and an impulse response coefficient are divided A first adder that obtains a convolution operation result by adding data read from each of the memories according to a memory address selected by each of the second selector circuits; A bit shift circuit for performing a bit shift operation on the convolution operation result output from the adder, and a second addition for adding the outputs of the bit shift circuit to obtain output data corresponding to the in-phase component and the quadrature component by time division processing And the number of memories used when configuring an FIR filter circuit using a memory having a small number of words can be reduced.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(First Embodiment) In a first embodiment, as an example, a transmission device with a burst transmission control function for performing QPSK modulation will be described.

As shown in FIG. 1, this apparatus has an input terminal 1 for inputting transmission data, an input terminal 2 for inputting a burst transmission on / off signal,
A mapping circuit 3 that performs QPSK mapping on transmission data and outputs “1” or “−1” according to the transmission data, and outputs “0” as an I component and a Q component when burst transmission is off; Address transmission circuit, memory, bit shift circuit,
FI for performing band limitation using adder and selector circuit
An R filter circuit 4, D / A converters 5 and 8 for converting an output signal of the FIR filter circuit 4 into an analog signal,
Post-filters 6 and 9 for smoothing output signals of A-converters 5 and 8 are provided, and output terminals 7 and 10 for outputting transmission signals.

The mapping circuit 3 outputs "1", "-"
"1" or "0" is output as 2 bits and 2's complement data, respectively.

In this case, the FIR filter circuit 4 performs a filter operation with an impulse response length of ± N symbols and a 4-fold oversampling (the number of taps: 8N) on the input signal. As shown in FIG. 2, the FIR filter circuit 4 includes an address generation circuit 11 for generating two-system memory addresses based on two's complement format and 2-bit I component data input from the mapping circuit,
An address generation circuit 16 for generating two memory addresses based on two's complement format and 2-bit Q component data input from a mapping circuit, and a two-system memory address of I component output from the address generation circuit 11 A selector circuit 12 for sequentially selecting addresses one by one; a selector circuit 17 for sequentially selecting addresses one by one from two memory addresses of the Q component output from the address generation circuit 16; A memory 13 that previously stores a result of a convolution operation between data and an impulse response coefficient, a memory 13 that previously stores a result of a convolution operation between transmission data after mapping of the Q component and an impulse response coefficient, and a memory 13 I read
A bit shift circuit 14 for performing a bit shift operation on the convolution operation result of the component, a bit shift circuit 19 for performing a bit shift operation on the convolution operation result of the Q component read from the memory 18, and a bit shift circuit 14 And an adder 15 for adding the outputs of the bit shift circuit 19 to obtain the data of the Q component.

The operation of the transmission device with a burst transmission control function will be described.

Digital data to be transmitted is applied to an input terminal 1 of this device at a symbol time point nT (n: positive integer, T: symbol period).
A burst transmission on / off signal is applied.

The digital data applied to the input terminal 1 is converted by the mapping circuit 3 into QPSK mapping data "1" or "-1" corresponding to the transmission data when the burst transmission ON signal is input to the input terminal 2. When the burst transmission off signal is input to the input terminal 2, it is converted to "0", and the 2-bit data I (nT), Q (n
T) is supplied to the FIR filter circuit 4.

Here, the principle of the filter operation in the FIR filter circuit 4 will be described. In this FIR filter circuit 4, a filter operation of 4 times oversampling is performed on input data.
(NT) and Q (nT) are respectively I ((4n + m)
T _S ), Q ((4n + m) T _S ) (m: 0, 1, 2, 3,
T _S = T / 4: sample period). Where m
When ≠ 0, I ((4n + m) T _s ) = Q ((4n +
m) T _s ) = 0.

At this time, the FIR filter coefficient is set to h (pT
_S ) (p: positive integer), the sample time (4n +
m) I-side FIR filter output YI at T _S ((4
n + m) T _S ), and the Q-side FIR filter output YQ
((4n + m) T _S ) can be expressed as (Equation 3). YI ((4n + m) T _s ) = Σh (pT _s ) ・ I ((4n + mp) T _s ) YQ ((4n + m) T _s ) = Σh (pT _s ) ・ Q ((4n + mp ) T _s ) (Equation 3) (Σ is added from p = 0 to 8N-1)

Here, only when | m−p | is a multiple of 4, I ((4n + m−p) T _s ) ≠ 0, Q ((4n + m−
p) Considering that T _s ) ≠ 0, p−m = 4 k
(K: integer). The value v _i, expressed in 2's complement ^{_{format, v i = -2 A-1}} · v i 0 + Σ2 A-1-k · v i k (Σ is summed from k = 1 to A-1 ) (where, a is the number of bits indicating the v _i, v _i ⁰ is the value of the MSB,
v Since _i ^k can display the value of v k th bit of the _i), the filter input, the two's complement form, considering that it is represented by two bits, the equation (3) is (Equation 4) Can be converted as follows.

YI ((4n + m) T _s ) = − 2 · Σh ((4k + m) T _s ) · I ⁰ ((nk) T) + Σh ((4k + m) T _s ) · I ¹ ( (nk) T) YQ ((4n + m) T _s ) =-2 ・ Σh ((4k + m) T _s ) ・ Q ⁰ ((nk) T) + Σh ((4k + m) T _s ) ・ Q ¹ ((nk) T) (Σ is added from k = 0 to 2N-1) (Equation 4) (However, I ⁰ and Q ⁰ are MSB of 2-bit data, I ¹ and Q ¹ are 2 bits LSB of data)

Next, (Equation 4) is converted into (Equation 5). YI ((4n + m) T _s ) =-2Ψ (I ⁰ (nT), I ⁰ ((n-1) T), I ⁰ ((n-2) T), ‥, I ⁰ (( n-2N + 1) T), m) + Ψ (I ¹ (nT), I ¹ ((n-1) T), I ¹ ((n-2) T), ‥, I ¹ ((n-2N +1) T), m) YQ ((4n + m) T _s ) =-2Ψ (Q ⁰ (nT), Q ⁰ ((n-1) T), Q ⁰ ((n-2) T ), ‥, Q ⁰ ((n-2N + 1) T), m) + Ψ (Q ¹ (nT), Q ¹ ((n-1) T), Q ¹ ((n-2) T), ‥ , Q ¹ ((n-2N + 1) T), m) where Ψ (I ^r (nT), I ^r ((n-1) T), I ^r ((n-2) T), ‥, I ^r ((n-2N + 1) T), m) = Σh ((4k + m) T _s ) ・ I ^r ((nk) T) Ψ (Q ^r (nT), Q ^r ((n-1 ) T), Q ^r ((n-2) T), ‥, Q ^r ((n-2N + 1) T), m) = Σh ((4k + m) T _s ) ・ Q ^r ((nk) T) (r = 0,1) (Σ is added from k = 0 to 2N-1) (Equation 5)

Therefore, the table of the memories 13 and 14 contains (I
^r (nT), I ^r ((n-1) T), I ^r ((n-2) T), ‥, I ^r ((n-2N + 1) T), m),
Or (Q ^r (nT), Q ^r ((n-1) T), Q ^r ((n-2) T), ‥, Q ^r ((n-2N + 1)
T) and m) are used as addresses, and （of (Equation 5) is written in advance, and at the time of calculation, a filter operation can be realized by performing a bit shift operation and an addition on Ψ.

Specifically, the operation is performed as follows. FI
R filter circuit 4 of the address generating circuit 11, the address of the I component per sample ^{(I r (nT), I} r ((n-1) T), I r ((n-2) T),
セ レ ク タ, I ^r ((n−2N + 1) T), m), and the selector circuit 12 alternately selects the address in the order of r = 0 and r = 1 and supplies the address to the memory 13. From the memory 13, Ψ specified by this address (Equation 5) is read out in the order of r = 0 and r = 1 and supplied to the bit shift circuit.

In the bit shift circuit 14, Ψ of r = 0 is 1
The amplitude is doubled by bit shifting, and Ψ of r = 1 is supplied to the adder 15 without bit shifting. The adder 15 multiplies Ψ of r = 0 by −1, adds it to ＝ of r = 1, and outputs YI ((4n + m)) which is a filter output.
T _s ).

Similarly, the address generation circuit 16
Q component address (Q ^r (nT), Q ^r ((n-1) T), Q
^r ((n−2) T), ‥, Q ^r ((n−2N + 1) T), m), and the selector circuit 17 alternately addresses the addresses in the order of r = 0 and r = 1. Select and supply to the memory 18. From the memory 18, Ψ designated by this address (Equation 5) is read in the order of r = 0, r = 1, and supplied to the bit shift circuit 19.

In the bit shift circuit 19, Ψ of r = 0 is 1
The amplitude is doubled by bit shifting, and Ψ of r = 1 is supplied to the adder 20 without bit shifting. The adder 20 multiplies Ψ of r = 0 by −1, and adds it to ＝ of r = 1 to obtain a filter output YQ ((4n + m)
T _s ).

In this FIR filter circuit 4, 2
A memory of × 2 ^{2N + 2} words and two adders are required.

In the bit shift circuits 14 and 19, r =
Instead of bit shifting about Ψ of 0, Ψ of r = 0
Is shifted by one bit to shift the amplitude of 倍 of r = 1 by １ ／ without increasing the bit, and the adders 15 and 20 multiply Ψ of r = 0 by −1, and then Ψ of r = 1. May be added to obtain a filter output.

The output of the FIR filter circuit 4 is converted into an analog sample value signal by D / A converters 5 and 8, and
The signal is smoothed by the post filters 6 and 9 and output from the output terminals 7 and 10 as the output of the transmission device.

As described above, in the transmitting apparatus of this embodiment, the in-phase / quadrature impulse data is input to the FIR filter circuit without using the multiplier when the burst transmission is on, and “0” is input when the burst transmission is off. Then, burst transmission control is performed using the transient response characteristic of the FIR filter.

In this FIR filter circuit, the result of convolution of these values and the impulse response coefficient is read out from the memory in accordance with the combination of the MSB values of the continuously input 2-bit input data. Corresponding to the combination of the LSB values of the data, the result of convolution of these values and the impulse response coefficient is read out from the memory, and these operation results are bit-shifted and added to obtain the input data and the impulse response coefficient. And the result of the convolution operation.

Since the convolution operation can be performed without using a multiplier, the circuit size can be reduced and the power consumption is small.

In this embodiment, the input data is 2
Although the convolution operation in the case of bits has been described, when the number of bits of input data is generally A, a combination of values of the first bit of the input data, a combination of values of the second bit,. The convolution results of the values and the impulse response coefficients are read out from the memory using the combinations of values as addresses, and necessary bit shifts are performed on the results of the convolution. The result of the convolution operation with the impulse response coefficient can be obtained.

(Second Embodiment) The transmitting apparatus with a burst transmission control function of the second embodiment differs from the first embodiment only in the configuration of the FIR filter circuit. Here, as in the first embodiment, a case in which the FIR filter circuit limits the band of the QPSK modulated wave signal will be described. In this FIR filter circuit, it is assumed that an impulse response length is ± N symbols, and a filter operation of 4 times oversampling (the number of taps: 8N) is performed on the filter input.

As shown in FIG. 3, the FIR filter circuit has a two's complement format output from the mapping circuit.
Address generating circuit for generating two addresses for two memories based on I-component data of bits
31 and 2's complement format output from the mapping circuit, 2
Address generation circuit for generating two addresses for two memories based on bit Q component data
39, a selector circuit a32 and a selector circuit b34 for sequentially selecting an address one by one from the two addresses inputted from the address generating circuit 31, and an address sequentially from the two addresses inputted from the address generating circuit 39 one by one. A selector circuit a40 and a selector circuit b42 to be selected;
The operation result of the convolution operation of the transmission data and the impulse response coefficient after mapping the I component is divided into two groups, a memory 33 storing one of them, a memory 35 storing the other, and a Q component The operation result of the convolution operation of the transmission data and the impulse response coefficient after mapping is divided into two groups, and a memory 41 storing one of them and a memory 43 storing the other one
A first adder 36 for adding the output data of the memory a33 and the output data of the memory b35, and a first adder for adding the output data of the memory a41 and the output data of the memory b43.
44, a bit shift circuit 37 for performing a bit shift operation on the I component data output from the first adder 36,
A bit shift circuit 45 for performing a bit shift operation on the Q component data output from the first adder 44, a second adder 38 for adding the I component data output from the bit shift circuit 37, A second adder 46 for adding the Q component data output from the bit shift circuit 45;

As in the first embodiment, when the burst transmission is turned on, the FIR filter circuit 4 receives QPSK mapping data “1” or “−1” corresponding to the transmission data. When the burst transmission is off, “0” is supplied as 2's complement format 2-bit data. This is called I (nT), Q (nT)
And

The principle of the filter operation in the FIR filter circuit 4 will be described. This FIR filter circuit 4
Performs a filter operation of 4 times oversampling on input data, so that filter inputs I (nT),
Q (nT) is I ((4n + m) T _S ), Q
((4n + m) T _S ) (m: 0, 1, 2, 3, T _S = T /
4: sample period). However, when m ≠ 0, I ((4n + m) T _S ) = Q ((4n + m) T _S ) =
0. At this time, the FIR filter coefficient is set to h (p
T _S ) (p: positive integer), the sample time (4n +
m) I-side FIR filter output YI at T _S ((4
n + m) T _S ), Q-side FIR filter output YQ ((4
n + m) T _s ) can be expressed as (Equation 6). YI ((4n + m) T _s ) = Σh (pT _s ) ・ I ((4n + mp) T _s ) YQ ((4n + m) T _s ) = Σh (pT _s ) ・ Q ((4n + mp ) T _s ) (Equation 6) (Σ is added from p = 0 to 8N-1)

Here, only when | m−p | is a multiple of 4, I ((4n + m−p) TS) ≠ 0, Q ((4n + m−
p) TS = 4k considering that TS) ≠ 0
(K: integer), and considering that the filter input is a 2's complement format and 2 bits, (equation 6) can be converted as (equation 7). YI ((4n + m) T _s ) =-2 ・ {Σh ((4k + m) T _s ) ・ I ⁰ ((nk) T) + Σh ((4k + 4N + m) T _s ) ・ I ⁰ ( (nkN) T)} + {Σh ((4k + m) T _s ) · I ¹ ((nk) T) + Σh ((4k + 4N + m) T _s ) · I ¹ ((nkN) T)} YQ ((4n + m) T _s ) =-2 ・ {Σh ((4k + m) T _s ) ・ Q ⁰ ((nk) T) + Σh ((4k + 4N + m) T _s ) ・ Q ⁰ (( nkN) T)} + {Σh ((4k + m) T _s ) · Q ¹ ((nk) T) + Σh ((4k + 4N + m) T _s ) · Q ¹ ((nkN) T)} (Σ Are added from k = 0 to N-1) (Equation 7) (However, I ⁰ and Q ⁰ are MSBs of 2-bit data, and I ¹ and Q ¹ are LSBs of 2-bit data)

Next, (Expression 7) is converted into (Expression 8). YI ((4n + m) T _s ) =-2 ・ {Ψ _a (I ⁰ (nT), I ⁰ ((n-1) T), ‥, I ⁰ ((n-N + 1) T), m) + Ψ _b (I ⁰ ((nN) T), I ⁰ ((nN-1) T), ‥, I ⁰ ((n-2N + 1) T), m)} + {Ψ _a (I ¹ (nT), I ¹ ((n-1) T), ‥, I ¹ ((n-N + 1) T), m) + Ψ _b (I ¹ ((nN) T), I ¹ ((nN- 1) T), ‥, I ¹ ((n-2N + 1) T), m)} YQ ((4n + m) T _s ) =-2 ・ {Ψ _a (Q ⁰ (nT), Q ⁰ ( (n-1) T), ‥, Q ⁰ ((n-N + 1) T), m) + Ψ _b (Q ⁰ ((nN) T), Q ⁰ ((nN-1) T), ‥, Q ⁰ ((n-2N + 1) T), m)} + {Ψ _a (Q ¹ (nT), Q ¹ ((n-1) T), ‥, Q ¹ ((n-N + 1) _{T), m) + Ψ b} (Q 1 ((nN) T), Q 1 ((nN-1) T), ‥, Q 1 ((n-2N + 1) T), m)} where, [psi _a (I ^r (nT), I ^r ((n-1) T), ‥, I ^r ((n-N + 1) T), m) = Σh ((4k + m) T _s ) ・ I ^r ( (nk) T) Ψ _b (I ^r ((nN) T), I ^r ((nN-1) T), ‥, I ^r ((n-2N + 1) T), m) = Σh ((4k + 4N + m) T _s ) ・ I ^r ((nkN) T) Ψ (Q ^r (nT), Q ^r ((n-1) T), ‥, Q ^r ((n-N + 1) T) , m) = Σh ((4k + m) T s) · Q r ((nk) T) Ψ b (Q r ((nN) T), Q r ((nN-1) T), ‥, Q r ((n-2N + 1) T), m) = Σh ((4k + 4N + m) T _s ) · Q ^r ((nkN) T) (r = 0,1) (Σ is k = (Add from 0 to N-1) (Equation 8)

Therefore, the table of the memories 33 and 41 contains (I
^r (nT), I ^r ((n-1) T), ‥, I ^r ((n-N + 1) T), m), or (Q ^r (n
T), Q ^r ((n-1) T), ‥, Q ^r ((n-N + 1) T), m)
Leave write the Ψ _a of (number 8), also, the memory 35, 43
Table contains (I ^r ((nN) T), I ^r ((nN-1) T), ‥, I ^r ((n-
2N + 1) T), m ), or ^{(Q r ((nN) T} ), Q r ((nN-1) T), ‥, Q
^{r ((n-2N + 1} ) T), the m) as the address, is written to [psi _b of (8). Then, when calculating implements a filter operation by performing an addition and bit shift operation on the [psi _a and [psi _b.

More specifically, the operation is performed as follows. The address generation circuit 31 of the FIR filter circuit 4 outputs the I
Component address (I ^r (nT), I ^r ((n-1) T), I ^r ((n-2) T), ‥, I
^r ((n-N + 1) T), m) and address (I ^r ((nN) T), I ^r ((nN-1) T),
^{‥, I r ((n-} 2N + 1) T), m) and generates a, respectively, and outputs to the selector circuit 32 and the selector circuit 34. Selector circuit
32 and the selector circuit 34 set the address as r = 0, r =
1, the memory a33 and the memory b35 are alternately selected.
To supply. From memory a33, [psi _a of the address specified by the equation (8) is, also, from the memory b 35, [psi _b of the specified (8) at this address, respectively r =
0 and r = 1 are read out in this order and output to the first adder 36.

[0060] In the first adder 36 adds the [psi _a is the output of the memory a33, and [psi _b which is the output of the memory b 35, and supplies the bit shift circuit 37. In the bit shift circuit 37, (Ψ _a + Ψ _b ) of r = 0 is shifted by one bit to double the amplitude, and (Ψ _a + Ψ _b ) of r = 1 is not shifted and the second Is supplied to the adder 73. In the second adder 38, after the r = 0 to (Ψ _a + Ψ _b) -1 times, r
= 1 (Ψ _a + Ψ _b ), and the filter output Y
I ((4n + m) T _S ) is output.

Similarly, the address generation circuit 39 includes
The address of the Q component (Q ^r (nT), Q ^r ((n-1) T), ‥,
Q ^r ((n-N + 1) T), m) and (Q ^r ((nN) T), Q ^r ((nN-1) T), ‥, Q ^r ((n
-2N + 1) T), m), and the selector circuit 40
And the selector circuit 42. The selector circuit 40 and the selector circuit 42 alternately select the addresses in the order of r = 0 and r = 1 and supply the addresses to the memory a41 and the memory b43. From memory a41, [psi _a of specified by this address (number 8), also, from the memory b43, [psi _b as specified by this address (8) are respectively r = 0, r =
1 and are output to the first adder 44.

The first adder 44 adds Ψ _a output from the memory a 41 and Ψ _b output from the memory _b 43 and supplies the result to the bit shift circuit 45. In the bit shift circuit 45, (Ψ _a + Ψ _b ) of r = 0 is shifted by 1 bit to double the amplitude, and (Ψ _a + Ψ _b ) of r = 1 is not shifted and the second Is supplied to the adder 46. In the second adder 46, after the r = 0 to (Ψ _a + Ψ _b) -1 times, r
= 1 (Ψ _a + Ψ _b ), and the filter output Y
And outputs the Q ((4n + m) T S).

In this FIR filter circuit 4, 4
A memory of × 2 ^{N + 2} words and four adders are required.

In the bit shift circuits 37 and 45, r =
Instead of bit shifting about (Ψ _a + Ψ _b ) of 0,
without (Ψ _a + Ψ _b) the bit shift of r = 0, to 1/2 the amplitude r = 1 of the (Ψ _a + Ψ _b) shifted by one bit, the second adder 38, 46 , R = 0 (Ψ _a + Ψ _b )
After 1 times, by adding the r = 1 of (Ψ _a + Ψ _b), may be obtained a filter output.

The output of the FIR filter circuit 4 is converted into an analog sampled value signal by a D / A converter 5 and a D / A converter 8, and then smoothed by a post filter 6 and a post filter 9, and the output of the transmitting device is output. Are output from the output terminals 7 and 10.

As described above, in the device of the second embodiment,
Burst transmission control is performed by an FIR filter circuit that does not include a multiplier and is configured using a memory with a small number of words, so that the circuit scale and power consumption can be reduced.

In this embodiment, the case where 2-bit data is input to the FIR filter circuit and the convolution operation result is divided into two parts and processed in the FIR filter circuit has been described. And the addition of memory, it is possible to further increase the number of divisions of the convolution operation result. If the number of bits of the input data is more than 2, the system of the memory address output from the address generation circuit to each selector circuit The number can be accommodated by making it the same number of bits.

(Third Embodiment) In the transmitting apparatus with a burst transmission control function according to the third embodiment, the FIR filter circuit performs time division processing.
The configuration other than the FIR filter circuit and the contents of the filter operation performed by the FIR filter circuit are the same as those in the first embodiment.

As shown in FIG. 4, the FIR filter circuit includes an address generating circuit 51 for generating two-system memory addresses based on two-complement 2-bit I-component data input from a mapping circuit, An address generating circuit 53 for generating two-system memory addresses based on two's complement format and 2-bit Q-component data input from the circuit;
A first selector circuit 52 for sequentially selecting addresses one by one from the memory addresses of the system, and a first selector for sequentially selecting addresses one by one from the two memory addresses of the Q component output from the address generation circuit 53 Circuit 54
And a second selector circuit 55 for alternately selecting a memory address of the I component output from the first selector circuit 52 and a memory address of the Q component output from the first selector circuit 54; A memory 56 in which a result of a convolution operation between transmission data and an impulse response coefficient is stored in advance.
A bit shift circuit 57 that performs a bit shift operation on the convolution operation result read from the memory 56; an adder 58 that adds the output of the bit shift circuit 57;
A register circuit 59 for outputting the data output from 58 in accordance with the output timing of the I component or the Q component.

The table of the memory 56 includes (I ^r (nT), I ^r ((n−1) T), I ^r ((n−2) T), ‥, I ^r ((n-2N + 1)
T), m), and ^{(Q r (nT), Q} r ((n-1) T), Q r ((n-2) T), ‥, Q r ((n-
Using (2N + 1) T), m) as an address, Ψ in (Equation 5) is written in advance. Since the contents of the memory are equal between the I component and the Q component, one table is shared by the I component and the Q component.

Address generation circuit of FIR filter circuit 4
51, like the first embodiment, the address of the I component per sample ^{(I r (nT), I} r ((n-1) T), I r ((n-2) T), ‥ , I ^r ((n-2
N + 1) T), m), the first selector circuit 52 alternately selects the address in the order of r = 0, r = 1, and supplies it to the second selector circuit 55. , Address generation circuit 53
Is the address of the Q component (Q ^r (nT), Q ^r ((n-1) T), Q ^r ((n-2) T), ‥, for each sample, as in the first embodiment. Q ^r ((n-2N +
1) T), m) are generated, and the first selector circuit 54 alternately selects the address in the order of r = 0 and r = 1 and supplies the address to the second selector circuit 55.

In the second selector circuit 55, the memory address of the I component output from the first selector circuit 52 and the first
And the memory address of the Q component, which is the output of the selector circuit 54, is alternately selected and supplied to the memory 56.

From the memory 56, Ψ of (Equation 5) specified by the memory address of the I component is read out in the order of r = 0, r = 1, and then specified by the memory address of the Q component ( Ψ in Equation 5) is read out in the order of r = 0, r = 1, and the data of the I component and the Q component read out by the time division processing is sequentially supplied to the bit shift circuit 57.

In the bit shift circuit 57, the memory output I
Regarding the component and the Q component, Ψ of r = 0 is shifted by one bit to double the amplitude, and Ψ of r = 1 is supplied to the adder 58 without bit shifting. The adder 58 performs addition on the I component and the Q component by time division processing, and for each sample, r = 0 for the I component.
Is multiplied by -1 and then added to ＝ of r = 1, the addition result YI ((4n + m) T _S ) is output to the register circuit 59, and Ψ of r = 0 is added to the Q component. After multiplying by −1, it is added to Ψ of r = 1, and YQ ((4n +
m) T _S) is output to the register circuit 59.

The register circuit 59 stores the YI ((4n + m) T _S ) and YQ ((4n + m) T _S ) input from the adder 58.
Are output in accordance with the output timings of the I component and the Q component, respectively.

In this FIR filter circuit 4, 2
A memory of ^{2N + 2} words and one adder are required.

Also, in the bit shift circuit 57, instead of performing a bit shift on Ψ of r = 0, the Ψ of r = 0 is not shifted, and the Ψ of r = 1 is shifted by one bit to reduce the amplitude by 1 /. It is also possible that the adder 58 multiplies Ψ of r = 0 by −1 and then adds it to Ψ of r = 1 to output the addition result.

The output of the FIR filter circuit 4 is converted into an analog sample value signal by a D / A converter 5 and a D / A converter 8, and then smoothed by a post filter 6 and a post filter 9. It is output from the output terminal 7 and the output terminal 10 as the output of the transmission device.

As described above, in the device of the third embodiment,
By the time-division processing, the number of memories used in the FIR filter circuit can be reduced, and the circuit size can be further reduced.

(Fourth Embodiment) In a transmitter with a burst transmission control function according to a fourth embodiment, time division processing is applied to the configuration of the FIR filter circuit according to the second embodiment. Note that the configuration other than the FIR filter circuit and the FIR
The content of the filter operation performed by the filter circuit is the same as that of the second embodiment.

As shown in FIG. 5, the FIR filter circuit has a two's complement format output from the mapping circuit.
Address generating circuit for generating two addresses for two memories based on I-component data of bits
61, 2's complement format output from the mapping circuit, 2
Address generation circuit for generating two addresses for two memories based on bit Q component data
66, a first selector circuit a62 and a first selector circuit b63 for sequentially selecting an address one by one from the two addresses inputted from the address generation circuit 61, and two addresses inputted from the address generation circuit 66. A first selector circuit a67 and a first selector circuit b68 for sequentially selecting an address one system at a time; a memory address of the I component output from the first selector circuit a62; and a Q address output from the first selector circuit a67. A second selector circuit a64 for alternately selecting a memory address of the component, a memory address of the I component output from the first selector circuit b63, and a first selector circuit a64.
A second selector circuit b69 for alternately selecting the memory address of the Q component output from the selector circuit b68 of the above, and a convolution operation result of the transmission data after the mapping and the impulse response coefficient are divided into two groups, A memory a65 storing one of them, a memory b70 storing the other, a first adder 71 for adding the output data of the memory a65 and the output data of the memory b70, and a first adder A bit shift circuit 72 that performs a bit shift operation on the data output from 71, a second adder 73 that adds the data output from the bit shift circuit 72, and a signal that is output from the second adder 73. Register circuit 74 for outputting the output data in accordance with the output timing of the I component or the Q component.
Is provided.

[0082] the memory a65 table, indicated by (number ^{8) (I r (nT)} , I r ((n-1) T), I r ((n-2) T), ‥, I r ( (n-N + 1) T),
m), and (Q ^r (nT), Q ^r ((n-1) T), Q ^r ((n-2) T), ‥, Q ^r ((n-N +
1) T), m) as the address, (previously written previously [psi _a few 8), also, the memory b70 table, (8)
(I ^r ((nN) T), I ^r ((nN-1) T), ‥, I ^r ((n-2N + 1) T),
m), and (Q ^r ((nN) T), Q ^r ((nN-1) T), ‥, Q ^r ((n-2N + 1) T),
The m) as the address, previously written the [psi _b of (8). Since the contents of these memories are equal between the I component and the Q component, one table is shared by the I component and the Q component in each of the memories 65 and 70.

Address generation circuit of FIR filter circuit 4
Reference numeral 61 denotes the address (I ^r (nT), I ^r ((n−1) T), ‥, I ^r ((n−N + 1)) of the I component for each sample, as in the second embodiment. T), m) and address (I ^r ((nN) T), I ^r ((nN-1) T), ‥, I ^r ((n-2N + 1) T),
m) are output to the first selector circuit a62 and the first selector circuit b63, respectively, and the address generation circuit 66 outputs Q for each sample similarly to the second embodiment. Component address (Q ^r (nT), Q ^r ((n-1) T), ‥, Q ^r ((n-N + 1)
T), m) and (Q ^r ((nN) T), Q ^r ((nN-1) T), ‥, Q ^r ((n-2N + 1) T),
m) are generated and output to the first selector circuit a67 and the first selector circuit b68, respectively.

The first selector circuit a62 and the first selector circuit a67 alternately select their addresses in the order of r = 0 and r = 1 and supply the addresses to the second selector circuit a64. Selector circuit b63 and first selector circuit b
68 alternately selects the address in the order of r = 0 and r = 1 and supplies it to the second selector circuit b69.

In the second selector circuit a64, the memory address of the I component which is the output of the first selector circuit a62,
The memory address of the Q component, which is the output of the first selector circuit a67, is alternately selected and supplied to the memory a65. In the second selector circuit b69, the I address which is the output of the first selector circuit b63 is output. The memory address of the component and the memory address of the Q component output from the first selector circuit b68 are alternately selected and supplied to the memory b70.

From the memory a65, the first selector circuit a
Specified by the memory address output from 62 (Equation 8)
Of [psi _a is read out in the order of r = 0, r = 1, then the first
Of [psi _a is r = 0 of the selector circuit a67 is specified in the output memory address (number 8), r = 1 of the sequentially read, thus time division processing by read I component and Q
[Psi _a data related components are sequentially supplied to the first adder 71. Similarly, from the memory b70, [psi _b of the specified (8) in a memory address output from the first selector circuit b63 is read out in the order of r = 0, r = 1, then Ψ _{b of} (Equation 8) specified by the memory address output from the first selector circuit b68 is r = 0, r =
Read out to the first order, [psi _b data related to the I and Q components read by time division processing manner is sequentially first
Is supplied to the adder 71.

[0087] In the first adder 71, first, the I component, adds the [psi _b output from the output from the memory a65 [psi _a memory b70, then the Q component output from the memory a65 have been [psi _a and the sum of the [psi _b output from the memory b70, when the I component obtained by the division process (Ψ _a + Ψ _b) and the Q component thus a (Ψ _a + Ψ _b), sequentially bit It is supplied to the shift circuit 72.

In the bit shift circuit 72, the first adder 71
For the I component and the Q component output from
_a + Ψ _b ) is shifted by one bit to double the amplitude, and
r = 1 of (Ψ _a + Ψ _b) as it is without bit shift,
It is supplied to a second adder 38. In the second adder 73, the addition for the I component and the Q component is performed by a time division process, and for each I sample, (Ψ _a + Ψ _b ) of r = 0 is multiplied by −1, and then r = It adds 1 (Ψ _a + Ψ _b) and outputs the addition result YI of _{((4n + m) T S} ) to the register circuit 74, also, the Q-component, of _{r = 0 (Ψ a + Ψ} b) the - after 1 times, it adds r = 1 and (Ψ _a + Ψ _b), and outputs the addition result YQ the _{((4n + m) T S} ) to the register circuit 74.

The register circuit 74 outputs YI ((4n + m) T _S ) and YQ ((4n +
m) T _s ) is output in accordance with the output timing of the I component and the Q component, respectively.

In this FIR filter circuit, 2 ×
2 ^{N + 2} words of memory and two adders are required.

[0091] In the bit shift circuit 72, instead of bit shift for (Ψ _a + Ψ _b) of r = 0, r =
(Ψ _a + Ψ _b ) of 0 is not bit-shifted, and (Ψ _a + Ψ _b ) of r = 1
to 1/2 the amplitude _a + _{Ψ b)} the shifted by 1 bit, the second adder 73, after the r = 0 to (Ψ _a + Ψ _b) -1 times, r = 1 of ([psi _a + Ψ _b ) may be added to obtain a filter output.

The output of the FIR filter circuit 4 is converted into an analog sampled value signal by a D / A converter 5 and a D / A converter 8, then smoothed by a post filter 6 and a post filter 9, and then output from the transmitting device. Is output from the output terminal 7 and the output terminal 10.

As described above, in the device of the fourth embodiment,
In the FIR filter circuit, a memory having a small number of words can be used, and the number of memories used can be reduced, so that the circuit size can be further reduced.

[0094]

As is apparent from the above description, the transmitting apparatus of the present invention can perform burst control with a small-scale circuit and with low power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a transmission device with a burst transmission control function in each embodiment of the present invention;

FIG. 2 is a block diagram showing a configuration of an FIR filter circuit in the transmission device according to the first embodiment;

FIG. 3 is a block diagram illustrating a configuration of an FIR filter circuit in a transmission device according to a second embodiment;

FIG. 4 is a block diagram illustrating a configuration of an FIR filter circuit in a transmission device according to a third embodiment;

FIG. 5 is a block diagram showing a configuration of an FIR filter circuit in a transmission device according to a fourth embodiment;

FIG. 6 is a block diagram showing a configuration of a conventional transmission device with a burst transmission control function.

[Explanation of symbols]

 1, 2, 81, 82 input terminal 3, 83 mapping circuit 4, 84 FIR filter circuit 5, 8, 92, 95 D / A converter 6, 9, 93, 96 post filter 7, 10, 94, 97 output terminal 11, 16, 31, 39, 51, 53, 61, 66 Address generation circuit 12, 17 Selector circuit 13, 18, 56 Memory 14, 19, 37, 45, 57, 72 bit shift circuit 15, 20, 58, 87 , 90 adders 32, 40 selector circuits a 33, 41, 65 memories a 34, 42 selector circuits b 35, 43, 70 memories b 36, 44, 71 first adders 38, 46, 73 second adders 52, 54 First selector circuit 55 Second selector circuit 59, 74 Register circuit 62, 67 First selector circuit a 63, 68 First selector circuit b 64 Second selector circuit a 69 Second selector circuit b 85, 88 Shift register circuit 86, 89 Multiplier 91 Impulse response coefficient generation circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-223232 (JP, A) JP-A-8-154105 (JP, A) JP-A-6-205058 (JP, A) JP-A-6-205050 205056 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (7)

(57) [Claims] 1. A mapping circuit that outputs quadrature in-phase impulse data corresponding to transmission data when burst transmission is on, and “0” when burst transmission is off, and an FIR filter circuit that limits the band of a burst waveform. In a transmission device having a burst transmission control function, the mapping circuit outputs each data of an in-phase component and a quadrature component in a two's complement format, and the FIR filter circuit includes an address generation circuit, a memory, a bit shift circuit, an adder And a convolution operation between input data input from the mapping circuit and an impulse response coefficient using a selector circuit and a selector circuit. 2. An FIR filter circuit comprising: an address generation circuit for generating the same number of memory addresses as the number of bits of input data; and one system from a plurality of memory addresses generated by the address generation circuit. A selector circuit for selecting, a memory storing a convolution operation result of the input data and the impulse response coefficient, and a bit shift operation of the convolution operation result read from the memory by a memory address selected by the selector circuit. The transmission device according to claim 1, further comprising a bit shift circuit for performing the operation, and an adder for adding an output of the bit shift circuit. 3. An address generation circuit, a selector circuit, a memory, a bit shift circuit, and two adders are provided in correspondence with input data of an in-phase component and a quadrature component input from the mapping circuit. Claim 2
The transmitting device according to claim 1. 4. An address generating circuit for generating a memory address having a number of systems (A × B) B times the number A of bits of input data, wherein the FIR filter circuit comprises: B input selectors, B selector circuits for sequentially selecting one system at a time from these memory addresses, B memory for dividing and storing a result of convolution of input data and an impulse response coefficient,
A first adder that adds the data read from each of the memories according to the memory address selected by each of the selector circuits to obtain a convolution operation result; and a bit of the convolution operation result output from the first adder. The transmission device according to claim 1, further comprising: a bit shift circuit that performs a shift operation; and a second adder that adds an output of the bit shift circuit. 5. The address generation circuit, the B selector circuits, the B memories, the first memory and the first memory in correspondence with input data of the in-phase component and the quadrature component input from the mapping circuit.
The transmission device according to claim 4, comprising two systems of the adder, the bit shift circuit, and the second adder. 6. An address generator according to claim 1, wherein said FIR filter circuit generates two memory addresses corresponding to the in-phase component and quadrature component data input from said mapping circuit, the number being the same as the number of bits of the input data. A circuit, two first selector circuits for sequentially selecting one system from a plurality of memory addresses generated by each of the address generation circuits, and a memory address output from each of the first selector circuits. , A memory storing a result of convolution of input data and an impulse response coefficient, and a memory read out from the memory by a memory address selected by the second selector circuit. A bit shift circuit for performing a bit shift operation on a convolution operation result; and The transmission device according to claim 1, further comprising an adder that obtains output data corresponding to the in-phase component and the quadrature component by time division processing. 7. The FIR filter circuit according to in-phase component and quadrature component data input from the mapping circuit, the memory address having a system number (A × B) B times the bit number A of the input data. And two address generation circuits for generating
And 2 × B first selector circuits for sequentially selecting one system at a time from these memory addresses, and two first selector circuits connected to separate address generation circuits.
B second selector circuits for alternately selecting memory addresses output from the selector circuit, B memories for dividing and storing a result of convolution of input data and an impulse response coefficient, A first adder that adds the data read from each of the memories according to the memory address selected by each of the selector circuits to obtain a convolution operation result; and a bit of the convolution operation result output from the first adder. A bit shift circuit that performs a shift operation; and a second adder that adds outputs of the bit shift circuit and obtains output data corresponding to the in-phase component and the quadrature component by time-division processing. Claim 1
The transmitting device according to claim 1.