JP3317524B2 - Color signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal processing circuit used for a reproduction system of an electronic still video.

[0002]

2. Description of the Related Art Electronic still video, for example, records and reproduces a color still image on a magnetic recording carrier such as a floppy disk.
Since the two kinds of color difference signals of RY and BY are FM-modulated at different center frequencies and are recorded in a line-sequential manner, R and
A process of rearranging the -Y and BY line-sequential color difference signals into an RY color difference signal and a BY color difference signal for each horizontal scanning line, that is, a so-called synchronization process was required.

FIG. 5 shows a color signal processing circuit in a conventional electronic still video reproducing system.
When a color still image recorded on the floppy disk 2 rotated and driven by the head unit 3 is read by the head unit 3, first, a color image signal output from the head unit 3 is input to the color signal demodulation circuit 4, and RY and The two types of color difference signals of BY are demodulated into line-sequential color signals alternately arranged.

Next, the line-sequential color signals output from the color signal demodulation circuit 4 are rearranged into RY color difference signals and BY color difference signals for each horizontal scanning line by a synchronizing process. The RY color difference signal is stored in the memory 5 and the BY color difference signal is stored in the memory 6 in address order.

Here, in order to perform the synchronization processing, a CCD (charge coupled device) 7 having a capacity for one horizontal scanning line is used.
, Two clamp circuits 8 and 9, two analog switches 10 and 11, and two A / D (analog / digital) converters 12 and 13.

That is, the line-sequential color signal output from the color signal demodulation circuit 4 includes an RY color difference signal for one horizontal scanning line (1H) as shown in FIG. This is a signal in which the BY color difference signals for the line (1H) are alternately arranged, and a pair of the RY color difference signal and the B
The color information of one horizontal scanning line is represented by the Y color difference signal.

After the line-sequential color signal is clamped by the first clamp circuit 8 in synchronization with the crank pulse CP1, the signal is input to the H terminal of the first analog switch 10 and the second analog switch 11 L terminal.

The line-sequential color signal is delayed by one horizontal scanning line by the CCD 7 as shown in FIG.
And then input to the L terminal of the first analog switch 10 and to the H terminal of the second analog switch 11.

The first and second clamp circuits 8, 9 are provided with R
It is provided to make the center frequency of the -Y color difference signal (1.2 MHz, deviation: 0.7 MHz) coincide with the center frequency of the BY color difference signal (1.3 MHz, deviation: 0.5 MHz).

First and second analog switches 10, 1
1 are synchronized with the line pulse LP of the color signal, respectively.
The terminal and the H terminal are selectively connected alternately. First, when the L terminal is selected, the RY1 color difference signal of the output signal (FIG. 6A) from the first clamp circuit 8 is input to the second A / D converter 13, and an 8-bit signal is input. The data is converted into digital data, and is written into the address "0" of the RY memory 5 under the control of the memory control circuit 14 and the address generation circuit 15.

Next, when the H terminal is selected, the second A / A
The (R−Y1) color difference signal of the output signal (FIG. 6B) from the second clamp circuit 9 is input to the D converter 13,
The digital data is converted into digital data of 1 bit and written into the address "1" of the RY memory 5, and the first A / D
The BY1 color difference signal of the output signal (FIG. 6A) from the first clamp circuit 8 is input to the converter 12 and converted into 8-bit digital data. "Written at the address.

Next, when the L terminal is selected, the second A /
The R-Y2 color difference signal of the output signal from the first clamp circuit 8 is input to the D converter 13, converted into 8-bit digital data, and written to the address "2" of the RY memory 5. At the same time, the (B−Y1) color difference signal of the output signal from the second clamp circuit 9 is input to the first A / D converter 12 and is converted into 8-bit digital data.
The data is written to the address “2” of the BY memory 6.

Thereafter, similarly, R for each horizontal scanning line is
The -Y color difference signal is stored in the RY memory 5 and the BY color difference signal for each horizontal scanning line is stored in the BY memory 6 in address order.

Thereafter, under the control of the memory control circuit 14 and the address generation circuit 15, the RY color difference signals and the BY color difference signals (digital data) for one horizontal scanning line are simultaneously read from the memories 5 and 6 in the order of addresses. If they are converted into analog signals by D / A (digital / address) converters 16 and 17, respectively, the color encoder 18
And encodes it to output a decoded video signal.

[0015]

As described above, in this type of conventional color signal processing circuit, the RY color difference signal and the B
CC to make the line-sequential color signal of the Y color difference signal
D7, the first and second clamp circuits 8, 9, the first and second clamp circuits
, And the first and second A / D converters 12 and 13 are required, the circuit configuration is complicated, and the storage as the RY memory 5 and the BY memory 6 is required. It was necessary to secure a large area, and it was difficult to reduce the size and cost.

As can be seen from FIGS. 6C and 6D, the RY color difference signal and the BY color difference signal of the same horizontal scanning line are called from the memories 5 and 6 with a difference of one line. Then, since the data is encoded after being converted into an analog signal, there is a disadvantage that the color change is not the original color.

Therefore, the present invention provides a RY color difference signal and a BY color signal.
A line-sequential color signal in which color difference signals are alternately arranged can be written to a memory without synchronizing, so that a circuit configuration can be simplified and a memory capacity can be reduced, and RY of the same horizontal scanning line can be achieved. An object of the present invention is to provide a color signal processing circuit capable of simultaneously encoding a color difference signal and a BY color difference signal to output a decoded video signal and improving the quality of color reproduction.

[0018]

According to the present invention, a color image signal read from a record carrier is inputted, and an R-Y color difference signal for one horizontal scanning line and a B-color signal for one horizontal scanning line are obtained from the color image signal. A color signal demodulation means for demodulating and outputting a line-sequential color signal in which Y color difference signals are alternately arranged, and clamping the line-sequential color signal from the color signal demodulation means in synchronization with a crank pulse; Center frequency and BY
A clamp circuit unit for matching the center frequency of the color difference signal; and a RY color difference for one horizontal scanning line in synchronization with a line pulse of the line sequential color signal output from the line sequential color signal output from the clamp circuit unit. Color difference signal selecting means for alternately selecting the signal and the BY color difference signal for the same one horizontal scanning line; and the RY color difference signals for one horizontal scanning line which are alternately selected by the color difference signal selecting means. An analog / digital conversion means for sequentially inputting the BY color difference signals for one horizontal scanning line, converting the data into digital data, and outputting the data; and a pair of memories receiving the digital data output by the analog / digital conversion means as input The RY color difference signal digital data is written into one of the pair of memories in address order, and the BY color difference signal digital data is written into the other memory in address order. And writing the data write control means, reads out the two horizontal scanning lines each to a pair of memory
A data read control means for supplying an address and simultaneously reading data of the same address twice in succession in address order from the pair of memories, and an analog conversion of the data read from the pair of memories by the read control means. Encoding means for post-encoding and outputting a decoded video signal.

[0019]

According to the circuit of the present invention having such a configuration, the color image signal read from the record carrier is converted by the color signal demodulating means into the RY color difference signal for one horizontal scanning line and the RY color difference signal for one horizontal scanning line. After being demodulated into line-sequential color signals in which the BY color difference signals are alternately arranged, the signal is demodulated without synchronization.
The center of the RY color difference signal
The frequency matches the center frequency of the BY color difference signal.
Is, B-Y color difference signals in synchronization with the line pulses of the line sequential color signal one horizontal scanning line of R-Y color difference signal and the one horizontal scanning line is Ru are selected alternately by the further color difference signal selecting means . The data is converted into digital data by A / D conversion means, and the digital data of the RY color difference signal is written into one memory in the order of addresses by the data writing control means, and the digital data of the BY color difference signal is written into the other memory. Are written in address order.

In this way, the data written to the pair of memories is read from the two memories simultaneously and sequentially at the same address twice in succession by the data read control means. Thereby, the RY color difference signal and the B signal of the same horizontal scanning line are arranged in the same order as when the synchronization processing is performed.
-Read without deviation from the Y color difference signal.

Then, the RY color difference signal and the BY color difference signal of the same horizontal scanning line read out from the pair of memories are analog-converted, coded, and output as a decoded video signal.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a color signal processing circuit of an electronic still video reproduction system will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the color signal processing circuit of this embodiment. For convenience of explanation, the same parts as those of the conventional circuit shown in FIG. 5 are denoted by the same reference numerals, and detailed description is omitted.

The color signal processing circuit of this embodiment converts a color image signal output from the head unit 3 for reading a color still image recorded on the floppy disk 2 into two types of RY and BY color difference signals. A color signal demodulation circuit 4 is provided as color signal demodulation means for demodulating signals into line-sequential color signals alternately arranged.

Further, the circuit of this embodiment includes a first clamp circuit 8 for clamping the output signal from the color signal demodulation circuit 4 in synchronization with the crank pulse CP1, and clamping the output signal in synchronization with the crank pulse CP2. And a center frequency (1.
2 MHz, deviation: 0.7 MHz, and the center frequency of the BY color difference signal (1.3 MHz, deviation:
0.5 MHz).

The output signals from the first and second clamp circuits 8 and 9 are changed for each horizontal scanning line by an analog switch 21 which is switched in synchronization with the line pulse LP of the line sequential color signal. A / D converter 2 as an A / D (analog / digital) conversion means that selects alternately
After converting the data into 8-bit digital data by a pair of memories (RY memory 5 and BY memory 6)
Is configured to be input.

The operation of writing and reading data to and from the RY memory 5 and the BY memory 6 is controlled by a memory control circuit 14 and an address generation circuit 15. That is, the memory control circuit 14 controls both the memories 5 and 6
, A write enable (WE) signal and a read enable (RE) for the RY memory 5, a row control clock RASR and a column control clock CASR for the RY memory 5, and a row control clock RASB and a And a column control clock CASB. Further, the address generation circuit 15 includes the two memories 5,
6 is given a write address or a read address in common.

Here, control at the time of writing digital data will be described with reference to the timing charts of FIGS.

As shown in FIGS. 2A and 4A, the color signal demodulation circuit 4 demodulates and outputs a line-sequential color signal of two types of color difference signals of RY and BY. . Thus, the clamp pulse CP1 is supplied to the first clamp circuit 8 at the timing shown in FIG. 2B, and the clamp pulse CP is supplied to the second clamp circuit 9 at the timing shown in FIG. CP2 is supplied. The line pulse LP is supplied to the analog switch 21 at the timing shown in FIG.

When writing digital data, the memory control circuit 14 activates the write enable signal WE as shown in FIG.
As shown in (g), the row control clock RASR for the RY memory 5 and the row control clock RASB for the BY memory 6 are alternately activated every 1H to hold the row address. FIG.
As shown in (h), the write row address “0”,
"1", "2",... Are supplied to both memories 5, 6. R-
Column control clocks CASR and B- for the Y memory 5
The column control clock CASB for the Y memory 6 receives a column address supplied by the address generation circuit 15 every 1H, and writes data to the memory.

As a result, as shown in FIG.
The RY color difference signals converted into digital data by the A / D converter 22 are written in the Y memory 5 in the order of addresses.
As shown in FIG. 4C, the BY color difference signals of the digital data are written in the BY memory 6 in the order of addresses. Here, the memory control circuit 14 and the address generation circuit 15 constitute data write control means.

Next, control for reading digital data will be described with reference to the timing charts of FIGS.

At the time of digital data reading, the memory control circuit 14 activates the read enable signal RE as shown in FIG.
As shown in (d), the row control clock RASR for the RY memory 5 and the row control clock RASB for the BY memory 6 are simultaneously activated every 1H, and the row address is held. FIG.
As shown in (e), read addresses "0", "1", "2",... Are sequentially supplied to both memories 5 and 6 every 2H. Column control clock CASR for RY memory 5
And the column control clock CASB for the BY memory 6
Also receives the column address supplied by the address generation circuit 15 and reads data from the memory.

As a result, as shown in FIGS. 4 (d) and 4 (e), data of the same address is simultaneously and successively read twice from the RY memory 5 and the BY memory 6 in the order of addresses. . Here, the memory control circuit 14 and the address generation circuit 15 constitute data read control means.

The digital data read from the RY memory 5 and the BY memory 6 are
After being converted into analog data by the D / A converters 16 and 17, the data is input to the color encoder 18. The data is encoded by the color encoder 18 and output as a decoded video signal. Here, a pair of D / A converters 16 and 17 and a color encoder 18
Constitutes encoding means.

In the circuit of this embodiment having such a configuration, the color image signal read from the floppy disk 2 is converted by the color signal demodulation circuit 4 into the RY color difference signal for one horizontal scanning line and the RY color difference signal for the same horizontal scanning line. After being demodulated into a line-sequential color signal in which the above-mentioned BY color difference signals are alternately arranged, the data is converted into digital data by the A / D converter 22 without being synchronized. The R-Y memory 5 has R-
The digital data of the Y color difference signal is selected and written in the address order, and the digital data of the BY color difference signal is selected and written in the BY memory 6 in the address order.

On the other hand, the digital data written to the RY memory 5 and the BY memory 6 are read out simultaneously at the same time in the address order and twice continuously at the same address. Thereby, the RY color difference signal and the B signal of the same horizontal scanning line are arranged in the same order as when the synchronization processing is performed.
The data is read from the pair of memories 5 and 6 without deviation from the -Y color difference signal. The digital data read from the pair of memories 5 and 6 are converted into analog signals by D / A converters 16 and 17, respectively, and then encoded by the color encoder 18 to be output as a decoded video signal. .

Accordingly, compared with the conventional color signal processing circuit shown in FIG. 5, the CCD 7 required for the synchronization processing can be omitted, and the number of analog switches and A / D converters can be reduced by one. Can be simplified.

Further, the storage capacities of the RY memory 5 and the BY memory 6 may be half those of the prior art, and it is not necessary to secure a large storage area for each of the memories 5 and 6. As a result, the size and cost of the circuit can be easily reduced, and the size and cost of the electronic still video can be easily reduced.

As is clear from FIGS. 4D and 4E, the RY color difference signal and the BY color difference signal of the same horizontal scanning line are simultaneously read out from the pair of memories 5 and 6 and converted into an analog signal. Further, since the decoded video signal is output after encoding, the color change becomes the original color, and the quality of color reproduction can be improved.

The present invention is not limited to a color signal processing circuit of an electronic still video, but can be applied to a color signal processing circuit in another color image reproducing system.

[0042]

As described in detail above, according to the present invention, R
Alternating -Y color difference signal and B-Y color difference signals from the line sequential color signals are arranged alternately with R-Y color difference signal and B-Y color difference signals
To digital data without synchronization
In addition, since data can be written in the memory, the circuit configuration can be simplified, the storage capacity of the mounted memory can be reduced, the circuit can be reduced in size and cost can be reduced, and the RY color difference signal and the B- Since a decoded video signal can be output by simultaneously encoding the Y color difference signal, a color signal processing circuit capable of improving the quality of color reproduction can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a circuit according to an embodiment of the present invention.

FIG. 2 is a main part timing chart at the time of writing memory data in the circuit of the embodiment.

FIG. 3 is a main part timing chart at the time of reading memory data in the circuit of the embodiment.

FIG. 4 is a main data configuration diagram in the circuit of the embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional circuit.

FIG. 6 is a main data configuration diagram of the conventional circuit.

[Explanation of symbols]

 4, a color signal demodulation circuit; 5, a RY memory; 6, a BY memory; 8, 9, a first and a second clamp circuit; 14, a memory control circuit; 15, an address generation circuit; 17: D / A converter, 18: Color encoder, 21: Analog switch, 22: A / D converter.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-218287 (JP, A) JP-A 61-60585 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 9/79-9/898

Claims (1)

(57) [Claims] 1. A color image signal read from a record carrier is input, and RY color difference signals for one horizontal scanning line and BY color difference signals for the same horizontal scanning line are alternately arranged from the color image signal. A color signal demodulation means for demodulating and outputting a line-sequential color signal; clamping the line-sequential color signal from the color signal demodulation means in synchronization with a crank pulse to obtain a center frequency of the RY color difference signal and a BY color difference A clamp circuit for matching the center frequency of the signal; and a line-sequential color signal output from the clamp circuit for synchronizing with the line pulse of the line-sequential color signal, the RY color difference for the one horizontal scanning line. Color difference signal selecting means for alternately selecting the signals and the B-Y color difference signals for the same one horizontal scanning line; RY color difference signals for one horizontal scanning line alternately selected by the color difference signal selecting means; 1 horizontal run A / D conversion means for sequentially inputting the BY color difference signals for the scanning lines, converting the data into digital data, and outputting the digital data; a pair of memories receiving the digital data output by the analog / digital conversion means; The digital data of the RY color difference signal is written into one of the pair of memories in the order of addresses, and the other is the BY data.
Data writing control means for writing the digital data of the color difference signal in the order of addresses, and reading out the pair of memories every two horizontal scanning lines
Data read control means for supplying an address and simultaneously and successively reading data of the same address twice in the order of addresses from the pair of memories; and converting the data read from the pair of memories by the read control means into analog data. And a coding means for coding and outputting a decoded video signal.