JP3317295B2 - Manufacturing method of capacitive element - Google Patents

Manufacturing method of capacitive element

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Publication number
JP3317295B2
JP3317295B2 JP35689499A JP35689499A JP3317295B2 JP 3317295 B2 JP3317295 B2 JP 3317295B2 JP 35689499 A JP35689499 A JP 35689499A JP 35689499 A JP35689499 A JP 35689499A JP 3317295 B2 JP3317295 B2 JP 3317295B2
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Japan
Prior art keywords
heat treatment
temperature heat
low
temperature
capacitor
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Expired - Fee Related
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JP35689499A
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JP2001177075A (en
Inventor
一郎 山本
敏洋 飯塚
芳健 加藤
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NEC Corp
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NEC Corp
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Priority to JP35689499A priority Critical patent/JP3317295B2/en
Priority to US09/736,562 priority patent/US20010004533A1/en
Priority to KR1020000077149A priority patent/KR20010062498A/en
Publication of JP2001177075A publication Critical patent/JP2001177075A/en
Priority to US10/135,620 priority patent/US6602722B2/en
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Publication of JP3317295B2 publication Critical patent/JP3317295B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/409—Oxides of the type ABO3 with A representing alkali, alkaline earth metal or lead and B representing a refractory metal, nickel, scandium or a lanthanide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、容量素子の製造
方法に関し、特に、ペロブスカイト（ｐｅｒｏｖｓｋｉ
ｔｅ）構造の誘電体を用いた容量素子の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitive element.
With regard to the method , in particular perovskite (perovskite)
te) The present invention relates to a method for manufacturing a capacitive element using a dielectric having a structure.

【０００２】[0002]

【従来の技術】従来、ＤＲＡＭ（ｄｙｎａｍｉｃ ｒａ
ｎｄｏｍ ａｃｃｅｓｓ ｍｅｍｏｒｙ）のセルキャパ
シタに用いられる誘電膜として、例えば、ペロブスカイ
ト構造の強誘電体膜が知られている。2. Description of the Related Art Conventionally, a dynamic random access memory (DRAM) has been used.
For example, a ferroelectric film having a perovskite structure is known as a dielectric film used for a cell capacitor of an ND (access memory).

【０００３】ペロブスカイト構造を有するものには、バ
リウム（Ｂａ）及びストロンチウム（Ｓｒ）を組み合わ
せたチタン酸バリウムストロンチウム（（Ｂａ，Ｓｒ）
ＴｉＯ3 ：ＢＳＴ）や、ＢＳＴの内で、Ｂａが含まれず
Ｓｒのみのチタン酸ストロンチウム（ＳｒＴｉＯ3 ）が
ある。[0003] Barium strontium titanate ((Ba, Sr)) comprising a combination of barium (Ba) and strontium (Sr) has a perovskite structure.
TiO 3: BST) and, among the BST, it is not included Ba Sr only strontium titanate (SrTiO 3).

【０００４】このような高誘電率のＢＳＴを容量絶縁膜
として用いたキャパシタの製造方法を説明する。先ず、
ルテニウム（Ｒｕ）を用いて下部電極を形成する。次
に、この下部電極の上に、熱ＣＶＤ（ｃｈｅｍｉｃａｌ
ｖａｐｏｒ ｄｅｐｏｓｉｔｉｏｎ）により成膜温度
４００℃でＢＳＴを成膜し、その後、ＢＳＴ膜の結晶化
のために６５０℃，１０分間の熱処理を行い、このＢＳ
Ｔ成膜と成膜後の熱処理を複数回（例えば４回）繰り返
す。次に、Ｒｕを用いてキャパシタ上部電極を形成す
る。A method of manufacturing a capacitor using such a high dielectric constant BST as a capacitance insulating film will be described. First,
A lower electrode is formed using ruthenium (Ru). Next, on this lower electrode, thermal CVD (chemical
A BST film is formed at a film formation temperature of 400 ° C. by vapor deposition, and then a heat treatment is performed at 650 ° C. for 10 minutes to crystallize the BST film.
The T film formation and the heat treatment after the film formation are repeated a plurality of times (for example, four times). Next, a capacitor upper electrode is formed using Ru.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、上述し
た製造方法により得られたキャパシタにおいては、十分
低いリーク特性が得られなかった。リーク特性の劣化は
ＤＲＡＭの保持特性を低下させてしまう。リーク特性及
び誘電率が劣化するのは、３００〜４００℃の低温で特
異的に離脱する不純物（炭素や水素等）が多く含まれて
いるためと考えられる。このため、不純物の離脱に対応
した低温による熱処理が必要であると思われる。However, in the capacitor obtained by the above-described manufacturing method, a sufficiently low leak characteristic cannot be obtained. Deterioration of the leak characteristics lowers the holding characteristics of the DRAM. It is considered that the reason why the leak characteristics and the dielectric constant are deteriorated is that a large amount of impurities (carbon, hydrogen, etc.) which are specifically released at a low temperature of 300 to 400 ° C. are contained. For this reason, it is considered that a heat treatment at a low temperature corresponding to the elimination of impurities is necessary.

【０００６】上述したようなＢＳＴ成膜における結晶化
熱処理については、例えば、Ｍ．Ｋｉｙｏｔｏｓｈｉ
ｅｔ ａｌ．１９９９ Ｓｙｍｐｏｓｉｕｍ ｏｎ Ｖ
ＬＳＩ Ｔｅｃｈｎｏｌｏｇｙ Ｄｉｇｅｓｔ ｏｆ
Ｔｅｃｈｎｉｃａｌ Ｐａｐｅｒｓ．ｐｐ．１０１〜１
０２に開示されているが、低温による熱処理については
何も述べられていない。The crystallization heat treatment in the BST film formation described above is described in, for example, M. Kiyotoshi
et al. 1999 Symposium on V
LSI Technology Digest of
Technical Papers. pp. 101-1
No. 02, but nothing about heat treatment at low temperatures.

【０００７】また、特開平１１−２４３１７７号公報に
は、リーク特性を改善することを目的とした半導体装置
及びその製造方法が開示されているが、この半導体装置
及びその製造方法においては、高温度の熱処理によりＢ
ＳＴ膜を２段階で成膜しており、低温による熱処理につ
いては述べられていない。Japanese Unexamined Patent Application Publication No. 11-243177 discloses a semiconductor device and a method of manufacturing the same for the purpose of improving the leakage characteristics. B by heat treatment of
The ST film is formed in two stages, and the heat treatment at a low temperature is not described.

【０００８】この発明の目的は、不純物の離脱に対応し
た低温による熱処理を行って、リーク特性及び誘電率の
劣化を防ぐことができる容量素子の製造方法を提供する
ことである。An object of the present invention is to provide a method of manufacturing a capacitor element capable of performing heat treatment at a low temperature corresponding to elimination of impurities to prevent deterioration of leak characteristics and dielectric constant.

【０００９】[0009]

【課題を解決するための手段】上記目的を達成するた
め、この発明に係る容量素子の製造方法は、誘電体膜を
上部電極及び下部電極で挟み込んだ容量素子の製造方法
において、ＡＢＯ3 複合酸化物からなる高誘電体膜の成
膜後、前記高誘電体膜を高温熱処理する高温熱処理工程
と、前記高温熱処理の処理温度より低い温度で低温熱処
理する低温熱処理工程とを有し、前記高誘電体膜の成膜
と前記高温熱処理、或いは前記高誘電体膜の成膜と前記
高温熱処理と前記低温熱処理は、それぞれ組み合わされ
て複数回繰り返されることを特徴としている。To achieve the above object, according to an aspect of manufacturing method of the capacitor according to the present invention is a method of manufacturing a capacitor element sandwiched a dielectric film at the upper and lower electrodes, ABO 3 complex oxide after the deposition of the high dielectric film made of things, possess the high temperature heat treatment step of high temperature heat treatment of the high dielectric film, and a low-temperature heat treatment step of low-temperature heat treatment in the high-temperature heat treatment process temperature lower than the temperature, the high dielectric Body film formation
And the high-temperature heat treatment, or the formation of the high dielectric film and the
The high-temperature heat treatment and the low-temperature heat treatment are each combined.
Is characterized in Rukoto repeated multiple times Te.

【００１０】上記構成を有することにより、ＡＢＯ3 複
合酸化物からなる高誘電体膜の成膜後、前記高誘電体膜
を高温熱処理する高温熱処理工程と、前記高温熱処理の
処理温度より低い温度で低温熱処理する低温熱処理工程
とを経て、誘電体膜を上部電極及び下部電極で挟み込ん
だ容量素子が製造される。この際、前記高誘電体膜の成
膜と前記高温熱処理、或いは前記高誘電体膜の成膜と前
記高温熱処理と前記低温熱処理は、それぞれ組み合わさ
れて複数回繰り返される。これにより、不純物の離脱に
対応した低温による熱処理を行って、リーク特性及び誘
電率の劣化を防ぐことができる。With the above structure, after forming the high dielectric film made of the ABO 3 composite oxide, a high temperature heat treatment step of performing high temperature heat treatment on the high dielectric film, and a high temperature heat treatment step at a temperature lower than the processing temperature of the high temperature heat treatment. Through a low-temperature heat treatment step of performing a low-temperature heat treatment, a capacitor in which the dielectric film is sandwiched between the upper electrode and the lower electrode is manufactured. At this time, the formation of the high dielectric film is performed.
Before forming the film and the high-temperature heat treatment or forming the high-dielectric film
The high temperature heat treatment and the low temperature heat treatment are combined
And repeated several times. This makes it possible to perform a heat treatment at a low temperature corresponding to the desorption of the impurities, thereby preventing the leak characteristics and the dielectric constant from deteriorating.

【００１１】[0011]

【００１２】[0012]

【発明の実施の形態】以下、この発明の実施の形態につ
いて図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１３】図１は、この発明の実施の形態に係る高誘
電率薄膜キャパシタを有する半導体装置の断面図であ
る。図１に示すように、高誘電率の薄膜キャパシタ（容
量素子）１０は、ＭＯＳＦＥＴ（ｍｅｔａｌ ｏｘｉｄ
ｅ ｓｅｍｉｃｏｎｄｕｃｔｏｒ ｆｉｅｌｄ ｅｆｆ
ｅｃｔ ｔｒａｎｓｉｓｔｏｒ）１１と共に、半導体装
置であるＤＲＡＭのメモリセル１２を形成している。FIG. 1 is a sectional view of a semiconductor device having a high dielectric constant thin film capacitor according to an embodiment of the present invention. As shown in FIG. 1, a thin film capacitor (capacitance element) 10 having a high dielectric constant includes a MOSFET (metal oxide).
e semiconductor field eeff
In addition, the memory cell 12 of the DRAM, which is a semiconductor device, is formed together with the E.C.

【００１４】ＭＯＳＦＥＴ１１は、ｐ型シリコン基板１
３の素子分離絶縁膜１４により分離された領域上に、ゲ
ート酸化膜１５を介して形成されたゲート電極１６を有
している。ゲート電極１６両側のｐ型シリコン基板１３
には、ソース側及びドレイン側のｎ型拡散層１７が設け
られている。このＭＯＳＦＥＴ１１の上には、ポリシリ
コンプラグ１８を有する層間絶縁膜１９を介して、薄膜
キャパシタ１０が形成されている。The MOSFET 11 is a p-type silicon substrate 1
A gate electrode 16 formed via a gate oxide film 15 is provided on a region separated by the third element isolation insulating film 14. P-type silicon substrate 13 on both sides of gate electrode 16
Are provided with n-type diffusion layers 17 on the source side and the drain side. On the MOSFET 11, a thin film capacitor 10 is formed via an interlayer insulating film 19 having a polysilicon plug 18.

【００１５】薄膜キャパシタ１０は、層間絶縁膜１９上
に層状に形成されたシリコンコンタクト層２０及び耐シ
リコン拡散導電層２１を介して、記載順に積み重ねられ
たキャパシタ下部電極２２、キャパシタ絶縁膜２３及び
キャパシタ上部電極２４を有している。キャパシタ下部
電極２２は、耐シリコン拡散導電層２１上に、キャパシ
タ絶縁膜２３は、シリコンコンタクト層２０、耐シリコ
ン拡散導電層２１及びキャパシタ下部電極２２を覆うよ
うに、キャパシタ上部電極２４は、キャパシタ絶縁膜２
３上に、それぞれ積み重ねられて層構造を有している。The thin film capacitor 10 includes a capacitor lower electrode 22, a capacitor insulating film 23 and a capacitor stacked in the stated order via a silicon contact layer 20 and a silicon diffusion resistant conductive layer 21 formed in layers on an interlayer insulating film 19. It has an upper electrode 24. The capacitor lower electrode 22 is formed on the silicon diffusion-resistant conductive layer 21, and the capacitor insulating film 23 is formed on the silicon contact layer 20, the silicon diffusion-resistant conductive layer 21 and the capacitor lower electrode 22. Membrane 2
3 on top of each other to have a layered structure.

【００１６】このキャパシタ絶縁膜２３には、ペロブス
カイト構造の強誘電体膜が用いられている。ペロブスカ
イト構造を有するものには、バリウム（Ｂａ）及びスト
ロンチウム（Ｓｒ）を組み合わせたチタン酸バリウムス
トロンチウム（（Ｂａ，Ｓｒ）ＴｉＯ3 、以下ＢＳＴと
略称する）や、ＢＳＴの内でＢａが含まれずＳｒのみの
チタン酸ストロンチウム（ＳｒＴｉＯ3 、以下ＳＴＯと
略称する）がある。As the capacitor insulating film 23, a ferroelectric film having a perovskite structure is used. Barium strontium titanate ((Ba, Sr) TiO 3 , hereinafter abbreviated as BST), which is a combination of barium (Ba) and strontium (Sr), which has a perovskite structure, and Sr which does not contain Ba in BST There is only strontium titanate (SrTiO 3 , hereinafter abbreviated as STO).

【００１７】これらは、キャパシタの薄膜化に適してお
りＤＲＡＭのキャパシタの材料として有望である。この
ような高誘電率のＢＳＴを容量絶縁膜として金属製の両
電極２２，２４で挟んだ薄膜キャパシタ１０を有する半
導体装置の製造方法を、以下に説明する。These are suitable for thinning capacitors and are promising as materials for DRAM capacitors. A method of manufacturing a semiconductor device having the thin film capacitor 10 in which such a high-permittivity BST is used as a capacitor insulating film and sandwiched between both electrodes 22 and 24 made of metal will be described below.

【００１８】図２（ａ）〜図５（ｈ）は、図１の薄膜キ
ャパシタを有する半導体装置の製造工程を示す断面図で
ある。図２（ａ）〜図５（ｈ）に示すように、先ず、既
知の方法に従って、ｐ型シリコン基板１３上の素子分離
絶縁膜１４で分離された領域に、ゲート酸化膜１５、ゲ
ート電極１６、及びゲート電極１６の両側下方に位置さ
せたｎ型拡散層１７等を作り込み、ＭＯＳＦＥＴ１１を
形成する（図２（ａ）参照）。FIGS. 2A to 5H are cross-sectional views showing the steps of manufacturing a semiconductor device having the thin film capacitor of FIG. As shown in FIGS. 2A to 5H, first, according to a known method, a gate oxide film 15 and a gate electrode 16 are formed in a region separated by an element isolation insulating film 14 on a p-type silicon substrate 13. Then, an n-type diffusion layer 17 and the like located below both sides of the gate electrode 16 are formed to form the MOSFET 11 (see FIG. 2A).

【００１９】次に、ＭＯＳＦＥＴ１１の上に、ＳｉＯ2
からなる膜厚３００ｎｍの層間絶縁膜１９をＣＶＤ法等
により成膜し、その後、層間絶縁膜１９を表面から基板
１３側に向けて貫通する接続孔２５を開口する（図２
（ｂ）参照）。Next, on the MOSFET 11, SiO 2
A 300-nm-thick interlayer insulating film 19 made of CVD is formed by a CVD method or the like, and thereafter, a connection hole 25 penetrating the interlayer insulating film 19 from the surface toward the substrate 13 is opened (FIG. 2).
(B)).

【００２０】次に、層間絶縁膜１９上に、ＣＶＤ法によ
りリンドープアモルファスシリコンを堆積させてリンド
ープアモルファスシリコン層２６を形成し、その後、リ
ンドープアモルファスシリコン層２６を７００〜８５０
℃で熱処理する（図３（ｃ）参照）。この熱処理の結
果、リンドープアモルファスシリコン層２６は結晶化し
てリンドープポリシリコン層となる。Next, a phosphorus-doped amorphous silicon layer is formed on the interlayer insulating film 19 by depositing phosphorus-doped amorphous silicon by a CVD method.
Heat treatment at ℃ (see FIG. 3 (c)). As a result of this heat treatment, the phosphorus-doped amorphous silicon layer 26 is crystallized to become a phosphorus-doped polysilicon layer.

【００２１】次に、ポリシリコン層２６をエッチバック
して層間絶縁膜１９を露出させ、接続孔２５内にポリシ
リコンプラグ１８を形成する（図３（ｄ）参照）。Next, the polysilicon layer 26 is etched back to expose the interlayer insulating film 19, and the polysilicon plug 18 is formed in the connection hole 25 (see FIG. 3D).

【００２２】次に、スパッタ法等により、ポリシリコン
プラグ１８を含む層間絶縁膜１９上に、膜厚３０ｎｍの
Ｔｉ層及び膜厚５０ｎｍのＴｉＮ層からなる耐シリコン
拡散導電層２１を形成し、その後、窒素（Ｎ2 ）雰囲気
中でのＲＴＡ（ｒａｐｉｄｔｈｅｒｍａｌ ａｎｎｅａ
ｌｉｎｇ）処理を行う。このＮ2 −ＲＴＡ処理により、
耐シリコン拡散導電層２１を形成するＴｉ層は、ＴｉＳ
ｉ2 層からなるシリコンコンタクト層２０に変化する
（図４（ｅ）参照）。Next, a silicon-diffused conductive layer 21 made of a 30-nm-thick Ti layer and a 50-nm-thick TiN layer is formed on the interlayer insulating film 19 including the polysilicon plug 18 by sputtering or the like. RTA (rapid thermal anna) in a nitrogen (N 2 ) atmosphere
ling) processing. By this N 2 -RTA processing,
The Ti layer forming the silicon diffusion-resistant conductive layer 21 is made of TiS
It changes to a silicon contact layer 20 composed of an i 2 layer (see FIG. 4E).

【００２３】次に、ＤＣ（ｄｉｒｅｃｔ ｃｕｒｒｅｎ
ｔ）スパッタ法等により、例えば、Ｒｕからなる膜厚１
００ｎｍのキャパシタ下部電極層２２を耐シリコン拡散
導電層２１上に成膜する（図４（ｆ）参照）。キャパシ
タ下部電極層２２は、Ｒｕの他、プラチナ（Ｐｔ）、ペ
ロブスカイト構造の導電性材料であるルテニウム酸スト
ロンチウム（ＳｒＲｕＯ3 ）等がある。Next, DC (direct curren)
t) By sputtering or the like, for example, a film thickness 1 of Ru
A 00 nm capacitor lower electrode layer 22 is formed on the silicon diffusion-resistant conductive layer 21 (see FIG. 4F). The capacitor lower electrode layer 22 is made of platinum (Pt), strontium ruthenate (SrRuO 3 ), which is a conductive material having a perovskite structure, in addition to Ru.

【００２４】次に、酸素及び塩素の混合ガスを用いたプ
ラズマエッチング法により、キャパシタ下部電極層２
２、耐シリコン拡散導電層２１及びシリコンコンタクト
層２０を所望の形状に加工する（図５（ｇ）参照）。Next, the capacitor lower electrode layer 2 is formed by a plasma etching method using a mixed gas of oxygen and chlorine.
2. Process the silicon diffusion-resistant conductive layer 21 and the silicon contact layer 20 into desired shapes (see FIG. 5G).

【００２５】次に、ビス−ジピバロイルメタンバリウム
（Ｂａ（ＤＰＭ）2 ）、ビス−ジピバロイルメタンスト
ロンチウム（Ｓｒ（ＤＰＭ）2 ）、ビス−ジピバロイル
メタンチタンイソプロポキシド（Ｔｉ（ｉ−ＯＣ
3 Ｈ7 ）2 （ＤＰＭ）2 ）及び酸素ガスを原料とした熱
ＣＶＤ法により、キャパシタ下部電極層２２上に、４０
０〜４８０℃で膜厚２０ｎｍのＢＳＴ薄膜をキャパシタ
絶縁膜２３として成膜する（図５（ｈ）参照）。ＤＰＭ
とは、ｂｉｓ−ｄｉｐｉｖａｌｏｙｌｍｅｔｈａｎａｔ
ｅの略である。Next, bis-dipivaloylmethanebarium (Ba (DPM) 2 ), bis-dipivaloylmethanestrontium (Sr (DPM) 2 ), bis-dipivaloylmethanetitanium isopropoxide ( Ti (i-OC
By thermal CVD using 3 H 7 ) 2 (DPM) 2 ) and oxygen gas as raw materials, 40
A BST thin film having a thickness of 20 nm is formed as the capacitor insulating film 23 at 0 to 480 ° C. (see FIG. 5H). DPM
Is bis-dipivaloylmethanat
e.

【００２６】なお、原料としては、上記例の他、Ｂａ
（ＤＰＭ）2 、Ｓｒ（ＤＰＭ）2 を単独で或いは組み合
わせて、Ｔｉ（ｉ−ＯＣ3 Ｈ7 ）2 （ＤＰＭ）2 、Ｔｉ
Ｏ（ＤＰＭ）2 、Ｔｉ（ｉ−ＯＣ3 Ｈ7 ）2 （ＤＰＭ）
2 を単独で或いは組み合わせて、これらに酸素ガスを加
えたものでもよい。これらの原料により、ペロブスカイ
ト構造の強誘電体膜を形成し、キャパシタ絶縁膜２３と
する。As the raw material, in addition to the above examples, Ba
(DPM) 2, Sr and (DPM) 2 alone or in combination, Ti (i-OC 3 H 7) 2 (DPM) 2, Ti
O (DPM) 2 , Ti (i-OC 3 H 7 ) 2 (DPM)
2 alone or in combination, may be obtained by adding these to oxygen gas. From these materials, a ferroelectric film having a perovskite structure is formed, and is used as the capacitor insulating film 23.

【００２７】そして、キャパシタ絶縁膜２３を形成した
後、結晶化を目的として酸素を０〜５％含む不活性ガス
雰囲気下において、結晶化開始温度である６５０〜９０
０℃の高温で熱処理を行う。この熱処理として、例え
ば、４００℃で１時間の窒素処理を行った後に７５０℃
で３０ｓｅｃ（秒）のＮ2 −ＲＴＡ処理を行った。After the capacitor insulating film 23 is formed, the crystallization start temperature is set at 650 to 90 in an inert gas atmosphere containing 0 to 5% oxygen for the purpose of crystallization.
Heat treatment is performed at a high temperature of 0 ° C. As this heat treatment, for example, after performing a nitrogen treatment at 400 ° C. for 1 hour, the heat treatment is performed at 750 ° C.
In was N 2 -RTA processing of 30sec (in seconds).

【００２８】ＢＳＴ薄膜に対する高温熱処理は、ランプ
アニール（ＲＴＡ）による場合、６００〜９００℃、好
ましくは６５０〜８００℃で、１〜２４０ｓｅｃ、好ま
しくは１〜６０ｓｅｃとする。炉による場合は、５２０
〜８００℃、好ましくは５５０〜６５０℃で、１〜４８
０ｍｉｎ（分）、好ましくは１０〜１２０ｍｉｎとす
る。The high temperature heat treatment for the BST thin film is performed at a temperature of 600 to 900 ° C., preferably 650 to 800 ° C., for 1 to 240 seconds, preferably 1 to 60 seconds in the case of lamp annealing (RTA). 520 if using furnace
~ 800 ° C, preferably 550-650 ° C, 1-48
0 min (minute), preferably 10 to 120 min.

【００２９】この熱処理の後、ＤＣスパッタ法等によ
り、ＢＳＴ膜上に、Ｒｕ等からなる膜厚５０ｎｍのキャ
パシタ上部電極層２４（図１参照）を成膜し、その後、
酸素を０〜５％含む不活性ガス雰囲気下において、２５
０〜５００℃の低温で熱処理を行う。この低温熱処理と
して、例えば、３００℃で３０分の窒素処理を行った。After this heat treatment, a 50 nm thick capacitor upper electrode layer 24 (see FIG. 1) made of Ru or the like is formed on the BST film by DC sputtering or the like.
Under an inert gas atmosphere containing 0 to 5% of oxygen, 25
The heat treatment is performed at a low temperature of 0 to 500C. As this low-temperature heat treatment, for example, nitrogen treatment was performed at 300 ° C. for 30 minutes.

【００３０】以上により、高誘電率のＢＳＴを容量絶縁
膜として用いた薄膜キャパシタ１０を有する半導体装置
を製造することができる（図１参照）。As described above, a semiconductor device having a thin film capacitor 10 using BST having a high dielectric constant as a capacitance insulating film can be manufactured (see FIG. 1).

【００３１】図６は、図２〜図５に示す製造方法により
製造した薄膜キャパシタを有する半導体装置の効果を説
明する図である。図６には、印加電圧（ａｐｐｌｉｅｄ
ｖｏｌｔａｇｅ：Ｖ）に対するリーク電流密度（ｌｅ
ａｋａｇｅ ｃｕｒｒｅｎｔｄｅｎｓｉｔｙ：Ａ／ｃｍ
2 ）が、従来の結晶化熱処理のみを行った場合（○印参
照）と、この発明に係る結晶化熱処理に加えて低温熱処
理を行った場合（●印参照）とについてグラフ表示され
ている。FIG. 6 is a diagram for explaining the effect of the semiconductor device having the thin film capacitor manufactured by the manufacturing method shown in FIGS. FIG. 6 shows the applied voltage (applied
voltage: V) and the leakage current density (le
age current density: A / cm
2 ) graphically shows the case where only the conventional crystallization heat treatment was performed (see the mark ○) and the case where the low-temperature heat treatment was performed in addition to the crystallization heat treatment according to the present invention (see the mark ●).

【００３２】図６に示すように、この発明に係る製造方
法である結晶化熱処理に加えて低温熱処理を行った場合
（●印参照）、従来の結晶化熱処理のみを行った場合
（○印参照）に比べ、印加電圧の全範囲（−３〜３Ｖ）
においてリーク電流密度が低下しているのが分かり、印
加電圧が−２〜２Ｖの範囲では、約１×１０-8レベルと
なっている。この結果、ＳｉＯ2 に換算した際の膜厚が
非常に小さく、且つ、リーク特性に優れた高誘電率薄膜
キャパシタを提供することができる。As shown in FIG. 6, when the low-temperature heat treatment is performed in addition to the crystallization heat treatment (see the mark ●) in the manufacturing method according to the present invention, the conventional crystallization heat treatment alone is performed (see the mark ○). ), The entire range of applied voltage (-3 to 3 V)
It can be seen that the leakage current density is lowered in the case of, and when the applied voltage is in the range of -2 to 2 V, it is about 1 × 10 -8 level. As a result, it is possible to provide a high-dielectric-constant thin-film capacitor having a very small thickness when converted to SiO 2 and having excellent leakage characteristics.

【００３３】つまり、ＢＳＴ薄膜の結晶化を目的とした
５２０〜９００℃の高温熱処理の後に、２５０〜５００
℃の低温熱処理を行うことにより、高誘電率のＢＳＴを
容量絶縁膜として用いた薄膜キャパシタ１０のリーク電
流を低減することができる。これは、熱ＣＶＤにより成
膜したＢＳＴ膜に多く含まれていると推定されるカーボ
ン（Ｃ）や水素（Ｈ）等の脱離に、２５０〜５００℃の
低温アニールが効果的に作用するものと思われる。That is, after a high-temperature heat treatment at 520 to 900 ° C. for the purpose of crystallization of the BST thin film, 250 to 500
By performing the low-temperature heat treatment at a temperature of ° C., it is possible to reduce the leak current of the thin-film capacitor 10 using BST having a high dielectric constant as a capacitive insulating film. This is because low-temperature annealing at 250 to 500 ° C. effectively acts on desorption of carbon (C), hydrogen (H), and the like presumed to be largely contained in a BST film formed by thermal CVD. I think that the.

【００３４】このように、上記実施の形態による薄膜キ
ャパシタ１０を有する半導体装置の製造方法において
は、熱ＣＶＤで成膜されたＢＳＴ膜を、不活性ガス雰囲
気のもと温度２５０〜５００℃の範囲でＢＳＴを結晶化
させることなく熱処理する低温熱処理工程と、同様の不
活性ガス雰囲気のもと温度５２０〜９００℃の範囲でＢ
ＳＴを結晶化させるために熱処理する高温熱処理工程と
を有している。As described above, in the method of manufacturing a semiconductor device having the thin film capacitor 10 according to the above-described embodiment, the BST film formed by thermal CVD is formed in a temperature range of 250 to 500 ° C. in an inert gas atmosphere. And a low-temperature heat treatment step of heat-treating the BST without crystallization at a temperature of 520 to 900 ° C. in the same inert gas atmosphere.
A high-temperature heat treatment step of performing a heat treatment to crystallize the ST.

【００３５】なお、高温熱処理は、薄膜キャパシタ１０
の容量絶縁膜の誘電率εが５０を超えるような状態にす
るのに必要な熱処理であり、低温熱処理は、高温熱処理
の温度から少なくとも２０℃以上低い温度、或いは容量
絶縁膜の結晶化温度より１５０℃低い温度から結晶化温
度より４００℃低い温度までの範囲の熱処理である。The high-temperature heat treatment is performed by
Is a heat treatment necessary to make the dielectric constant ε of the capacitive insulating film exceed 50, and the low-temperature heat treatment is a temperature at least 20 ° C. lower than the temperature of the high-temperature heat treatment or the crystallization temperature of the capacitive insulating film. The heat treatment ranges from 150 ° C. lower to 400 ° C. lower than the crystallization temperature.

【００３６】ここで、低温熱処理（温度範囲２５０〜５
００℃）と高温熱処理（温度範囲５２０〜９００℃）の
２つの熱処理は、ＢＳＴ成膜後に行われれば良く、例え
ば、低温熱処理を、高温熱処理の前或いは後に行う、キ
ャパシタ上部電極形成の前或いは後に行う等、製造工程
において少なくとも１回は高温熱処理と低温熱処理が含
まれていれば良く、熱処理を行う時点及び回数は任意で
ある。Here, low-temperature heat treatment (temperature range 250 to 5)
The two heat treatments of (00 ° C.) and the high-temperature heat treatment (temperature range of 520 to 900 ° C.) may be performed after the BST film formation. For example, the low-temperature heat treatment is performed before or after the high-temperature heat treatment, before or after the formation of the capacitor upper electrode. At least one high-temperature heat treatment and one low-temperature heat treatment may be included in the manufacturing process, such as performed later, and the time and number of heat treatments are arbitrary.

【００３７】即ち、製造工程は、上述したＢＳＴ成膜→
高温熱処理→上部電極層形成→低温熱処理の順番の他、
例えば、ＢＳＴ成膜後、低温熱処理→高温熱処理→上部
電極層形成、高温熱処理→低温熱処理→上部電極層形
成、上部電極層形成→高温熱処理→低温熱処理等、の各
順番でも良い。That is, the manufacturing process is the same as the above-described BST film formation.
In addition to the order of high temperature heat treatment → upper electrode layer formation → low temperature heat treatment,
For example, after the BST film formation, the order of low-temperature heat treatment → high-temperature heat treatment → upper electrode layer formation, high-temperature heat treatment → low-temperature heat treatment → upper electrode layer formation, upper electrode layer formation → high-temperature heat treatment → low-temperature heat treatment may be used.

【００３８】また、ＢＳＴ成膜と成膜後の高温熱処理の
２つを組み合わせて複数回繰り返し、その後に低温熱処
理を行っても良く、更に、ＢＳＴ成膜と成膜後の高温熱
処理及び低温熱処理の３つを一つにまとめて複数回繰り
返しても良い。The BST film formation and the high temperature heat treatment after the film formation may be repeated a plurality of times in combination, followed by the low temperature heat treatment after the BST film formation and the high temperature heat treatment after the film formation. May be combined into one and repeated a plurality of times.

【００３９】また、低温熱処理を、余り酸素を含まない
酸素含有率０〜５％の不活性ガス雰囲気で行うことによ
り、酸素濃度が高い場合にＲｕ等からなるキャパシタ上
部電極層２４が酸化してしまうのを防止することができ
る。Further, by performing the low-temperature heat treatment in an inert gas atmosphere having an oxygen content of 0 to 5% containing little oxygen, the capacitor upper electrode layer 24 made of Ru or the like is oxidized when the oxygen concentration is high. Can be prevented.

【００４０】図７は、図２〜図５に示す製造方法に用い
られる半導体製造装置の概略構成図である。図７に示す
ように、半導体製造装置２７は、枚葉式の製造装置であ
り、装置中心部に設置された搬送系２８、及び搬送系２
８の周囲に配置された複数のチャンバを有している。FIG. 7 is a schematic configuration diagram of a semiconductor manufacturing apparatus used in the manufacturing method shown in FIGS. As shown in FIG. 7, the semiconductor manufacturing apparatus 27 is a single-wafer type manufacturing apparatus, and has a transport system 28 and a transport system 2 installed at the center of the apparatus.
8 has a plurality of chambers arranged around it.

【００４１】複数のチャンバは、ＢＳＴ成膜チャンバ２
９、高温熱処理用チャンバ３０、低温熱処理用チャンバ
３１、上部電極成膜用チャンバ３２、及びロードロック
チャンバ３３からなり、ロードロックチャンバ３３には
制御部３４が設置されている。The plurality of chambers are the BST film forming chamber 2
9, a high-temperature heat treatment chamber 30, a low-temperature heat treatment chamber 31, an upper electrode film formation chamber 32, and a load lock chamber 33, in which a control unit 34 is provided.

【００４２】キャリア（図示しない）に収納された処理
対象のウェハは、ロードロックチャンバ３３を介して各
チャンバ２９〜３２に搬入され、各チャンバ２９〜３２
毎の処理を経た後、ロードロックチャンバ３３を介して
装置外に搬出される。ＢＳＴ成膜チャンバ２９は、ＢＳ
Ｔ成膜を行い、高温熱処理用チャンバ３０は、ＢＳＴを
結晶化させるための高温熱処理を行う。低温熱処理用チ
ャンバ３１は、ＢＳＴをその処理単独では結晶化しない
条件で低温熱処理を行い、上部電極成膜用チャンバ３２
は、キャパシタ上部電極層２４の成膜を行う。制御部３
４は、各チャンバ２９〜３２毎の処理を含む装置全体の
動作制御を行う。The wafer to be processed, which is stored in a carrier (not shown), is carried into each of the chambers 29 to 32 via the load lock chamber 33, and is loaded into each of the chambers 29 to 32.
After each process, it is carried out of the apparatus via the load lock chamber 33. The BST film forming chamber 29 is
T film formation is performed, and the high-temperature heat treatment chamber 30 performs high-temperature heat treatment for crystallizing BST. The low-temperature heat treatment chamber 31 performs the low-temperature heat treatment under the condition that the BST is not crystallized by the treatment alone, and the upper electrode film formation chamber 32 is formed.
Performs the film formation of the capacitor upper electrode layer 24. Control unit 3
4 controls the operation of the entire apparatus including the processing for each of the chambers 29 to 32.

【００４３】処理対象のウェハに対する各チャンバ２９
〜３３毎の処理は、これら各チャンバ２９〜３３の間を
移動することにより行われるが、この際、大気に晒され
ずに移動及び処理が行われる。Each chamber 29 for a wafer to be processed
The processing for each of ~ 33 is performed by moving between these chambers 29-33, but at this time, the movement and processing are performed without being exposed to the atmosphere.

【００４４】この半導体製造装置２７による処理作業の
流れの例を説明する。半導体製造装置２７内に搬入され
た処理対象のウェハは、始めにロードロックチャンバ３
３に入った後、ＢＳＴ成膜チャンバ２９→高温熱処理用
チャンバ３０→低温熱処理用チャンバ３１→上部電極成
膜用チャンバ３２へと順次移動し、ＢＳＴ成膜後の高温
熱処理及び低温熱処理を経て、再びロードロックチャン
バ３３へ戻る。その後、キャパシタ上部電極２４の加工
が行われる。An example of a flow of a processing operation by the semiconductor manufacturing apparatus 27 will be described. The wafer to be processed carried into the semiconductor manufacturing apparatus 27 is first loaded into the load lock chamber 3.
3 and then sequentially move to the BST film forming chamber 29 → the high temperature heat treatment chamber 30 → the low temperature heat treatment chamber 31 → the upper electrode film formation chamber 32, and after the high temperature heat treatment and the low temperature heat treatment after the BST film formation, Return to the load lock chamber 33 again. Thereafter, processing of the capacitor upper electrode 24 is performed.

【００４５】また、処理対象のウェハを、ＢＳＴ成膜チ
ャンバ２９→低温熱処理用チャンバ３１→高温熱処理用
チャンバ３０→上部電極成膜用チャンバ３２へと順次移
動させ、或いは、ＢＳＴ成膜チャンバ２９→高温熱処理
用チャンバ３０→上部電極成膜用チャンバ３２→低温熱
処理用チャンバ３１へと順次移動させて、ＢＳＴ成膜後
の高温熱処理及び低温熱処理を行ってもよい。The wafer to be processed is sequentially moved from the BST film forming chamber 29 to the low temperature heat treatment chamber 31 → the high temperature heat treatment chamber 30 → the upper electrode film formation chamber 32, or alternatively, the BST film formation chamber 29 → The high-temperature heat treatment and the low-temperature heat treatment after the BST film formation may be performed by sequentially moving from the high-temperature heat treatment chamber 30 to the upper electrode film formation chamber 32 to the low-temperature heat treatment chamber 31.

【００４６】ところで、この熱処理は、キャパシタ上部
電極２４の加工後に行った方がより効果的であることか
ら、例えば、キャパシタ上部電極２４をウェハ全面に成
膜してエッチングする前に、結晶化させるための高温熱
処理、及びその処理単独では結晶化しない条件での低温
熱処理を連続して行うというプロセスが望ましい。Since this heat treatment is more effective after the processing of the capacitor upper electrode 24, for example, the capacitor upper electrode 24 is crystallized before being formed on the entire surface of the wafer and etched. For this purpose, a process of continuously performing a high-temperature heat treatment and a low-temperature heat treatment under conditions that do not cause crystallization by itself are desirable.

【００４７】キャパシタ上部電極２４の形成には、スパ
ッタだけでなくエッチングも含まれるので、キャパシタ
上部電極２４の形成後に熱処理を行う場合は、高温熱処
理と低温熱処理を別々の工程で行う必要がある。この場
合、キャパシタ上部電極２４の形成を、例えば、キャパ
シタ上部電極２４の成膜工程と加工工程とに分けるなら
ば、低温熱処理後にキャパシタ上部電極２４の加工を行
うことも可能であり、結晶化させるために行う熱処理
と、その処理単独では結晶化しない条件で行う熱処理と
を組み合わせればよい。Since the formation of the capacitor upper electrode 24 includes not only sputtering but also etching, when heat treatment is performed after the formation of the capacitor upper electrode 24, it is necessary to perform high-temperature heat treatment and low-temperature heat treatment in separate steps. In this case, if the formation of the capacitor upper electrode 24 is divided into, for example, a film forming step and a processing step of the capacitor upper electrode 24, it is possible to process the capacitor upper electrode 24 after the low-temperature heat treatment, and to crystallize. May be combined with a heat treatment performed under conditions that do not cause crystallization by itself.

【００４８】このように、この発明によれば、ＢＳＴ成
膜の後、不活性ガス雰囲気のもとで、ＢＳＴを結晶化さ
せるための高温熱処理及びＢＳＴをその処理単独では結
晶化しない条件で低温熱処理を行う。この低温熱処理を
加えることで、従来に比べリーク特性及び誘電率の劣化
を防ぐことができ、リーク電流を減らしてＤＲＡＭの保
持特性の向上を図ることができる。As described above, according to the present invention, after the BST film is formed, a high-temperature heat treatment for crystallizing the BST and a low-temperature Heat treatment is performed. By applying this low-temperature heat treatment, it is possible to prevent the leak characteristics and the dielectric constant from deteriorating as compared with the conventional case, reduce the leak current, and improve the retention characteristics of the DRAM.

【００４９】なお、上記実施の形態において、薄膜キャ
パシタ１０の強誘電体膜（容量膜）には、ペロブスカイ
ト構造の材料としてＢＳＴ系の材料が用いられている
が、これに限らず、Ｐｂ系のＡＢＯ3 型の材料を用いて
も良く、更に、ペロブスカイト構造を含むＡＢＯ3 複合
酸化物であればよい。In the above embodiment, the ferroelectric film (capacitance film) of the thin-film capacitor 10 is made of a BST-based material as a material having a perovskite structure. An ABO 3 type material may be used, and any ABO 3 composite oxide having a perovskite structure may be used.

【００５０】[0050]

【発明の効果】以上説明したように、この発明によれ
ば、ＡＢＯ3 複合酸化物からなる高誘電体膜の成膜後、
前記高誘電体膜を高温熱処理する高温熱処理工程と、前
記高温熱処理の処理温度より低い温度で低温熱処理する
低温熱処理工程とを経て、誘電体膜を上部電極及び下部
電極で挟み込んだ容量素子が製造され、この際、前記高
誘電体膜の成膜と前記高温熱処理、或いは前記高誘電体
膜の成膜と前記高温熱処理と前記低温熱処理は、それぞ
れ組み合わされて複数回繰り返されるので、不純物の離
脱に対応した低温による熱処理を行って、リーク特性及
び誘電率の劣化を防ぐことができる。As described above, according to the present invention, after forming a high dielectric film made of ABO 3 composite oxide,
Through a high-temperature heat treatment step of performing high-temperature heat treatment on the high-dielectric film and a low-temperature heat treatment step of performing low-temperature heat treatment at a lower temperature than the processing temperature of the high-temperature heat treatment, a capacitive element in which the dielectric film is sandwiched between the upper electrode and the lower electrode is manufactured. At this time, the high
The formation of a dielectric film and the high-temperature heat treatment or the high-dielectric
The film formation, the high-temperature heat treatment, and the low-temperature heat treatment
Are combined repeated several times Runode, heat treatment is performed at a low temperature corresponding to the separation of impurities, it is possible to prevent the deterioration of the leak characteristic and dielectric constant.

【００５１】[0051]

【図面の簡単な説明】[Brief description of the drawings]

【図１】この発明の実施の形態に係る高誘電率薄膜キャ
パシタを有する半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device having a high dielectric constant thin film capacitor according to an embodiment of the present invention.

【図２】図１の薄膜キャパシタを有する半導体装置の製
造工程を示す断面図（その１）である。FIG. 2 is a cross-sectional view (No. 1) showing a step of manufacturing the semiconductor device having the thin film capacitor of FIG.

【図３】図１の薄膜キャパシタを有する半導体装置の製
造工程を示す断面図（その２）である。FIG. 3 is a sectional view (No. 2) showing a step of manufacturing the semiconductor device having the thin film capacitor of FIG.

【図４】図１の薄膜キャパシタを有する半導体装置の製
造工程を示す断面図（その３）である。FIG. 4 is a sectional view (No. 3) showing a step of manufacturing the semiconductor device having the thin film capacitor of FIG. 1;

【図５】図１の薄膜キャパシタを有する半導体装置の製
造工程を示す断面図（その４）である。FIG. 5 is a sectional view (No. 4) showing a step of manufacturing the semiconductor device having the thin film capacitor of FIG. 1;

【図６】図２〜図５に示す製造方法により製造した薄膜
キャパシタを有する半導体装置の効果を説明する図であ
る。FIG. 6 is a diagram illustrating the effect of a semiconductor device having a thin film capacitor manufactured by the manufacturing method shown in FIGS. 2 to 5;

【図７】図２〜図５に示す製造方法に用いられる半導体
製造装置の概略構成図である。FIG. 7 is a schematic configuration diagram of a semiconductor manufacturing apparatus used in the manufacturing method shown in FIGS. 2 to 5;

【符号の説明】[Explanation of symbols]

１０ 薄膜キャパシタ １１ ＭＯＳＦＥＴ １２ メモリセル １３ ｐ型シリコン基板 １４ 素子分離絶縁膜 １５ ゲート酸化膜 １６ ゲート電極 １７ ｎ型拡散層 １８ ポリシリコンプラグ １９ 層間絶縁膜 ２０ シリコンコンタクト層 ２１ 耐シリコン拡散導電層 ２２ キャパシタ下部電極 ２３ キャパシタ絶縁膜 ２４ キャパシタ上部電極 ２５ 接続孔 ２６ リンドープアモルファスシリコン層 ２７ 半導体製造装置 ２８ 搬送系 ２９ ＢＳＴ成膜チャンバ ３０ 高温熱処理用チャンバ ３１ 低温熱処理用チャンバ ３２ 上部電極成膜用チャンバ ３３ ロードロックチャンバ ３４ 制御部 REFERENCE SIGNS LIST 10 thin film capacitor 11 MOSFET 12 memory cell 13 p-type silicon substrate 14 element isolation insulating film 15 gate oxide film 16 gate electrode 17 n-type diffusion layer 18 polysilicon plug 19 interlayer insulating film 20 silicon contact layer 21 silicon-resistant diffusion conductive layer 22 capacitor Lower electrode 23 Capacitor insulating film 24 Capacitor upper electrode 25 Connection hole 26 Phosphorus-doped amorphous silicon layer 27 Semiconductor manufacturing equipment 28 Transport system 29 BST film forming chamber 30 High temperature heat treatment chamber 31 Low temperature heat treatment chamber 32 Upper electrode film formation chamber 33 Load Lock chamber 34 control unit

フロントページの続き (56)参考文献 特開 平11−297964（ＪＰ，Ａ) 特開 平11−177048（ＪＰ，Ａ) 特開 平11−54721（ＪＰ，Ａ) 特開2000−332209（ＪＰ，Ａ) 特開2000−349254（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/8242 H01L 27/108 Continuation of front page (56) References JP-A-11-297964 (JP, A) JP-A-11-177048 (JP, A) JP-A-11-54721 (JP, A) JP-A-2000-332209 (JP, A) A) JP-A-2000-349254 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/8242 H01L 27/108

Claims (8)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】誘電体膜を上部電極及び下部電極で挟み込
んだ容量素子の製造方法において、 ＡＢＯ3 複合酸化物からなる高誘電体膜の成膜後、前記
高誘電体膜を高温熱処理する高温熱処理工程と、前記高
温熱処理の処理温度より低い温度で低温熱処理する低温
熱処理工程とを有し、 前記高誘電体膜の成膜と前記高温熱処理、或いは前記高
誘電体膜の成膜と前記高温熱処理と前記低温熱処理は、
それぞれ組み合わされて複数回繰り返され ることを特徴
とする容量素子の製造方法。1. A method of manufacturing a capacitor in which a dielectric film is sandwiched between an upper electrode and a lower electrode, comprising: forming a high dielectric film made of an ABO 3 composite oxide; a heat treatment step, the have a low-temperature heat treatment step of low-temperature heat treatment at a treatment temperature lower than the temperature of the high temperature heat treatment, the high deposition and the high temperature heat treatment of the dielectric film, or the high
The formation of the dielectric film and the high-temperature heat treatment and the low-temperature heat treatment,
Each combined to the manufacturing method of the capacitor, characterized in Rukoto repeated multiple times. 【請求項２】前記高温熱処理は、前記高誘電体膜を結晶
化する温度で行われ、前記低温熱処理は、その処理単独
では結晶化しない温度で行われることを特徴とする請求
項１に記載の容量素子の製造方法。2. The method according to claim 1, wherein the high-temperature heat treatment is performed at a temperature at which the high-dielectric film is crystallized, and the low-temperature heat treatment is performed at a temperature at which the processing alone does not crystallize. Method for manufacturing a capacitive element. 【請求項３】前記高温熱処理或いは前記低温熱処理が行
われた後に、前記上部電極が形成されることを特徴とす
る請求項１または２に記載の容量素子の製造方法。After wherein said high-temperature heat treatment or said low-temperature heat treatment is performed, the manufacturing method of the capacitor according to claim 1 or 2, wherein the upper electrode is formed. 【請求項４】前記上部電極が形成された後に、前記低温
熱処理が行われることを特徴とする請求項１または２に
記載の容量素子の製造方法。After wherein said upper electrode is formed, the manufacturing method of the capacitor according to claim 1 or 2, wherein said low-temperature heat treatment is performed. 【請求項５】前記低温熱処理を、酸素含有率０〜５％の
不活性ガス雰囲気で行うことを特徴とする請求項１から
４のいずれかに記載の容量素子の製造方法。5. The method according to claim 1, wherein the low-temperature heat treatment is performed in an inert gas atmosphere having an oxygen content of 0 to 5%.
5. The method for manufacturing a capacitive element according to any one of 4 . 【請求項６】前記高温熱処理は、５２０〜９００℃の温
度範囲で行われ、前記低温熱処理は、２５０〜５００℃
の温度範囲で行われることを特徴とする請求項１から５
のいずれかに記載の容量素子の製造方法。6. The high-temperature heat treatment is performed in a temperature range of 520 to 900 ° C., and the low-temperature heat treatment is performed in a temperature range of 250 to 500 ° C.
5 to be carried out in the temperature range of the preceding claims, characterized
A method for manufacturing a capacitive element according to any one of the above. 【請求項７】前記ＡＢＯ3 複合酸化物は、ペロブスカイ
ト構造を有することを特徴とする請求項１から６のいず
れかに記載の容量素子の製造方法。Wherein said ABO 3 complex oxide, method for producing a capacitor according to any of claims 1 to 6, characterized in that it has a perovskite structure. 【請求項８】前記ペロブスカイト構造を有する前記ＡＢ
Ｏ3 複合酸化物は、チタン酸バリウムストロンチウム
（（Ｂａ，Ｓｒ）ＴｉＯ3 ）であることを特徴とする請
求項７に記載の容量素子の製造方法。8. The AB having the perovskite structure
O 3 composite oxide, method for producing a capacitor element according to claim 7, characterized in that the barium strontium titanate ((Ba, Sr) TiO 3 ).
JP35689499A 1999-12-16 1999-12-16 Manufacturing method of capacitive element Expired - Fee Related JP3317295B2 (en)

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US09/736,562 US20010004533A1 (en) 1999-12-16 2000-12-13 Process for fabricating capacitor having dielectric layer with perovskite structure and apparatus for fabricating the same
KR1020000077149A KR20010062498A (en) 1999-12-16 2000-12-15 Process for fabricating capacitor having dielectric layer with perovskite structure and apparatus for fabricating the same
US10/135,620 US6602722B2 (en) 1999-12-16 2002-04-30 Process for fabricating capacitor having dielectric layer with pervskite structure and apparatus for fabricating the same

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US7428137B2 (en) * 2004-12-03 2008-09-23 Dowgiallo Jr Edward J High performance capacitor with high dielectric constant material
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US5716875A (en) 1996-03-01 1998-02-10 Motorola, Inc. Method for making a ferroelectric device
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KR20010062498A (en) 2001-07-07

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