JP3298448B2 - Voltage controlled oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator, and more particularly, to a voltage controlled oscillator which is suitable for use in a PLL (Phase Locked Loop) or the like, and suitable for a semiconductor integrated circuit. A voltage-controlled oscillator having a wide oscillation frequency band.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing an example of a circuit configuration of a conventional voltage controlled oscillator (hereinafter, referred to as "VCO").
Referring to FIG. 2, this VCO is formed of a semiconductor integrated circuit, and includes a control voltage control unit 1 for generating a bias voltage with respect to an input voltage, and a ring oscillator unit 2. The ring oscillator unit 2 includes an odd-numbered inverter 21
To 25 and transfer gates 26 to 30. The details of the circuit configuration of the control voltage control unit 1 are omitted.

Each of the inverters 21 to 25 and each of the transfer gates 26 to 30 are constituted by CMOS (complementary MOS), and the inverter 21 is composed of a PMOS transistor 21a and an NMOS transistor 21b. The drain electrodes of these transistors are connected to a node 21n. Connected by Similarly, the inverter 22 includes a PMOS transistor 22a and an NMOS transistor 22b, the inverter 23 includes a PMOS transistor 23a and an NMOS transistor 23b, and the inverter 24 includes
The inverter 25 includes a PMOS transistor 25a and an NMOS transistor 25b. The drain electrodes of the transistors constituting each CMOS inverter are connected to each other.
Node 22n, Node 23n, Node 24n, Node 2
5n.

Each node 21n, 22n, 23n, 24
n and 25n are transfer gates 2 of the next stage, respectively.
6, 27, 28, 29, 30. The transfer gates 26, 27, 28, 29, 30
6n, 27n, 28n, 29n, and 30n are connected to the input terminals of the next-stage inverters 22, 23, 24, 25, and 21, respectively.

The node 30n is connected to the PMO of the inverter 21.
It is connected to the gate electrodes of the S transistor 21a and the NMOS transistor 21b and is output to the outside.

The PMOS transistors 21c to 25c are inserted between the source electrodes of the PMOS transistors 21a to 25a constituting the inverters 21 to 25 and the power supply voltage VDD, respectively. Is a PMOS transistor 21
a to 25a are controlled. A voltage is applied from the control voltage controller 1 to the gate electrodes of the PMOS transistors 21c to 25c.

On the other hand, between the source electrodes of the NMOS transistors 21b to 25b constituting the inverters 21 to 25 and the GND, respectively, the NMOS transistors 21d to 21d are connected.
25d is inserted, and the NMOS transistors 21d to 25d are inserted.
d controls the current flowing through the NMOS transistors 21b to 25b. The input voltage Vin is applied to the gate electrodes of the NMOS transistors 21d to 25d via the control voltage control unit 1.

The ring oscillator 2 outputs an oscillation frequency based on an input voltage Vin from an output Out.

In the ring oscillator 2, each of the inverters 22 to 25 is connected to a transfer gate 2 located at a preceding stage.
Input the voltages of the output nodes 26n-29n of 6-29,
Inverter 21 receives the voltage of output node 30n of transfer gate 30. And each inverter 21
25 are transfer gates 30, 26 to 29 in the preceding stage.
And outputs an inverted voltage of the output voltage. Thereby, the voltage of the node 30n oscillates.

The output node 21n of the inverter 21
Is delayed and propagated to the inverter 22. The delay time here is determined by the transistors 21a and 21b and the PMOS transistors 21c and N
Current flowing through MOS transistor 21d, inverter 2
2 and the delay time of the transfer gate 26. The same applies to the inverters 22 to 25, and the input voltage and the delay time determine the oscillation frequency band.

[0011]

However, the above-mentioned conventional VCO has the following problems.

Generally, when used for a PLL or the like, VC
O oscillation frequency is required to have a wide band. In the conventional VCO, the oscillation frequency is determined for the input voltage Vin, and a necessary frequency band is obtained by adjusting the input voltage.

However, there is a limit in the oscillation frequency band only by controlling the input voltage, and therefore, the VCO is used in a specific frequency band. Then, for the band that could not be controlled by the input voltage, it was necessary to change the circuit configuration in the VCO.

As described above, the conventional VCO operates in a frequency band that can be controlled by the input voltage, and as a result, has a problem that the oscillation frequency band is narrowed and it is difficult to widen the band. ing.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a VCO capable of expanding an output oscillation frequency band.

[0016]

In order to achieve the above object, a voltage controlled oscillator according to the present invention has a plurality of transfer gates having different delay times in a ring oscillator circuit,
By switching these by switching, a ring oscillator circuit is provided which enables a wide adjustment of the delay time of the ring oscillator circuit.

Further, the present invention preferably comprises a control voltage control circuit for generating a bias voltage with respect to an input voltage, an odd number of stages of inverters, and a transfer gate for adjusting a delay time between these inverters. In a voltage controlled oscillator including a ring oscillator circuit and outputting an oscillation frequency according to the input voltage, the transfer gate inserted into the ring oscillator circuit includes a plurality of transfer gates having different delay times arranged in parallel.
And it is configured by, Oh one transfer gate of the different transfer gates of the plurality of delay time
Means for turning on the other transfer gates and turning off the other transfer gates so as to broadly adjust the delay time and broaden the oscillation frequency band to be output.

[0018]

Embodiments of the present invention will be described below. In a preferred embodiment of the voltage controlled oscillator of the present invention, the output terminal of the inverter of the ring oscillator and the input terminal of the next-stage inverter, in which the last stage of the cascade-connected odd-numbered stage inverters are fed back to the first stage, are provided. As a transfer gate for delay time adjustment inserted therebetween, a plurality of transfer gates having different delay times connected in parallel with each other are provided, and a plurality of transfer gates connected in parallel are switched on / off by a switching signal and switched, The variable range of the delay time in the ring oscillator circuit is expanded so as to widen the range of the delay time in which the output oscillation frequency band is widened. According to the embodiment of the present invention, the frequency band can be greatly expanded as compared with the conventional voltage controlled oscillator obtained by the fluctuation of the input voltage Vin.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing a circuit configuration of a VCO according to one embodiment of the present invention. With reference to FIG.
The CO is configured by a semiconductor integrated circuit, and includes a control voltage control unit 3 that generates a bias voltage with respect to an input voltage, and a ring oscillator unit 4.

In this embodiment, the ring oscillator 4
Means that the oscillation frequency is changed to the output terminal Ou by the input voltage Vin.
Output from t. The ring oscillator 4 includes odd-numbered inverters 41 to 45 and transfer gates 46 to 50
have. Each of the inverters 41 to 45 and each of the transfer gates 46 to 50 are formed of CMOS, and the inverter 41 includes a PMOS transistor 41a and an NMOS transistor 21b. The drain electrodes of these transistors are connected to each other at a node 41n. Similarly, the inverter 42 includes a PMOS transistor 42a and an NMO
The inverter 43 is composed of an S transistor 42b.
OS transistor 43a and NMOS 43 transistor b
And the inverter 44 includes a PMOS transistor 4
4a and an NMOS transistor 44b. The inverter 45 includes a PMOS transistor 45a and an NMOS transistor 45b. The drain electrodes of the transistors constituting each inverter are connected to a node 42n, respectively.
Nodes 43n, 44n, and 45n are connected.

The transfer gate 46 is connected to the inverter 4
1 output node 41n and inverter 42 input node 4
6n two transfer gates 4 connected in parallel
6a, 46b and the signals sw1, s
On / off control is performed by w2. That is, a PMOS transistor forming the transfer gate 46a,
The gate electrode of the NMOS transistor is connected to the signal sw
2, the gate electrodes of the PMOS transistor and the NMOS transistor that constitute the transfer gate 46b are connected to the signals sw1 and sw2, respectively.

Similarly, the transfer gate 47 includes transfer gates 47a and 47b, and the transfer gate 48 includes transfer gates 48a and 48b.
The transfer gate 49 includes transfer gates 49a and 49b, and the transfer gate 50 includes transfer gates 50a and 50b, and is turned on and off by signals sw1 and sw2.

The transfer gates 46a to 50a and the transfer gates 46b to 50b have different delay times due to the difference in transistor size.

Each node 41n, 42n, 43n, 44
n and 45n are transfer gates 46 and 47 in the next stage,
The transfer gates 45 to 49 are connected to the next inverters 42, 43, 44, and 45 by nodes 46n, 47n, 48n, and 49n.
Connected to.

The node 50n is connected to the PMO of the inverter 41.
It is connected to the gate electrodes of the S transistor 41a and the NMOS transistor 41b and is output to the outside.

The PMOS transistors 41c to 45c are inserted between the source electrodes of the PMOS transistors 41a to 45a and the power supply voltage VDD, and a voltage is input from the control voltage control circuit 3 to the gate electrodes of the PMOS transistors 41c to 25c. .

On the other hand, NMOS transistors 41b to 45
The NMOS transistors 41d to 45d are connected between the source electrode side of “b” and GND, and the NMOS transistors 41d to 45d are connected.
The input voltage Vin is applied to the gate electrodes d to 45d.

The operation of the VCO of this embodiment shown in FIG. 1 will be described.

The ring oscillator 4 outputs an oscillation frequency based on the input voltage Vin from an output Out. Also,
The voltage of output node 41 n of inverter 41 is delayed and propagated to inverter 42. The delay time here is the current flowing through the inverters 41a, 41b, 41c, 41d,
It depends on the gate capacity of the inverter 42 and the delay time of the transfer gate 46. Inverters 42 to 45
Similarly, the input voltage and the delay time determine the oscillation frequency band.

In the embodiment of the present invention, the delay time in the ring oscillator for determining the oscillation frequency will be described.

In the ring oscillator 4, the transfer gates 46 to 50 have two transfer gates having different delay times, and are switched by switching the signals sw1 and sw2. The power supply voltage VDD is applied to the signal line sw1,
When the ground voltage GND is applied to sw2, the transfer gate 46a is turned on, the transfer gate 46b is turned off, and the voltage of the node 41n propagates through the transfer gate 46a. Conversely, the ground voltage GN is applied to the signal line sw1.
When the power supply voltage VDD is applied to D and sw2, the transfer gate 46a is turned off and the transfer gate 46b
Is turned on, and the voltage of node 41n propagates through transfer gate 46b.

The inverters 42 to 45 receive the voltages from the output nodes 46n to 49n of the transfer gates 46 to 49 selected by the switching at the preceding stage, and the inverter 41 outputs the voltage from the output node 50 of the transfer gate 50.
Input the voltage from n.

The inverters 41 to 45 output inverted voltages of the output voltages of the transfer gates 50 and 47 to 49 in the preceding stage. Thus, the voltage of the node 50n oscillates.

Here, the transfer gate 46a and the transfer gate 46b constituting the transfer gate 46
Are assumed to be t46a and t46b, respectively.

For these delay times, t46a> t
At the time of 46b, when the power supply voltage VDD is applied to the signal sw1 and the ground voltage GND is applied to the signal sw2, the delay time of the ring oscillator increases, and the ring oscillator oscillates in a low band.

Conversely, when the ground voltage GND is applied to the signal sw1 and the power supply voltage VDD is applied to the signal sw2, the oscillation occurs in a high band.

FIG. 3 is a diagram for explaining the operation and effect of this embodiment in comparison with the conventional example shown in FIG. 2 as a comparative example. As shown in FIG. 3, the oscillation frequency range of the conventional example depends on the input voltage, and in this embodiment, an oscillation frequency in a wider band can be obtained by adjusting the delay time in the ring oscillator.

[0039]

As described above, according to the present invention, V
A plurality of transfer gates for delay time adjustment are provided in the CO ring oscillator circuit, and these are switched by switching, so that the delay time of the ring oscillator is adjusted. This has the effect of widening the frequency band. As a result, according to the present invention, the frequency band can be greatly expanded as compared with the conventional system obtained by the fluctuation of the input voltage.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a VCO according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a circuit configuration of a conventional VCO.

FIG. 3 is a graph showing a relationship between an oscillation frequency and an input voltage.

[Explanation of symbols]

 Reference Signs List 3 control voltage control circuit 4 ring oscillator circuit 41-45 inverter 41a-45a PMOS 41b-45b NMOS 41c-45c PMOS 41d-45d NMOS 46-50 transfer gate 46a-50a transfer gate 46b-50b transfer gate CTP control voltage CTN control voltage (Input voltage) Out Output oscillation frequency Vin Input voltage sw1, sw2 Switching control voltage

Claims (3)

(57) [Claims] 1. A ring oscillator circuit comprising: a control voltage control circuit for generating a bias voltage with respect to an input voltage; an odd number of stages of inverters; and a transfer gate for adjusting a delay time between the inverters. In a voltage controlled oscillator that outputs an oscillation frequency according to an input voltage, a plurality of inverters of the ring oscillator circuit are connected to each other.
Juxtaposed the transfer gates with different time delays to have one of the transfer gates of the different transfer gates of the plurality of delay times are arranged in parallel in between the inverter
Switch on, and other transfer gates off.
A voltage-controlled oscillator, characterized in that the voltage-controlled oscillator comprises means for operating the voltage controlled oscillator. 2. A delay time adjustment inserted between an output terminal of an inverter forming a ring oscillator and an input terminal of a next-stage inverter, in which a final stage of an odd-number of cascade-connected inverters is fed back to a first stage. A plurality of transfer gates connected in parallel with different delay times from each other, and performing switching control by a switching signal to turn on one of the plurality of transfer gates connected in parallel. ,other
A voltage-controlled oscillator configured to turn off a transfer gate . 3. The transfer gate according to claim 2, wherein said plurality of transfer gates comprise at least two CMOS transfer gates having relatively small and large delay times.
A voltage controlled oscillator as described.