JP3296168B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3296168B2 JP3296168B2 JP30314695A JP30314695A JP3296168B2 JP 3296168 B2 JP3296168 B2 JP 3296168B2 JP 30314695 A JP30314695 A JP 30314695A JP 30314695 A JP30314695 A JP 30314695A JP 3296168 B2 JP3296168 B2 JP 3296168B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- semiconductor element
- substrate
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体パッケージに
関し、特にボール・グリッド・アレイ（ＢａｌｌＧｒｉ
ｄ Ａｒｒａｙ。以下、ＢＧＡと記す）と称されるパッ
ケージに関する。The present invention relates to a semiconductor package, and more particularly, to a ball grid array (BallGrid array).
d Array. Hereinafter, referred to as a BGA).
【０００２】[0002]
【従来の技術】図４は従来のＢＧＡの断面図で、例えば
日経ＢＰ社刊「日経エレクトロニクス」１９９４年２月
１４日（ｎｏ．６０１）号の６１ページに同様のものが
記載されている。配線基板１上面中央部には、半導体素
子２が搭載され接着剤で配線基板上のダイパツド１１に
固定されている。配線基板下面には、半田ボールで成る
複数の球形電極３が設けられている。配線基板の両面に
は、金属膜でできた配線群があり、上面の配線４と下面
の配線５とは配線基板端部近傍に設けられた導電性の貫
通孔（バイアホール）６ａにより接続されている。配線
群は絶縁性皮膜であるソルダーレジスト１０で被われて
いる。半導体素子の能動面上の電極パッドは、配線基板
上面の配線４の内端と金属細線７で接続されている。前
記球形電極３は前記配線基板下面の配線５の内端と接続
している。また、半導体素子は外力から保護されるよう
絶縁性の樹脂８で被われている。2. Description of the Related Art FIG. 4 is a cross-sectional view of a conventional BGA, which is described, for example, on page 61 of "Nikkei Electronics" published by Nikkei BP, February 14, 1994 (no. 601). The semiconductor element 2 is mounted on the center of the upper surface of the wiring board 1 and is fixed to the die pad 11 on the wiring board with an adhesive. A plurality of spherical electrodes 3 made of solder balls are provided on the lower surface of the wiring board. On both sides of the wiring board, there are wiring groups made of a metal film, and the wiring 4 on the upper surface and the wiring 5 on the lower surface are connected by a conductive through hole (via hole) 6a provided near the end of the wiring substrate. ing. The wiring group is covered with a solder resist 10 which is an insulating film. The electrode pad on the active surface of the semiconductor element is connected to the inner end of the wiring 4 on the upper surface of the wiring board by a thin metal wire 7. The spherical electrode 3 is connected to the inner end of the wiring 5 on the lower surface of the wiring board. The semiconductor element is covered with an insulating resin 8 so as to be protected from external force.
【０００３】図５は従来のキヤビテイーダウンタイプの
ＢＧＡの断面図である。配線基板１は多層基板であり一
部は内層まで削除されデバイスホールを形成している。
デバイスホールの底部には内層の一部であるダイパッド
１１があり、半導体素子２が接着剤でこのダイパツド１
１に固定されている。配線基板下面には、半田ボールで
成る複数の球形電極３が設けられている。配線基板１は
多層基板であり、上下の外層及び内層二層には金属膜で
できた配線群があり、内層の配線１３と下面の円形電極
１５とは配線基板に設けられた導電性の貫通孔（バイア
ホール）６ａにより接続されている。外層の配線群は絶
縁性皮膜であるソルダーレジスト１０で被われている。
半導体素子の能動面上の電極パッドは、配線基板内層の
配線１３がデバイスホール内に露出した内端と金属細線
７で接続されている。前記球形電極３は前記配線基板下
面の円形電極１５と接続している。また、半導体素子は
外力から保護されるよう絶縁性の樹脂８で被われてい
る。FIG. 5 is a sectional view of a conventional cavity-down type BGA. The wiring board 1 is a multi-layer board, and a part of the wiring board 1 is deleted to an inner layer to form a device hole.
A die pad 11 which is a part of an inner layer is provided at the bottom of the device hole.
Fixed to 1. A plurality of spherical electrodes 3 made of solder balls are provided on the lower surface of the wiring board. The wiring board 1 is a multi-layer board, and has a wiring group made of a metal film on the upper and lower outer layers and the inner layer. They are connected by a hole (via hole) 6a. The outer wiring group is covered with a solder resist 10 which is an insulating film.
The electrode pad on the active surface of the semiconductor element is connected to the inner end where the wiring 13 in the wiring board inner layer is exposed in the device hole by the thin metal wire 7. The spherical electrode 3 is connected to a circular electrode 15 on the lower surface of the wiring board. The semiconductor element is covered with an insulating resin 8 so as to be protected from external force.
【０００４】[0004]
【発明が解決しようとする課題】図４、図５のどちらの
ＢＧＡも、実使用時には前記ＢＧＡ配線基板とは別のよ
り大きな配線基板（以下、マザーボードと記す）に設け
た金属電極に半田ペーストをスクリーン印刷等で添着
し、その上にＢＧＡを前記球形電極の先端が前記半田ペ
ースト層内に入り込むように置いたのち加熱して接続す
る。ＢＧＡの球形電極として半田ボールが用いられる場
合が多いが、このような場合は半田ペーストの代わりに
フラックスだけを用いることもできる。In each of the BGAs shown in FIGS. 4 and 5, a solder paste is applied to a metal electrode provided on a larger wiring board (hereinafter referred to as a motherboard) different from the BGA wiring board in actual use. Is attached by screen printing or the like, and a BGA is placed thereon such that the tip of the spherical electrode enters the solder paste layer, and then heated and connected. In many cases, solder balls are used as the spherical electrodes of the BGA. In such a case, only flux can be used instead of the solder paste.
【０００５】このようにＢＧＡをマザーボードに実装し
た状態ではＢＧＡの球形電極はマザーボードに隠れてし
まっているし、ＢＧＡ基板上面の配線もソルダーレジス
ト１０、絶縁性樹脂８で被われているため、例えばオシ
ロスコープのプローブを当てて電源電圧を点検したり、
電気信号の波形を見て回路動作の良否を点検することは
不可能である。また、点検用の電極をマザーボード上に
設けることはコストアップになるし、小型化を求められ
る携帯型電子機器においては事実上不可能な事が多い。In the state where the BGA is mounted on the motherboard, the spherical electrodes of the BGA are hidden by the motherboard, and the wiring on the upper surface of the BGA substrate is covered with the solder resist 10 and the insulating resin 8. Check the power supply voltage by applying an oscilloscope probe,
It is impossible to check the quality of the circuit operation by looking at the waveform of the electric signal. In addition, providing an inspection electrode on a motherboard increases costs, and is often impossible in portable electronic devices that require miniaturization.
【０００６】本発明の目的はかかる課題を解決し、ＢＧ
Ａをマザーボードに実装した状態でもＢＧＡ端子の電気
信号の波形をオシロスコープ等で見て回路動作の良否を
点検することが可能なＢＧＡを提供することにある。An object of the present invention is to solve such a problem and to provide a BG
It is an object of the present invention to provide a BGA capable of checking the circuit operation by checking the waveform of an electric signal at a BGA terminal with an oscilloscope or the like even when A is mounted on a motherboard.
【０００７】[0007]
【課題を解決するための手段】本発明による請求項１記
載の半導体装置は、少なくとも第１面及び第１面と反対
の第２面に導体が設けられ該導体の少なくとも一部が絶
縁性皮膜で被われ、複数のバイアホールを備えた配線基
板と、該配線基板の一面に搭載された半導体素子と、該
半導体素子と前記導体の少なくとも一部を被う絶縁性樹
脂と、前記配線基板の第１面に設けられた球形端子群と
を含んで成り、前記半導体素子の電極群と前記球形端子
群とを電気的に接続する電気径路群が形成された半導体
装置において、前記半導体素子が該配線基板の第２面に
搭載され、前記第２面に設けられ前記電気径路と同電位
の前記導体の一部が前記絶縁性皮膜あるいは前記絶縁性
樹脂から露出し、露出された前記導体の一部が、前記バ
イアホールの直上に位置し、該バイアホールと同心円を
なす同心円状電極として形成されたことを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device, wherein a conductor is provided on at least a first surface and a second surface opposite to the first surface, and at least a part of the conductor is an insulating film. covered with a wiring board having a plurality of via holes, a semiconductor element mounted on one surface of the wiring substrate, and an insulating resin which covers at least a part of the with the semiconductor element conductors, the wiring board comprises a spherical terminal group provided on the first surface, the semiconductor device electrical path group is formed for electrically connecting the electrode group and said spherical terminal group of the semiconductor element, the semiconductor element is the On the second surface of the wiring board
Is mounted, the second provided face the portion of the conductor of the electrical path and the same potential is exposed from the insulating film or the insulating resin, a portion of the exposed the conductor, the bus
Located directly above the via hole, and concentric with the via hole
It is characterized in that it is formed as a concentric electrode .
【０００８】[0008]
【０００９】[0009]
【００１０】[0010]
【作用】本発明による半導体装置にあっては、ＢＧＡの
配線基板の上面（ＢＧＡ端子と反対の面）にＢＧＡ端子
と電気的に接続した電気径路の一部あるいは電気径路と
同電位の導体が絶縁物に被われることなく露出されてい
るので、ＢＧＡをマザーボードに実装した状態でもオシ
ロスコープのプローブを当てて電源電圧を点検したり、
電気信号の波形を見て回路動作の良否を点検することが
可能である。In the semiconductor device according to the present invention, a part of an electric path electrically connected to the BGA terminal or a conductor having the same potential as the electric path is formed on the upper surface (the surface opposite to the BGA terminal) of the BGA wiring board. Because it is exposed without being covered with insulators, you can check the power supply voltage by applying an oscilloscope probe even when the BGA is mounted on the motherboard.
The quality of the circuit operation can be checked by looking at the waveform of the electric signal.
【００１１】[0011]
【発明の実施の形態】図１、図２は本発明の第１の実施
例で、図１は半導体装置を上から見た平面図である。図
１において、１は配線基板、４は配線基板上面の配線
（導体）、８は封止樹脂、１０はソルダーレジストであ
る。ただし、配線基板上面の配線４、ソルダーレジスト
１０は全体の四分の一だけ描いてある。他の四分の三は
パッケージ中心を中心として９０度ずつ回転した図形で
ある。また、封止樹脂で隠れた部分は描いてない。図２
は半導体装置を図１のＡ−Ａで切断した断面図である。
１は配線基板、２は半導体素子、３は球形電極、４は配
線基板上面の配線、５は配線基板下面の配線（導体）、
６ａはバイアホール、７は金属細線、８は封止樹脂、１
０はソルダーレジスト、１１はダイパッドである。本パ
ッケージでは、金属細線７、配線基板上面の配線４、バ
イアホール６ａ、配線基板下面の配線５が半導体素子か
ら球形電極に至る電気径路を形成している。ＢＧＡの配
線基板１の上面にはこの電気径路の一部である配線４の
一部がソルダーレジスト１０、封止樹脂などの絶縁物に
被われることなく露出されている。1 and 2 show a first embodiment of the present invention. FIG. 1 is a plan view of a semiconductor device as viewed from above. In FIG. 1, 1 is a wiring board, 4 is a wiring (conductor) on the upper surface of the wiring board, 8 is a sealing resin, and 10 is a solder resist. However, the wiring 4 and the solder resist 10 on the upper surface of the wiring board are drawn only for a quarter of the whole. The other three quarters are figures rotated by 90 degrees about the package center. Also, the portion hidden by the sealing resin is not drawn. FIG.
2 is a cross-sectional view of the semiconductor device taken along the line AA in FIG.
1 is a wiring board, 2 is a semiconductor element, 3 is a spherical electrode, 4 is wiring on the upper surface of the wiring substrate, 5 is wiring (conductor) on the lower surface of the wiring substrate,
6a is a via hole, 7 is a thin metal wire, 8 is a sealing resin, 1
0 is a solder resist and 11 is a die pad. In this package, the thin metal wire 7, the wiring 4 on the upper surface of the wiring board, the via hole 6a, and the wiring 5 on the lower surface of the wiring board form an electric path from the semiconductor element to the spherical electrode. On the upper surface of the BGA wiring board 1, a part of the wiring 4 which is a part of the electric path is exposed without being covered with an insulator such as a solder resist 10 or a sealing resin.
【００１２】本実施例の半導体装置は以下のように製造
した。The semiconductor device of this embodiment was manufactured as follows.
【００１３】（１）プリント配線基板を用意する。この
基板上面中央部には四角形のダイパッドがあり、ダイパ
ッドの周囲には金属配線（導体）が設けられ、ダイパッ
ド近傍から基板端部に設けられたバイアホールに至って
いる。基板下面にはマトリックス状に円形の電極（導
体）が設けられ、前記バイアホールから前記円形電極ま
で金属配線が走っている。バイアホールの内壁には銅メ
ッキが施され、バイアホールの両端（基板の上面及び下
面）には金属の同心円状の電極（導体）が設けられ、基
板上面及び下面の金属配線と内壁銅メッキとの接続を確
かにしている。こうして基板上面のダイパッド近傍から
基板下面の円形電極に至る電気径路を形成している。ソ
ルダレジストは、ダイパッド、上面の同心円状電極、下
面の円形電極を除いた基板上下両面に施されている。(1) A printed wiring board is prepared. A rectangular die pad is provided at the center of the upper surface of the substrate, metal wiring (conductor) is provided around the die pad, and a via hole provided at an end of the substrate is provided from the vicinity of the die pad. On the lower surface of the substrate, circular electrodes (conductors) are provided in a matrix, and metal wiring runs from the via hole to the circular electrode. Copper plating is applied to the inner wall of the via hole, and metal concentric electrodes (conductors) are provided at both ends (upper and lower surfaces of the substrate) of the via hole. Make sure the connection. In this way, an electric path from the vicinity of the die pad on the upper surface of the substrate to the circular electrode on the lower surface of the substrate is formed. The solder resist is applied to both the upper and lower surfaces of the substrate except for the die pad, the concentric electrodes on the upper surface, and the circular electrodes on the lower surface.
【００１４】（２）次いで、ダイパッドに銀ペーストを
塗布し半導体素子を搭載し１７５℃・１時間乾燥し固着
した。(2) Next, a silver paste was applied to the die pad, the semiconductor element was mounted, dried at 175 ° C. for 1 hour, and fixed.
【００１５】（３）次いで、半導体素子の能動面に設け
られたパッド電極と基板上面の金属配線の内端とを金属
細線で接続した。金属細線としては直径３０μｍの金線
を用い超音波併用熱圧着法で接続した。(3) Next, the pad electrode provided on the active surface of the semiconductor element was connected to the inner end of the metal wiring on the upper surface of the substrate by a thin metal wire. As a thin metal wire, a gold wire having a diameter of 30 μm was used and connected by thermocompression combined with ultrasonic waves.
【００１６】（４）次いで、前記基板をモールド金型に
装填し、トランスフアーモールド法により半導体素子を
被う様に樹脂で封止した。モールド工程の詳細は日経Ｂ
Ｐ社１９９３年刊行の「ＶＬＳＩパッケージング技術
（下）」３１ページから４０ページに述べられているの
で参照されたい。但し、本発明で実施したのは片側モー
ルドであるので、金型のキャビテイは半導体素子のある
上型だけに設けられている。(4) Next, the substrate was loaded into a mold and sealed with a resin by a transfer molding method so as to cover the semiconductor element. For details of the molding process, see Nikkei B
Please refer to page 31 to page 40 of "VLSI Packaging Technology (Lower)" published by P Company 1993. However, since the one-side mold is used in the present invention, the cavity of the mold is provided only in the upper mold having the semiconductor element.
【００１７】（５）次いで、基板下面の円形電極にフラ
ックスを塗布し、半田ボールを搭載したのち加熱溶融し
て半田ボールを取り付けた。この時、半田ボールは概略
球の一部を切断した形で円形電極に接着する。(5) Next, a flux was applied to the circular electrode on the lower surface of the substrate, solder balls were mounted, and then heated and melted, and solder balls were attached. At this time, the solder ball adheres to the circular electrode in a form in which a part of the sphere is roughly cut.
【００１８】図３は本発明の第２の実施例の断面図で、
キヤビテイーダウンタイプのＢＧＡである。図３におい
て、１は配線基板、２は半導体素子、３は球形電極、１
４は配線基板上面の円形電極（導体）、１５は配線基板
下面の円形電極（導体）、６ａ、６ｂはバイアホール、
７は金属細線、８は封止樹脂、１０はソルダーレジス
ト、１１はダイパッド、１３は配線基板内面の配線（導
体）である。本パッケージでは、金属細線７、配線基板
内面の配線１３、バイアホール６ａ、配線基板下面の円
形電極１５が半導体素子から球形電極に至る電気径路を
形成している。ＢＧＡの配線基板１の上面にはこの電気
径路とバイアホール６ａにより接続された円形電極１４
がソルダーレジスト１０、封止樹脂などの絶縁物に被わ
れることなく露出されている。円形電極１４は電気的導
体であるバイアホール６ａにより接続されることにより
前記電気径路と同電位になっている。FIG. 3 is a sectional view of a second embodiment of the present invention.
It is a cavity down type BGA. In FIG. 3, 1 is a wiring board, 2 is a semiconductor element, 3 is a spherical electrode, 1
4 is a circular electrode (conductor) on the upper surface of the wiring board, 15 is a circular electrode (conductor) on the lower surface of the wiring substrate, 6a and 6b are via holes,
7 is a thin metal wire, 8 is a sealing resin, 10 is a solder resist, 11 is a die pad, and 13 is a wiring (conductor) on the inner surface of the wiring board. In this package, the thin metal wire 7, the wiring 13 on the inner surface of the wiring board, the via hole 6a, and the circular electrode 15 on the lower surface of the wiring board form an electric path from the semiconductor element to the spherical electrode. On the upper surface of the BGA wiring board 1, a circular electrode 14 connected to the electric path and the via hole 6a is provided.
Are exposed without being covered with an insulator such as the solder resist 10 and the sealing resin. The circular electrode 14 is connected to the via hole 6a, which is an electric conductor, to have the same electric potential as the electric path.
【００１９】本実施例の半導体装置は以下のように製造
した。The semiconductor device of this embodiment was manufactured as follows.
【００２０】（１）プリント配線基板を用意する。この
基板１は多層基板であり、一部は内層まで削除されデバ
イスホールを形成している。デバイスホールの底部には
内層の一部であり半導体素子が搭載されるダイパッド１
１がある。ダイパッドの周囲には内層２層を使った金属
配線１３が設けられ、ダイパッド近傍からバイアホール
６ａに至っている。バイアホールはマトリックス状に配
置されており、バイアホールの内壁には銅メッキが施さ
れ、中は樹脂で充填され、下端には円形の電極１５が設
けられている。バイアホールの上端にも下端と同様に金
属の円形電極１４が設けられている。こうしてダイパッ
ド近傍から基板下面の円形電極に至る電気径路を形成し
ている。基板上面には放熱用金属層１２が設けられ、放
熱用バイアホール６ｂによりダイパッド１１と接続され
ている。ソルダーレジストは、基板上面の円形電極１
４、放熱用金属層１２、基板下面の円形電極１５、デバ
イスホールを除いた基板上下両面に施されている。(1) A printed wiring board is prepared. This substrate 1 is a multi-layer substrate, part of which is deleted to the inner layer to form a device hole. At the bottom of the device hole, a die pad 1 which is a part of an inner layer and on which a semiconductor element is mounted.
There is one. A metal wiring 13 using two inner layers is provided around the die pad, and extends from the vicinity of the die pad to the via hole 6a. The via holes are arranged in a matrix. The inner wall of the via hole is plated with copper, the inside is filled with resin, and a circular electrode 15 is provided at the lower end. At the upper end of the via hole, a metal circular electrode 14 is provided similarly to the lower end. Thus, an electric path from the vicinity of the die pad to the circular electrode on the lower surface of the substrate is formed. A heat dissipating metal layer 12 is provided on the upper surface of the substrate, and is connected to the die pad 11 through a heat dissipating via hole 6b. The solder resist is a circular electrode 1 on the upper surface of the substrate.
4. The heat dissipating metal layer 12, the circular electrode 15 on the lower surface of the substrate, and the upper and lower surfaces of the substrate excluding device holes are provided.
【００２１】（２）次いで、ダイパッドに銀ペーストを
塗布し半導体素子を搭載し１７５℃・１時間乾燥し固着
した。(2) Next, a silver paste was applied to the die pad, the semiconductor element was mounted, and dried at 175 ° C. for 1 hour to be fixed.
【００２２】（３）次いで、半導体素子の能動面に設け
られたパッド電極と基板内層に設けられた金属配線の内
端とを金属細線で接続した。金属細線としては直径３０
μｍの金線を用い超音波併用熱圧着法で接続した。(3) Next, the pad electrode provided on the active surface of the semiconductor element and the inner end of the metal wiring provided on the inner layer of the substrate were connected by a thin metal wire. The diameter is 30 as a thin metal wire
Connection was made by a thermocompression bonding method using ultrasonic waves using a gold wire of μm.
【００２３】（４）次いで、液状エポキシ樹脂をデバイ
スホール内に充填し、半導体素子、金属細線が隠れるま
で塗布したのち１５０℃・１時間乾燥し封止した。(4) Next, a liquid epoxy resin was filled in the device hole, applied until the semiconductor element and the fine metal wire were hidden, dried at 150 ° C. for 1 hour, and sealed.
【００２４】（５）次いで、基板下面の円形電極にフラ
ックスを塗布し、半田ボールを搭載したのち加熱溶融し
て半田ボールを取り付けた。この時、半田ボールは概略
球の一部を切断した形で円形電極に接着する。(5) Next, a flux was applied to the circular electrode on the lower surface of the substrate, solder balls were mounted, and then heated and melted to attach the solder balls. At this time, the solder ball adheres to the circular electrode in a form in which a part of the sphere is roughly cut.
【００２５】前記の第１の実施例、第２の実施例のいず
れでも、半導体素子の能動面に設けられたパッド電極と
基板に設けられた金属配線の内端とを金属細線で接続し
た例を示したが、半田バンプを用いたフリップチップ接
続、金バンプと導電性接着剤による接続あるいは異方性
導電膜による接続でもよい。In each of the first and second embodiments, the pad electrode provided on the active surface of the semiconductor element and the inner end of the metal wiring provided on the substrate are connected by a thin metal wire. However, flip-chip connection using a solder bump, connection using a gold bump and a conductive adhesive, or connection using an anisotropic conductive film may be used.
【００２６】[0026]
【発明の効果】本発明による半導体装置にあっては、Ｂ
ＧＡの配線基板の上面にＢＧＡ端子と電気的に接続した
電気径路の一部が絶縁物に被われることなく露出されて
いるので、ＢＧＡをマザーボードに実装した状態でもテ
スターを用いて電源電圧を点検したり、オシロスコープ
のプローブを当てて電気信号の波形を見て回路動作の良
否を点検することが可能である。特にマザーボードの回
路が正しく動作しない場合にその原因を解明するときに
は大いに威力を発揮する。ことに携帯電話やノート型パ
ーソナルコンピュータなどの携帯型電子機器ではマザー
ボードを小さくする事が必須であるので、マザーボード
に点検用の電極を設ける余裕がなく、本発明のＢＧＡは
このような用途に用いる多端子パッケージとして極めて
好適である。According to the semiconductor device of the present invention, B
A part of the electrical path electrically connected to the BGA terminal is exposed on the upper surface of the GA wiring board without being covered with an insulator. Therefore, even when the BGA is mounted on the motherboard, check the power supply voltage using a tester. It is possible to check the circuit operation by checking the waveform of the electric signal by applying a probe of an oscilloscope. This is especially useful when trying to find out why the circuit on the motherboard does not work properly. Particularly in portable electronic devices such as mobile phones and notebook personal computers, it is essential to reduce the size of the motherboard, so there is no room for providing an electrode for inspection on the motherboard, and the BGA of the present invention is used for such purposes. It is very suitable as a multi-terminal package.
【図１】本発明の第１の実施例で、半導体装置を上から
見た平面図。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, as viewed from above.
【図２】本発明の第１の実施例で、半導体装置を図１の
Ａ−Ａで切断した断面図。FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, taken along line AA of FIG. 1;
【図３】本発明の第２の実施例で、半導体装置の断面
図。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
【図４】第１の従来例で、半導体装置の断面図。FIG. 4 is a sectional view of a semiconductor device in a first conventional example.
【図５】第２の従来例で、半導体装置の断面図。FIG. 5 is a sectional view of a semiconductor device in a second conventional example.
１…配線基板 ２…半導体素子 ３…球形電極 ４…絶縁基板上面の配線 ５…絶縁基板下面の配線 ６ａ，６ｂ…バイアホール ７…金属細線 ８…封止樹脂 １０…ソルダーレジスト １１…ダイパッド １２…放熱用金属層 １３…内層の金属配線 １４…基板上面の円形電極 １５…基板下面の円形電極 DESCRIPTION OF SYMBOLS 1 ... Wiring board 2 ... Semiconductor element 3 ... Spherical electrode 4 ... Wiring on the upper surface of an insulating substrate 5 ... Wiring on the lower surface of an insulating substrate 6a, 6b ... Via hole 7 ... Fine metal wire 8 ... Sealing resin 10 ... Solder resist 11 ... Die pad 12 ... Metal layer for heat radiation 13 ... Metal wiring of inner layer 14 ... Circular electrode on upper surface of substrate 15 ... Circular electrode on lower surface of substrate
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/12
Claims (1)
面に導体が設けられ該導体の少なくとも一部が絶縁性皮
膜で被われ、複数のバイアホールを備えた配線基板と、
該配線基板の一面に搭載された半導体素子と、該半導体
素子と前記導体の少なくとも一部を被う絶縁性樹脂と、
前記配線基板の第１面に設けられた球形端子群とを含ん
で成り、前記半導体素子の電極群と前記球形端子群とを
電気的に接続する電気径路群が形成された半導体装置に
おいて、 前記半導体素子が該配線基板の第２面に搭載され、 前記 第２面に設けられ前記電気径路と同電位の前記導体
の一部が前記絶縁性皮膜あるいは前記絶縁性樹脂から露
出し、 露出された前記導体の一部が、前記バイアホールの直上
に位置し、該バイアホールと同心円をなす同心円状電極
として形成された ことを特徴とする半導体装置。At least a first surface and a second surface opposite to the first surface.
A conductor provided on the surface, at least a part of the conductor is covered with an insulating film, and a wiring board having a plurality of via holes ;
A semiconductor element mounted on one surface of the wiring substrate, and an insulating resin which covers at least a part of the with the semiconductor element conductor,
In the comprises a spherical terminal group provided on the first surface of the wiring board, a semiconductor device electrically path group is formed for electrically connecting the electrode group of the semiconductor element and the spherical terminal group, wherein a semiconductor element is mounted on the second surface of the wiring substrate, a portion of the conductor of the electrical path and the same potential is provided on the second surface is exposed from the insulating film or the insulating resin
The exposed and exposed part of the conductor is located just above the via hole.
A concentric electrode located concentrically with the via hole
A semiconductor device formed as:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30314695A JP3296168B2 (en) | 1995-11-21 | 1995-11-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30314695A JP3296168B2 (en) | 1995-11-21 | 1995-11-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09148480A JPH09148480A (en) | 1997-06-06 |
| JP3296168B2 true JP3296168B2 (en) | 2002-06-24 |
Family
ID=17917444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30314695A Expired - Fee Related JP3296168B2 (en) | 1995-11-21 | 1995-11-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3296168B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100308899B1 (en) * | 1998-12-29 | 2001-11-15 | 마이클 디. 오브라이언 | semiconductor package and method for fabricating the same |
| KR100400672B1 (en) * | 1999-08-24 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | circuit board for semiconductor package |
| KR20020085603A (en) * | 2001-05-09 | 2002-11-16 | 주식회사 실리콘 테크 | Booting error free apparatus when semiconductor device function testing use of pc mother board |
-
1995
- 1995-11-21 JP JP30314695A patent/JP3296168B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09148480A (en) | 1997-06-06 |
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