JP3287013B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an SR memory device having soft error resistance against alpha rays or the like.
It relates to the structure of a memory cell in AM.

[0002]

2. Description of the Related Art Recently, a CMOS SRAM using a CMOS inverter has attracted attention as an effective means for reducing the power consumption of an SRAM. However, in the CMOS circuit, a region for separating the N-MOS transistor and the P-MOS transistor is required, which is disadvantageous for high integration.

Therefore, conventionally, a P-MOS transistor used as a load is constituted by an inverted stagger type TFT (thin film transistor), so that a CMOS SR
High integration of AM is aimed at. That is, P-channel type TF
By stacking T (hereinafter simply referred to as P-TFT) on the N-MOS transistor, the area occupied by the CMOS circuit is significantly reduced, and high integration of the CMOS SRAM can be easily realized.

The configuration of a conventional CMOS SRAM will be described with reference to an equivalent circuit diagram of FIG. 6 and a sectional view of FIG.

As shown in FIG. 6, a conventional SRAM has a pair of driver transistors (N-MOS transistors).
Tr ₁ and Tr ₂ and their driver transistors Tr ₁
And Tr ₂ of the storage nodes N ₁ and N ₂ connected to a pair of P-channel type thin film transistor (hereinafter, simply P-TF
A memory cell is composed of a flip-flop circuit FF composed of a load composed of T ₁ and T ₂ and a pair of access transistors (N-MOS transistors) Q ₁ and Q ₂ . In the drawing, WL is a word line, and BL and (inverted BL) are bit lines.

More specifically, the structure of this SRAM will be described with reference to FIG. 7. A driver transistor T is formed on a P-type well region 31 via a gate insulating film 32 made of SiO ₂ or the like.
r ₁ gate electrode GD _{1 and} access transistor Q
_{A second} gate electrode (word line) WL is formed of, for example, a first semiconductor layer, for example, a polycide layer, and a P-TFT (T ₁ ) is formed on these gate electrodes GD ₁ via an interlayer insulating film 33 made of SiO _2. and T ₂ gate electrode GT ₁ and GT ₂ are second-layer semiconductor layer) is formed by, for example, polycrystalline silicon layer, S on gate electrodes GT ₁ and GT ₂
via an interlayer insulating film 34 made of iO ₂ P-TFT (T
Active layer Ac ₁ and Vcc line 35 is the third-layer semiconductor layer _1), for example, it is constituted by forming at polycrystalline silicon layer.

The gate electrode GD _{1 of the} driver transistor
Memory node N ₁ shown in FIG. 6 in the connection portion between the one of the source and drain regions SD of the access transistor Q ₂ is formed with. Reference numerals 36 and 37 denote interlayer insulating films made of SiO _2, and reference numeral 38 denotes a wiring for extracting a bit line made of a metal film such as Al. Reference numeral 39 denotes a P-type silicon substrate, and reference numeral 40 denotes an N-type well region.

[0008] Conventionally, software
P-TFT (T₁) Gate power
Extreme GT₁To the active layer Ac₁The above storage node N₁Connected to
Extending below the drain region 41D to be formed.
From the gate electrode GT₁Between drain and drain region 41D
The capacity is formed. In this case, the P-TFT
(T₁) Gate electrode GT₁And driver transistor T
r₁Gate electrode GD ₁A coupling capacitance is also formed between them.

That is, when this configuration is viewed in terms of an equivalent circuit, as shown in FIG. 6, the storage node N ₁ and the storage node N ₂ are connected by a coupling capacitance C. (IEDM
88 P48-P51 “A25 μm ² , New Pol
y-Si PMOS Load (PPL) SRAM
Cell Having Excellent So
ft ErrorImmunity ”)

[0010]

The above-mentioned SR
In AM, a P-TFT (T₁, T_Two) Saw
Area 41S becomes the Vcc power supply line as it is,
P-TFT (T₁, T_Two)of
The source region 41S and the drain region 41D have 10 ¹⁹cm
^-3It is formed simultaneously with the above high impurity concentration.

When a coupling capacitance is formed at the overlapping portion of the drain region 41D having a high impurity concentration and the gate electrodes GT ₁ and GT ₂ as described above, when a gate electric field is applied to the drain region 41D, the drain region 41D comes into contact with the channel region 41C. At the end of the drain region, a drain leak occurs due to an inter-band tunneling current, causing a problem that the off-state current of the P-TFT (T ₁ , T ₂ ) increases.

In view of the above, the present invention provides a semiconductor memory device capable of forming a coupling capacitance without increasing drain leakage, ie, off current, in a semiconductor thin film transistor.

[0013]

A semiconductor memory device according to the present invention comprises a pair of driver transistors Tr ₁ and Tr _2.
And a flip-flop circuit FF composed of a pair of semiconductor thin film transistors T ₁ and T ₂ stacked on the driver transistors Tr ₁ and Tr _{2 with the} storage nodes N ₁ and N ₂ as connection points, respectively. A memory cell is composed of a pair of access transistors Q ₁ and Q ₂ ,
Gate electrodes GD of driver transistors Tr ₁ and Tr _2
1 and GD ₂ are formed by a first semiconductor layer, and a semiconductor thin film transistor is formed.
Transistor T _1, the gate electrode GT ₁ of T _2, GT ₂ 2
A semiconductor thin film transistor formed of a semiconductor layer
The active layers Ac ₁ and Ac _{2 of} T ₁ and T ₂ are the third semiconductor layers.
It is formed, one of the source of the access transistor Q _2, Q ₁
Source / drain region SD and driver transistor T
The gate electrodes GD ₁ and GD _{2 of} r ₁ and Tr ₂ are connected.
In the storage nodes N ₁ and N ₂ , the first semiconductor layer
Gate electrodes of driver transistors Tr ₁ and Tr ₂
A semiconductor thin film transistor with a second semiconductor layer on GD ₁ and GD ₂
Through the gate electrodes GT ₂ and GT ₁ of the transistors T ₂ and T ₁
To form a semiconductor thin film transistor T using a third semiconductor layer.
₁ , the drain region 10D of the active layers Ac ₁ and Ac ₂ of T ₂
And the gate electrodes GT ₁ and GT _{2 of} the semiconductor thin film transistors T ₁ and T ₂ are extended to below the drain region 10 D connected to the storage nodes N ₁ and N ₂ of the active layers Ac ₁ and Ac ₂ , respectively. 10D and gate electrode G
_A coupling capacitance C (C _A , C _B ) is formed between T ₁ and GT ₂ , and the storage nodes N ₁ and N ₂ are connected by the coupling capacitance C (C _A , C _B ) to constitute a coupling capacitance Drain region (portion of the drain region overlapping the gate electrode) 10
The impurity concentration of D ₁ is a configuration a lower concentration than the impurity concentration of the source region 10S of the semiconductor thin film transistor.

In the semiconductor memory device according to the present invention, a pair of driver transistors Tr ₁ and Tr ₂ and storage nodes N ₁ and N _{2 are provided} on the driver transistors Tr ₁ and Tr ₂ , respectively.
A flip-flop circuit FF composed by ₂ comprising a semiconductor thin film transistor T _1, T ₂ of a pair of stacked as a connection point load, a memory cell is constituted of a pair of access transistors Q _1, Q ₂ Prefecture, driver Tiger
Njisuta Tr _1, the gate electrode GD ₁ of the Tr _2, GD ₂ is
A semiconductor thin film transistor T formed of a first semiconductor layer
₁ and T ₂ gate electrodes GT ₁ and GT ₂ are the second semiconductor layers
And the activity of the semiconductor thin film transistors T ₁ and T ₂
The layers Ac ₁ and Ac ₂ are formed of a third semiconductor layer,
Source / drain region of one of the transistors Q ₂ and Q ₁
Area SD and gates of driver transistors Tr ₁ and Tr ₂
Storage nodes N ₁ , N connected to electrodes GD ₁ , GD _2
In part _2, the driver transistor by the first semiconductor layer
_{2 on} the gate electrodes GD ₁ and GD ₂ of the transistors Tr ₁ and Tr 2.
Semiconductor thin film transistors T ₂ , T ₁ using the first semiconductor layer
Third semiconductor layer via the gate electrodes GT ₂ and GT ₁
Active layer Ac of semiconductor thin film transistors T ₁ and T _2
1 and the drain region 10D of Ac ₂ are connected, and the gate electrodes GT ₁ and GT _{2 of the} semiconductor thin film transistors T ₁ and T ₂ are connected.
There the active layer Ac _1, Ac ₂ memory node N _1, coupling N until connected under the drain region 10D ₂ is extended between the drain region 10D and the gate electrode GT _1, GT ₂ capacitance C (C _A, C _B ) is formed, and the coupling capacitance C (C _A ,
C _B ) connects the storage nodes N ₁ and N _{2 with} each other, and includes a drain region including a portion constituting the coupling capacitances C _A and C _B (that is, a portion 10D ₁ overlapping the gate electrode and a portion 10D ₂ other than the gate electrode). The configuration is such that the impurity concentration of the entire drain region (10D) is lower than the impurity concentration of the source region 10S of the semiconductor thin film transistors T ₁ and T ₂ .

[0015]

According to the present invention, the coupling capacitance C _A of the drain region 10D, by the impurity concentration of C _B constitute part 10D ₁ in lower concentration than that of the source region 10S, a gate electrode GT _1, GT ₂ And drain region 10
Desired coupling capacitances C _A and C _B are formed between D and
The drain leak due to the inter-band tunneling current at the end of the drain region in contact with the channel region 10C is suppressed, and the off current does not increase. Access transistor
The source / drain region SD of _one of Q ₂ and Q ₁
The gate electrodes GD ₁ , G of the transistors Tr ₁ , Tr ₂
In the storage nodes N ₁ and N ₂ connected to D ₂ ,
The gate electrode GD ₁ of the first layer semiconductor layer, a semiconductor on GD ₂
Gate by a second layer a semiconductor layer of the thin film transistor T _2, T ₁
Via the gate electrodes GT ₂ and GT ₁
Drain region 1 with third semiconductor layer of T ₁ and T ₂
0D is connected, so the step at the connection is small and each semiconductor
Body layers are connected with good coverage.

In the present invention, the coupling capacitances C _A ,
C _B constitute part 10D ₁ and other portions 10 of the
When a lower concentration than the source region 10S of the impurity concentration in the entire drain region 10D including the D ₂ also, similarly, the gate electrode GT _1, GT ₂ and between the drain region 10D desired coupling capacitance C _A, is C _B While being formed, drain leakage due to interband tunneling current at the end of the drain region is suppressed, and the off current does not increase. Also,
As described above, in the portion of the storage nodes N ₁ and N ₂ , the first semiconductor layer
Thin film transistors on the gate electrodes GD ₁ and GD ₂
The gate electrode G of the second semiconductor layer of T ₂ and T ₁
The semiconductor thin film transistors T ₁ , T ₁ , T ₂ , GT ₁
Drain region 10D is connected by 3-layer semiconductor layer of T ₂
The step at the connection is small and each semiconductor layer is covered.
Ledge is well connected.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 is a plan view showing the configuration of the SRAM according to the present embodiment, FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is an enlarged view of a main part thereof. FIG. 4 is an equivalent circuit diagram of the SRAM according to this embodiment.

As shown in FIG. 4, the SRAM according to this embodiment has a pair of driver transistors (N-MOS transistors) Tr ₁ and Tr ₂ and the storage nodes N ₁ and N of these driver transistors Tr ₁ and Tr _{2. 2} is connected to a pair of P-channel thin film transistors (hereinafter simply referred to as P
And referred) and the flip-flop circuit FF constituted by a load consisting of T ₁ and T ₂ -TFT, the memory cell is composed of a pair of access transistors (N-MOS transistor) Q ₁ and Q ₂ Metropolitan. In the drawing, WL is a word line, and BL and (inverted BL) are bit lines.

The structure of this SRAM is shown in FIGS.
As shown in FIG._TwoGe consisting of etc.
Driver transistor Tr via the gate insulating film 2₁as well as
Tr _Two(Tr_TwoFor each gate electrode G of FIG. 1).
D₁And GD_TwoAnd access transistor Q₁And Q
_Two(Q₁The gate electrode of FIG.
For example, if the gate line WL is a first semiconductor layer, for example, polycide
And a gate electrode (GD)₁, G
D_Two) And SiO on WL_TwoVia an interlayer insulating film 3 made of
And P-TFT (T₁And T_Two) Of each gate electrode GT₁
And GT_TwoIs the second semiconductor layer, for example, polycrystalline silicon
Formed in layers, and these gate electrodes GT₁And GT_TwoUp
P-TFT (T₁And T_Two) Of each active layer Ac₁And A
c_Two(Ac_TwoFor details, see FIG._CCLine 4 is 3
The first semiconductor layer, for example, formed of polycrystalline silicon
Be composed.

The storage nodes N ₁ and N 2 shown in FIG. 4 are connected to the gate electrodes GD ₁ and GD _{2 of} each of the driver transistors Tr ₁ and Tr ₂ and the source / drain regions SD of the access transistors Q ₁ and Q ₂ . ₂ is configured. The storage nodes N ₁ and N ₂ are shown in FIGS.
As shown, the gate electrode GD of the first polycrystalline silicon layer
₁ and GD ₂ on the semiconductor thin film transistors T ₂ and T ₁ .
Gate electrodes GT ₂ and GT _{1 made} of a polycrystalline silicon layer
Through the third layer of the semiconductor thin film transistors T ₁ and T ₂
Active layer Ac by polycrystalline silicon layer _1, Ac ₂ slaves
Connection region 10D is connected.

5 and 6 are SiO._TwoInterlayer insulation consisting of
Film 7 is a bit line take-out arrangement made of a metal film such as Al.
Line, 8 is a P-type silicon substrate, 9 is an N-type well region
is there. 10S is the power supply V_CCSource region to which is applied
Area, 10D is storage node N₁, N _TwoDray connected to
Region, 10C is a channel region, 13 is a gate insulating film,
14 is a ground line (V_SSLine).

In order to prevent soft errors due to α rays or the like, the gate electrodes GT ₁ and GT ₂ of the P-TFTs (T ₁ and T ₂ ) are connected to the corresponding active layers Ac ₁ and Ac.
₂ is formed to extend to under the drain region 10D is connected to the memory node N ₁ and N _2, the overlapping portions 10 consuming the gate electrode GT ₁ and GT ₂ and the drain region 10D
_A coupling capacitance C _A and C _B are formed between D ₁ and D ₁ , respectively. In this case, the gate electrodes GT ₁ and GT _{2 of} the P-TFTs (T ₁ and T ₂ ) and the driver transistor T
A coupling capacitance is also formed between the gate electrodes GD ₁ and GD _{2 of} r ₁ and Tr ₂ .

When this configuration is viewed in terms of an equivalent circuit, as shown in FIG. 4 , the storage nodes N ₁ and N ₂ are connected by a coupling capacitance C, and this coupling capacitance C (C _A , C _B )
Can control the soft error.

In this embodiment, however, the drain region 1
0D coupling capacitance C_AAnd C_BConnected to the gate region G
T₁, GT_Two10D that overlaps₁The impurity concentration of
In region gate electrode GT₁, GT_TwoPart that does not overlap with
(That is, storage node N₁And N _TwoThe part to be connected with
Min) 10D_TwoAnd lower than the impurity concentration of the source region 10S.
To the concentration.

[0025] That is, the source region 10S of the P over TFT (T ₁ and T ₂₎ are, since the Sosomama V _CC line 4, a drain region 10D formed simultaneously from a need to lower the wiring resistance source region 10C and this and Storage nodes N ₁ ,
The side of the 10D which is connected to the N _{2 2} is doped with an impurity in a high concentration of more than 10 ¹⁹ cm ^-3 order. For example, active layers Ac ₁ and Ac ₂ of a polycrystalline silicon layer having a thickness of 400 °
This is achieved by implanting BF ₂ ⁺ ions at a dose of about 1 × 10 ¹⁵ cm ⁻² .

On the other hand, the coupling capacitance C of the drain region 10D_A
And C_BGate electrode GT in which₁, GT_TwoAnd heavy
Part 10D₁Impurity concentration is 10¹⁸cm^-3Less than order
Lower to lower concentration. For example, a 400 mm thick
Active layer Ac of crystalline silicon layer ₁, Ac_TwoAgainst BF_Two
⁺10¹³cm^-2Ion implantation at a moderate dose
Is achieved by

According to the structure of this embodiment, the P-TFT (T
₁ and T ₂ ) by extending each of the gate electrodes GT ₁ and GT ₂ to a position below the drain region 10 D of the corresponding active layer Ac ₁ and Ac ₂ , thereby forming a drain region 10 D overlapping the gate electrodes GT ₁ and GT _2. coupling capacitance C _a for between portions 10D ₁ soft error prevention in can form a C _B.

[0028] Then, in particular the impurity concentration of the portion 10D ₁ which overlaps with the gate electrode GT ₁ and GT ₂ of the drain region 10D, by the lower concentration than the impurity concentration of the other portions 10D ₂ and the source region 10S of the drain region, At the end of the drain region in contact with the channel region 10C, drain leakage (so-called leakage due to gate electric field) due to interband tunneling current can be suppressed. Therefore, it is possible to form a coupling capacitance that fluctuates a sufficient capacitance value without increasing the off current of the P-TFT (T ₁ and T ₂ ). In the part of the storage nodes N ₁ and N ₂ , FIG.
As shown in FIG. 3, the gate voltage of the first polycrystalline silicon layer
A gate of a second polycrystalline silicon layer on poles GD ₁ and GD ₂
Semiconductor thin film transistor through the gate electrodes GT ₂ and GT ₁
Active layer Ac of the third polycrystalline silicon layer of T ₁ and T _2
1 , the drain region 10D _{2 of} Ac ₂ is connected,
The step at the connection part is small and each polysilicon layer is covered
To provide a highly reliable semiconductor memory device
Can be provided.

FIG. 5 shows another embodiment of the present invention. In the embodiment of FIG. 3 described above, although the impurity concentration of the portion 10D ₁ which overlaps with the gate electrode GT ₁ and GT ₂ of the drain region 10D lightly, other, as shown in the embodiment of FIG. 5,
Side portion 10 of which connected to the gate electrode GT _1, GT ₂ and the overlapped part 10D ₁ and the other storage nodes N _1, N ₂
It is also possible to configure the entire drain region 10D including the D ₂ in the lower concentration than the impurity concentration of the source region 10S. Even in this configuration, the band between the bands at the end of the drain region
The drain leak due to the tunneling current is suppressed, and the gate electrodes GT ₁ , GT
_A coupling capacitance can be formed between the _second and the drain region 10D. Moreover, parts of the case storage nodes N _1, N ₂
The gate electrode G of each first polycrystalline silicon layer.
D ₁ , GD ₂ and gate electrode G of second polycrystalline silicon layer
T ₂ , GT ₁ and drain region of third polycrystalline silicon layer
The difference in level at the interconnecting part with 10D is small,
Recon layer is connected with good coverage and reliable semiconductor
A body memory device can be provided.

[0030]

According to the semiconductor memory device of the present invention, it is possible to form a coupling capacitance between a gate electrode and a drain region of a semiconductor thin film transistor for preventing a soft error due to α rays or the like without increasing an off current. Can be . Furthermore, increase the connection reliability at the storage node part
be able to. Therefore, high reliability of the semiconductor memory device can be achieved.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of an SRAM according to the present invention.

FIG. 2 is a cross-sectional view taken along line AA of FIG.

FIG. 3 is an enlarged view of a main part of FIG. 2;

FIG. 4 is an equivalent circuit diagram of the SRAM according to the present invention.

FIG. 5 is a sectional view of a main part showing another example of the SRAM according to the present invention.

FIG. 6 is an equivalent circuit diagram of a CMOS SRAM.

FIG. 7 is a sectional view of an SRAM according to a conventional example.

[Explanation of symbols]

Tr _1, Tr ₂ driver transistors _{T 1, T 2 P-TFT} Q 1, Q 2 access transistors N _1, N ₂ storage node C (C _A, C _B) binding capacity GD _1, GD ₂ gate electrode Ac _1, Ac ₂ active layer WL word line BL, inverted BL bit line 1 P-type well region 2 gate insulating film 3, 5, 6 interlayer insulating film 4 V _CC line 7 bit line take-out wiring 8 silicon substrate 9 N-type well region 10S source region 10D (10D _1, 10D ₂₎ drain region 10C channel region 14 ground line

Claims (2)

(57) [Claims] 1. A flip-flop circuit comprising a pair of driver transistors, a load composed of a pair of semiconductor thin-film transistors stacked on the driver transistors, each having a storage node as a connection point, and a pair of access transistors. A memory cell is formed, and a gate electrode of the driver transistor is a first-layer semiconductor.
A gate electrode of the semiconductor thin film transistor.
The pole is formed of the second semiconductor layer, and the semiconductor thin film transistor is formed.
An active layer of a transistor is formed by a third semiconductor layer, and one source / drain region of the access transistor is formed.
Region is connected to the gate electrode of the driver transistor.
In the portion of the storage node that has been added, the first semiconductor layer
The second layer on the gate electrode of the driver transistor.
The gate electrode of a semiconductor thin film transistor with a semiconductor layer
Through the semiconductor thin film transistor of the third semiconductor layer
The drain region of the active layer of the transistor is connected, the gate electrode of the semiconductor thin film transistor extends to below the drain region of the active layer connected to the storage node, and a coupling capacitance is formed between the drain region and the gate electrode; The coupling capacitance connects the storage nodes to each other, and the impurity concentration of the drain region of the portion forming the coupling capacitance is increased.
A semiconductor memory device having a lower concentration than an impurity concentration of a source region of the semiconductor thin film transistor . 2. A flip-flop circuit comprising a pair of driver transistors, a load composed of a pair of semiconductor thin film transistors stacked on the driver transistors, each having a storage node as a connection point, and a pair of access transistors. A memory cell is formed, and a gate electrode of the driver transistor is a first-layer semiconductor.
A gate electrode of the semiconductor thin film transistor.
The pole is formed of the second semiconductor layer, and the semiconductor thin film transistor is formed.
An active layer of a transistor is formed by a third semiconductor layer, and one source / drain region of the access transistor is formed.
Region is connected to the gate electrode of the driver transistor.
In the portion of the storage node that has been added, the first semiconductor layer
The second layer on the gate electrode of the driver transistor.
The gate electrode of a semiconductor thin film transistor with a semiconductor layer
Through the semiconductor thin film transistor of the third semiconductor layer
The drain region of the active layer of the transistor is connected, the gate electrode of the semiconductor thin film transistor extends to below the drain region of the active layer connected to the storage node, and a coupling capacitance is formed between the drain region and the gate electrode; The connection between the storage nodes is performed by the coupling capacitance, and the drain region includes a portion forming the coupling capacitance.
A semiconductor memory device, wherein an impurity concentration is lower than an impurity concentration of a source region of the semiconductor thin film transistor .