JP3286155B2 - Constant voltage circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage circuit which can obtain a predetermined voltage by utilizing a difference in a shresh hold voltage of a MOS transistor and which voltage is hardly affected by a temperature change.

[0002]

2. Description of the Related Art A constant voltage circuit which obtains a predetermined voltage by utilizing a difference in a shreshold voltage is disclosed in, for example, Japanese Patent Laid-Open No. 1-240.
No. 917. FIG. 3 is a circuit diagram thereof.
Depletion type MOS transistors Q10, Q1
1. An enhancement type MOS transistor Q12 is connected in series, and a transistor Q11 and a transistor Q1 are connected.
A voltage is obtained from the output terminal 1 at the connection point 2. Transistor Q10 serves as a current source. Transistor Q
The gate and source of the transistor 10 are connected, the gates of the remaining transistors Q11 and Q12 are connected to each other, and the gate is connected to the source and the gate of the transistor Q10. 2
Is a power supply terminal connected to the power supply voltage V _CC .

FIG. 4 is a characteristic diagram showing a relationship between a source-drain current I _DS and a gate-source voltage V _GS .
0, 11 and 12 are transistors Q10, Q11 and Q, respectively.
12 shows 12 characteristic curves. V ₁₀ the transistor Q1
0, Q11 shoe-less hold voltage of, V ₁₂ Zhu less hold voltage of the transistor 12, I _10, the transistor Q
The current flowing in the series circuit when the gate-source voltage V _{GS of 10} is 0 V, and V ₁₁₁ and V ₁₂₁ are the gate-source voltages of the transistors Q 11 and Q 12 when the current I ₁₀ flows. In this case, the voltage V ₁ shown in the equation (1) is obtained at the output terminal 1. V ₁ = V ₁₂₁ −V ₁₁₁ (1) If the characteristic curves of the transistors Q11 and Q12 have the same gradient, the equation (2) is established. V ₁₂₁ -V ₁₁₁ = V ₁₂ -V ₁₀ = V ₁ (2)

[0004] The slope of the characteristic curve changes depending on the temperature and is susceptible to the change, but the shreshold voltage is hardly affected by the temperature. Therefore, it hardly affected by the temperature change by that can be set by the difference between the shoe-less hold voltage as voltages V ₁ obtained at the output terminal 1 (2). However, such a conventional constant voltage circuit is composed of three transistors connected in series, there is a disadvantage that the output impedance so obtaining voltages V ₁ from the connection point increases.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to reduce the output impedance of a constant voltage circuit to facilitate connection with another circuit.

[0006]

According to the present invention, there is provided a constant voltage circuit comprising:
A current source, enhancement-type first and second MOS transistors, and a third MOS transistor, wherein the first MOS transistor has a gate and a drain connected to each other and connected to the current source, and the second MOS transistor has a third MOS transistor; MO
The gate is connected to the S transistor in series and the gate is connected to the gate of the first MOS transistor. Third MOS
The transistor has a gate connected to a current source. 2nd M
The shape and size of the OS transistor and the third MOS transistor are substantially the same, and a predetermined voltage is obtained from the connection point.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A constant voltage circuit according to the present invention comprises at least three MOS transistors and a current source, and a predetermined voltage is obtained from a connection point between two transistors connected in series. The voltage at the connection point is set by the difference between the shreshold voltages of the two transistors. The current source is not connected in series with the two transistors,
The voltage provided by the current source is applied to the gates of the two transistors.

[0008]

FIG. 1 shows an embodiment of a constant voltage circuit according to the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals. In FIG. 1, Q1 and Q2 are N-channel first and second MOS transistors of an enhancement type.
Q3 is an N-channel third MO
It is an S transistor. Transistor Q3 may be either an enhancement type or a depletion type. Q4 is a depletion-type N-channel fourth transistor, which functions as a current source S1.

The transistor Q1 has its gate and drain connected, its drain connected to the source of the transistor Q4, and its source grounded. Transistor Q2 has a gate connected to the gate of transistor Q1, a source grounded, and a drain connected to the source of transistor Q3.
The gate of transistor Q3 is connected to the gate of transistor Q4, and the drain is connected to power supply terminal 2 to which power supply voltage V _CC is applied. The transistor Q4 has a gate and a source connected to each other, and a drain connected to a power supply terminal. Therefore,
The gate of the transistor Q3 is the drain of the transistor Q1.
Connected to the gate. Note that the transistor Q3 forms a source follower circuit. The voltages V ₁ to be output is obtained at the output terminal 1 of the connection point of the transistors Q2 and Q3. The shape and size of the transistor Q2 and the transistor Q3 are the same. Further, the shresh hold voltage of the transistor Q1 and the transistor Q2 are the same. As a result, the transistor Q1 and the transistor Q2 constitute a current mirror circuit when the threshold voltage is equal to or higher than the same threshold voltage, and the constant voltage circuit can be operated in a wide fluctuation range of the power supply voltage V _CC .

In the constant voltage circuit configured as described above, all transistors are operated in a saturated state,
Equations (3) and (4) hold. _{I D2 = k 2 (V G3} -V T2) 2 (3) I D3 = k 3 (V G3 -V 1 -V T3) 2 (4) In _{addition, k 2, I D2, V} T2 are the respective transistors Q2 Conductivity coefficient, drain current, shreshold voltage, k ₃ , I
_D3 and _VT3 are the conductivity coefficient, drain current, and shreshhold voltage of the transistor Q3, respectively, and _VG3 is the transistor Q3.
The gate voltage of, V ₁ is the voltage obtained at the terminal 1.

Since the transistor Q2 and the transistor Q3 have the same shape and size and are connected in series, I _D2 = I _D3 and k ₂ = k ₃ . Therefore,
Equation (5) holds, and equation (6) is obtained. (V _G3 −V _T2 ) = (V _G3 −V ₁ −V _T3 ) (5) V ₁ = V _T2 −V _T3 (where V _T2 > V _T3 ) (6) That is, the voltage V ₁ is equal to the voltage of the transistor Q2. Shrewsbury-less hold voltage V _T2, is set only by the shoe-less hold voltage V _T3 of the transistor Q3.

The conditions for operating the transistors Q1 and Q2 in a saturated state are shown by equations (7) and (8), and equation (9) holds. Therefore, the gate voltage V _G3
Is in the range shown by the expression (9). _{V G2 = V G3> V T2} (7) V G3 -V T2 <V 1 (8) V T2 <V G3 <2V T2 -V T3 (9) voltage V _G3 is preferably set in the range of (9) Therefore, a resistor, a diode, M
An OS transistor is connected, and the voltage _VG3 is obtained from the transistor Q1 side end, so that the value can be reduced. In that case, a circuit element other than the transistor Q4 functions as a current source.

FIG. 2 is a circuit diagram showing another embodiment of the constant voltage circuit according to the present invention, wherein the current source S1 is a depletion type P
This is different from FIG. 1 in that the channel MOS transistor 41 is formed. The gate and source of MOS transistor 41 are connected to power supply terminal 2 and the drain is connected to transistor Q1. In the configuration of FIG. 2, the circuit operates in the same manner as in FIG. Note that a resistor may be connected between the transistor Q1 and the power supply terminal 2 in the embodiment to function as the current source S1. It goes without saying that the transistors Q1, Q2, Q3 may be P-channel. In that case, the transistors Q1, Q2
Is connected to the power supply terminal 2, the drain of the transistor Q3 and the current source are grounded.

[0014]

As described above, the constant voltage circuit according to the present invention comprises at least three MOS transistors and a current source, and a voltage can be obtained from a connection point of two transistors connected in series. The two transistors connected in series form a source follower circuit, and the output impedance can be reduced. Therefore, connection with other circuits is facilitated, and the circuit can be used as a circuit for impedance matching. In addition, the first and second
There is also an advantage that the constant voltage circuit can be operated in a wide range of fluctuation of the power supply voltage by making the shresh hold voltage of the transistors the same.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a constant voltage circuit according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the constant voltage circuit of the present invention.

FIG. 3 is a circuit diagram of a conventional constant voltage circuit.

FIG. 4 is a characteristic diagram of a transistor of a conventional constant voltage circuit.

[Explanation of symbols]

 Q1 First MOS transistor Q2 Second MOS transistor S3 Third MOS transistor S1 Current source

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-162121 (JP, A) JP-A-61-127018 (JP, A) JP-A-62-72019 (JP, A) JP-A 57-162 41721 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G05F 3/24

Claims (3)

(57) [Claims] (1)A current source; Gate and drain are connected
And an enhancer whose drain and gate are connected to the current source.
A first MOS transistor of an element type; The gate is connected to the gate of the first MOS transistor.
, Enhancement-type second MOS transistor
When, A gate is connected between the current source and the first MOS transistor.
The drain is connected to the gate and the source is the second MOS.
The shape and size of the transistor connected to the drain
Is approximately the same as the second MOS transistor.
S transistor And the second MOS transistor
Between the drain of the third MOS transistor and the source of the third MOS transistor.
A predetermined voltage is obtained from the connection point Characterized by a constant current
Pressure circuit. (2)A current source connected to the first voltage source; The gate and the drain are connected, and the drain and the gate
Connected to a current source, the source connected to a second voltage source
A first MOS transistor of an enhancement type; The gate is connected to the gate of the first MOS transistor.
Wherein the source is connected to the second voltage source;
A second MOS transistor of a segment type; A gate is connected between the current source and the first MOS transistor.
Connected to the drain and the gate, the drain being connected to the first voltage
And the source is connected to the second MOS transistor.
Connected to the drain, the shape and size of the second M
Third MOS transistor almost the same as the OS transistor
When And the drain of the second MOS transistor
A predetermined distance from a connection point of the source of the third MOS transistor
Voltage A constant voltage circuit, characterized in that: 3. A depletion type fourth MOS transistor having a source and a gate connected as a current source.
Constant voltage circuit as claimed in claim 1 or claim 2 that.