JP3285317B2 - Superimposed voice control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speech superimposition control system using a speech synthesis circuit.

[0002]

2. Description of the Related Art Conventionally, in a system for producing a sentence (text) using a speech synthesis circuit (a so-called speech synthesis IC), apart from an amplifier circuit and a speaker for speech production for producing a sentence, An amplifier circuit for an operation sound (such as a BEEP sound) generated when a switch or the like is operated and a piezoelectric buzzer are provided.

[0003]

In the above-mentioned conventional system, a device for operating sound (an amplifier circuit and a piezoelectric buzzer, etc.) is required separately, so that the number of circuit components increases and the circuit design becomes complicated. was there. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide a voice superimposed utterance control system capable of reducing the number of components and designing a circuit saving circuit.

[0004]

In order to achieve the above object, the present invention has a memory for storing a plurality of phrases, and a sentence combining one or a plurality of phrases read from the memory. A voice synthesizing circuit that converts the signal into a voice signal and outputs the voice signal separately from a plurality of channels; a driver unit that gives the voice synthesizing circuit an instruction to designate the sentence or stop the voice signal output; A control task unit for controlling the timing of the sentence utterance and the switching timing of the channel and performing the superposition utterance control of the voice by allocating to each channel, and the driver unit constitutes a sentence
By specifying the addresses of the phrases in order,
The voice synthesis circuit, and the driver
The phrase is read from memory at the specified address
Output each phrase in the order of the above address
It is characterized in that it is stored in memory like a phrase in the past, and the operation sound that was conventionally generated by a device such as an amplifier circuit or a piezoelectric buzzer is separately converted to a normal sentence according to the utterance request Since the operation sound can be switched and uttered, it is not necessary to provide a separate operation sound device as in the related art, and the number of parts can be reduced and the circuit can be reduced.

According to a second aspect of the present invention, in the first aspect of the present invention, the control task section sets one or a plurality of sentences in which the phrases are combined in a sentence table, and sets the sentence table in response to an external request. Setting and deleting a sentence from the table, and upon receiving a request for uttering the set sentence, giving a command to utter the sentence to the driver unit;
The sentence can be freely set in the sentence table by the control task unit without changing the hardware.

According to a third aspect of the present invention, in the first or second aspect of the invention, the driver unit has a function of confirming termination of the output of the audio signal from the audio synthesis circuit, and a function of outputting the audio signal output from the audio synthesis circuit. The control task unit outputs a sound signal output confirmed by the driver unit.
A new sentence after the end of
Output a new sentence after the end of the sentence being output, output a new sentence after the output of any phrase of the sentence being output, or force the sentence being output The sentence can be uttered at various timings, such as when the sentence is stopped and a new sentence is output.

According to a fourth aspect of the present invention, in the third aspect of the present invention, there is provided a buffer for buffering a sentence utterance request for each channel, and the control task unit is adapted to respond to the type of sentence for which the utterance request was made. Determining the timing of processing of the sentence utterance request buffered in the buffer, wherein application tasks and the like for externally requesting a sentence are performed in parallel and another operation is performed even when the sentence is requested. Can be executed, and the processing efficiency can be improved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments. FIG. 1 is a diagram showing a system configuration of the present embodiment. A commercially available general-purpose speech synthesis circuit (IC for speech synthesis) 2 is controlled by an arithmetic processing unit (MPU) 1 and output from the speech synthesis circuit 2. The audio signal is amplified by the amplifier circuit 3 and the speaker 4 is sounded to generate a sentence or an operation sound.

The voice synthesizing circuit 2 is composed of a one-chip LSI having a built-in PROM (not shown) for storing voice data, and includes two channels ch1 and ch2 for voice output.
And a mixing function for two channels ch1 and ch2. The audio data is stored at a predetermined address of the PROM in units of phrases constituting a sentence. Therefore, the voice synthesis circuit 2 converts the phrases into voice signals in the order of the designated addresses and outputs the voice signals in accordance with the instruction given from the arithmetic processing unit 1, whereby the sentence composed of a combination of one or a plurality of phrases is output to the speaker. It is uttered from 4. Also,
In the present embodiment, the operation sound (BEEP sound or the like) is also stored as a phrase in the PROM, and the operation sound is output from the channel ch1, and the other normal phrases (sentences) are output from the channel ch2. The voice synthesizing circuit 2 outputs a BUSY signal indicating whether or not a voice signal is being output and a NAR signal indicating whether or not a command from the arithmetic processing unit 1 can be accepted.

On the other hand, the arithmetic processing unit 1 includes a speech synthesis circuit 2
And a driver section 5 for directly controlling the speech synthesis circuit 2 by giving commands such as a sentence output request and an output stop request. The phrase output request includes a phrase number to be output and channels ch1 and ch1 to be output.
Specify ch2. However, the output itself is output when the driver unit 5 can accept the signal by referring to the NAR signal output from the speech synthesis circuit 2. When the driver unit 5 cannot accept the signal, the driver unit 5 checks the NAR signal by polling and determines that the reception is acceptable. Wait until it becomes. The terminating condition of the phrase output request differs depending on the channels ch1 and ch2 to be output. When the channel ch1 is designated, the operation sound is output, and if the channel ch1 can be output, the operation ends normally. On the other hand, when the channel ch2 is designated, it is necessary to detect a break between individual phrases constituting the sentence. Therefore, after outputting the phrase number (the address of the phrase stored in the PROM), the BUSY It monitors the signal and waits for the output of the audio signal from the audio synthesis circuit 2 to end.

The output stop request is a command for forcibly stopping the phrase currently output by the voice synthesizing circuit 2, and monitors the BUSY signal to determine whether the voice synthesizing circuit 2 is outputting a voice signal. For example, a stop code is output to forcibly stop, and if no output is being performed, the process ends without performing any operation. When this output stop request is given, the sound signal output from the two channels ch1 and ch2 of the sound synthesis circuit 2 is both stopped. The driver unit 5 works in conjunction with the BUSY signal of the voice synthesizing circuit 2 to prevent a noise sound from being generated from the speaker 4 except when the voice signal is being output (for example, to reduce the amplification of the amplifier circuit 3). Is realized by that).

The arithmetic and control unit 1 processes sentence utterance requests from a plurality of application tasks 9 ₁ , 9 _2, ... Executed at the same time and performs a superposition utterance control of an operation sound and a sentence other than the operation sound. The unit 6 includes a sentence table 7 in which a plurality of sentences composed of combinations of phrases stored in the PROM of the speech synthesis circuit 2 are set.

The control task unit 6 sets a sentence consisting of a combination of phrases in the sentence table 7 in response to a sentence setting request from the application task 9 ₁ . FIG. 2 shows a sentence setting instruction format. The first command defines a sentence setting instruction. The end code indicates the processing state of the sentence setting instruction. “0” indicates normal end, and “1” indicates abnormal parameter. The sentence number is a number for specifying a setting location in the sentence table 7, and the output command specifies a command of the voice synthesizing circuit 2 when outputting the setting sentence, for example, a volume control of the amplifier circuit 3, and the like. One or more phrases (phrases stored in the PROM of the speech synthesis circuit 2) constituting the sentence are specified in the output order, and the end of the setting buffer is specified by a terminator. Since this sentence setting request (instruction) is a process only in the control task unit 6, the application task 9 that has issued a request that the process has been completed is requested.
₁ ... will be notified of completion.

On the other hand, FIG. 3 shows an instruction format of setting sentence output from the control task unit 6 to the driver unit 5. The first command defines a sentence output instruction. If the end code is "0", the command ends normally, if "1", it indicates a parameter error, and if "2", it indicates a hardware error. Also, the sentence number set in the sentence table 7 and the channel ch for outputting the sentence
1 and the channel number of ch2. The stop condition is a channel c that outputs a sentence other than the normal operation sound.
This is valid only for h2, and when there is a sentence being output, specifies a stop condition for the set sentence. That is, when "0" is specified as the stop condition, the last phrase of the currently output sentence is switched to a new sentence after output, and when "1" is specified, an arbitrary phrase of the currently output sentence is output and a new phrase is output. When the sentence is switched to the sentence and "128" is designated, the driver unit 5 is controlled so that the sentence currently being output is forcibly stopped and a new sentence is output.
The end of the phrase is detected by the BUS of the speech synthesis circuit 2.
This is performed by monitoring the Y signal with the driver unit 5. Further, the number of outputs is also valid only for channel ch2,
If "0" is specified, the sentence is output infinitely,
When “1” to “255” is designated, the driver unit 5 is controlled so as to output a sentence the designated number of times.

FIG. 4 shows a sentence output stop instruction format. When "0" is specified as a stop condition, the last phrase of the currently output sentence is stopped after output, and "1" is specified. Is stopped after outputting any phrase of the sentence currently being output, and "128"
If specified, it will be forcibly stopped. Incidentally, the processing unit each channel to 1 ch1, buffer ₈₁ for each ch2, 8 ₂ is is provided with, NAR speech synthesis circuit 2
When the signal is incapable of receiving the command, the sentence output command can be buffered, and the channel c can be buffered.
the buffer 8 ₁ for h1 are sentences up to 10 can be buffered. Also, channel ch2
Since only one sentence in the buffer 8 ₂ use is buffered, if a new sentence utterance request is issued buffer is rewritten to the new sentence. Although the completion of processing of the sentence output command if buffered, if the buffer _81, 82 is a buffer full is not a process end until there is room in the buffer _81, 82.

Next, the operation of this embodiment will be described. When there is an utterance request from any of the application tasks 9 ₁ to the control task unit 6, the control task unit 6 refers to the sentence table 7 and issues a sentence output instruction for outputting a sentence of the designated sentence number to the driver unit. Give 5 At this time, if the sentence requested to be uttered is an operation sound, the channel ch1 is specified as a channel to be output. If the sentence is any other normal sentence, the channel ch2 is specified.

Here, when the speech synthesis circuit 2 is outputting, a request to produce a sentence is buffered in the buffers 8 ₁ and 8 ₂ for each of the designated channels ch 1 and ch _2. Provided to part 5. That is, the other sentence is the speech synthesis circuit 2
When a sentence is being output, a new sentence is output after the output sentence ends, a new sentence is output when any phrase of the output sentence ends, or a sentence that is being output is output. It can be specified in three ways, forcibly stopping and outputting a new sentence. For example, when a request to generate an operation sound is issued from any of the application tasks 9 ₁ … while outputting a normal sentence other than the operation sound,
The above three timings can be used properly according to the type of the operation sound. That is, in the case of an operation sound that indicates a warning, it is conceivable to use the operation in which the sentence being output is forcibly stopped and the utterance of the operation sound is prioritized.

According to the present embodiment, the operation sound is set as a sentence in the sentence table 7, and the sentence of the operation sound and the other sentences are set in two channels ch.
1 and 2 and buffered in the buffers 8 ₁ and 8 ₂ and superimposed and uttered at the three timings described above, so that an amplifier circuit or a piezoelectric buzzer is separately provided for the operation sound as in the conventional case. There is no need to provide devices such as the above, and there is an advantage that the number of parts can be reduced and a circuit-saving design can be achieved. The control task unit 6 sets a sentence composed of a plurality of phrases in the sentence table 7 in response to a request from the application task 9 ₁ ... And outputs the sentence for utterance. There is an advantage that setting can be performed freely. Further, since the control task unit 6 distributes the sentence utterance request to the buffers 8 ₁ and 8 ₂ for each of the channels ch1 and ch2, the application tasks 9 ₁ ... Even when a request is made, another operation can be performed, and the efficiency of processing in the arithmetic processing device 1 can be improved.

[0019]

According to the first aspect of the present invention, there is provided a memory for storing a plurality of phrases, and a sentence obtained by combining one or more phrases read from the memory is converted into an audio signal, and the sentence is individually converted from a plurality of channels. A voice synthesizing circuit for outputting, a driver unit for giving an instruction for designating the sentence or stopping the output of the audio signal to the voice synthesizing circuit; distributing a request for sentence utterance to each of the channels; and controls the switching timing and a control task unit that performs superimposition vocal control of voice, the driver unit, congenital
The addresses of the phrases that make up the source
To specify the sentence, and the speech synthesis circuit
From the memory by the above address specified in the
And read each phrase in the order of the above address.
Is converted into an audio signal, so that the operation sound conventionally generated by a device such as an amplifier circuit or a piezoelectric buzzer is stored in the memory in the same way as a phrase, and a normal sentence is prepared according to the utterance request. Since the voice can be generated by switching the sentence of the operation sound, there is no need to provide a separate device for the operation sound as in the related art, and the number of parts can be reduced and the circuit can be reduced.

According to a second aspect of the present invention, the control task section includes:
One or more sentences in which the above phrases are combined are set in a sentence table, and sentence tables are set and deleted in response to an external request. Since the instruction to produce the sentence is given to the driver unit, there is an effect that the sentence can be freely set in the sentence table by the control task unit without changing the hardware.

According to a third aspect of the present invention, the driver section has a function of confirming termination of output of the audio signal from the audio synthesis circuit and a function of stopping the output of the audio signal from the audio synthesis circuit. The control task section is confirmed by the above driver section.
After the end of audio signal output or after the stop of audio signal output
Output a new sentence after the current sentence is completed, output a new sentence after outputting any phrase of the current sentence, or force the current sentence to be output. There is an effect that a sentence can be uttered at various timings such as when the sentence is stopped temporarily and a new sentence is output.

According to a fourth aspect of the present invention, a buffer for buffering a sentence request for each channel is provided for each channel, and the control task unit is buffered in the buffer according to the type of sentence for which the request for speech is made. Since the processing timing of the sentence utterance request is determined, it is possible to execute another task in parallel even when an application task or the like that makes a request for utterance of a sentence from the outside is performed in parallel and at the time of the request for utterance of the sentence. There is an effect that can be improved.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an instruction format of a sentence setting in the above.

FIG. 3 is a diagram showing an instruction format of sentence output in the above.

FIG. 4 is a diagram showing an instruction format of a sentence output stop in the above.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Processing unit 2 Speech synthesis circuit 3 Amplifier circuit 4 Speaker 5 Driver unit 6 Control task unit 7 Sentence table 8 ₁ , 8 ₂ Buffer 9 ₁ … Application task

Continuation of the front page (56) References JP-A-7-20893 (JP, A) JP-A-61-75397 (JP, A) JP-A-2-17091 (JP, A) JP-A-56-161600 (JP) JP-A-4-69699 (JP, A) JP-A-1-267698 (JP, A) JP-A-5-281992 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) G10L 13/04 G10L 13/00

Claims (4)

(57) [Claims] A voice synthesizing circuit having a memory for storing a plurality of phrases, converting a sentence obtained by combining one or more phrases read from the memory into a voice signal, and outputting the voice signal separately from a plurality of channels; For the speech synthesis circuit, the above sentence is specified and the speech signal output
Comprising a driver unit for providing instructions stop, and a control task unit the request sentence uttered by controlling the switching timing of the timing and the channel of the sentence uttered with distributing to each channel performs superposition vocal control of voice, said driver Section is the frame that makes up the sentence.
By specifying the address of the
And the voice synthesis circuit is specified by the driver section.
Read the phrase from memory using the above address
Convert each phrase to audio signal in the order of the above address
A speech superposition and utterance control system characterized by comprising: 2. The control task unit sets one or a plurality of sentences in which the phrases are combined in a sentence table, and sets and deletes sentences in the sentence table in response to an external request. 2. The superimposed utterance control system according to claim 1, wherein when a set utterance request is received, a command for uttering the sentence is given to the driver unit. 3. The driver section has a function of confirming termination of audio signal output from the audio synthesis circuit and a function of stopping audio signal output from the audio synthesis circuit . Audio signal confirmed by the above driver
After the output is completed or the audio signal output is stopped, a new sentence
Voice superimposed utterance control system according to claim 1 or 2, wherein the outputting the scan. 4. A buffer for buffering a sentence request for each sentence for each channel, wherein the control task unit receives the sentence request from the buffer in the buffer according to the type of sentence requested to be sent. 4. The control system according to claim 3, wherein the processing timing is determined.