JP3283319B2 - Processor element and parallel processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing system used in numerical analysis, computer graphics, a database, and the like, and a processor element used in the parallel processing system.

[0002]

2. Description of the Related Art In recent years, the parallel processing system has been able to see the performance limit of a serial type system,
Various researches are being conducted in the industry due to its future potential. In a parallel processing system, communication between a plurality of processors is required, and performing this communication at high speed and without contradiction greatly affects the performance of the entire system.

An example of a conventional parallel processing system will be described below with reference to the drawings.

First, a parallel processing system in which deadlock occurs will be described as a first conventional example. When communication is performed randomly between a plurality of processors, processing may not proceed first due to deadlock.

FIG. 13 is a configuration diagram of a parallel processing system according to a first conventional example. In FIG. 13, 51x, 51
y, 51z are communication devices for controlling data transfer, 54
x, 54y, 54z are buffers for temporarily holding data, 60x, 60y, 60z are memories, 66x, 66
y and 66z are processor elements (hereinafter referred to as PEs) each having communication devices 51x, 51y and 51z and memories 60x, 60y and 60z. Communication device 51x ~
Each of the 51z has three ports, one of the three ports is connected to the memory in the PE to which the communication device belongs, and the other two are connected to the outside of the PE.
Buffers 54x to 54z have a two-stage first-in first-out (FIF
O) The device. For simplicity of description, the number of PEs is three, and the flow of data between PEs is unidirectional.

[0006] There are three types of basic operations of the PE, and "send" which reads data from a memory and sends the data to the outside.
And "relay", in which data input from the outside is temporarily stored in a buffer in the communication device, and then the data is transmitted to the outside again, and "reception", in which the data input from the outside is written in the memory. Is done.

Data x2 and y1, data y2 and z1, data z2 and x1 are stored in buffers 54x, 54y and 54z, respectively. The alphabet of the code of the data indicates the transfer destination.
The data y1 in 4x is finally data to be written to the memory 60y, and the data z1 in the buffer 54y is data to be written to the memory 60z. In the connection form as shown in FIG.
When sending data from E66x to PE66z, use PE6
6y.

Here, it is assumed that each of the buffers 54x to 54z has reached a full state as shown in FIG. The data y1 in the buffer 54x is to be sent to the memory 60y via the buffer 54y, but cannot be sent because the buffer 54y is full. To release the full state of the buffer 54y, the data z1 is stored in the memory 60z via the buffer 54z.
, But the buffer 54z is full.
Similarly, in order to release the full state of the buffer 54z, it is necessary to send the data x1 to the memory 60x via the buffer 54x, but the buffer 54x is in the full state. In order to release the full state of the buffer 54x, it is necessary to send the data y1 to the memory 60y via the buffer 54y. Accordingly, none of the PEs can send data, and the operation stops forever in this state. Such a state is a deadlock.

Next, as a second conventional example, a parallel processing system to which the above-described deadlock avoiding method for avoiding deadlock is applied will be described. FIG. 14 shows a parallel processing system according to a second conventional example, in which (a) is a configuration diagram of a PE of the parallel processing system, and (b) is a configuration diagram of the parallel processing system. For this example, see "1990 Proce
eding of the International Symposium on Computer A
rchtecture P70-P81 ".

In FIG. 14A, reference numeral 71 denotes a communication device for performing data transfer control (original communication Agen).
t), 80 are memory (original Memory Agent: Communication Agen which has the role of interface with external memory)
Since it looks like a memory from t, it is a memory here), and 85 is a processor (Computation Agent
) And 86 are a communication device 71, a memory 80, and a processor 85.
It is PE which has these. As shown in FIG. 14A, the communication device 71 has four ports communicating with the outside of the PE 86 and a PE.
3 connected to memory 80 or processor 85 in
And 20 buffers (not shown) arranged in parallel.

In the above-described parallel processing system using PEs, data transfer is performed after a path through which data flows (hereinafter, referred to as a pathway) is obtained. FIG.
As shown in FIG. 4 (b), 16 PEs are respectively assigned numbers of [0000] to [1111] in binary 4 bits, and six pathways Net1 to Net6 are obtained.

For example, the pathway Net1 is PE [00
00] (transmission)-PE [0100] (relay)-PE [1
000] (transmit, receive, relay)-Connect to PE [1100] (receive). Here, () shows the operation of the PE. When data is transferred using the pathway Net1, for example, the PE [0000] performs only transmission, and the PE [1000] performs transmission, reception, Perform the relay.

In the parallel processing system according to the second conventional example, since a plurality of buffers are arranged in parallel inside the PE, for example, as shown in FIG.
In [0100], two pathways, Net1 and Net2, can be acquired simultaneously, and each pathway can be handled independently in a time-division manner, so that data transfer performed using each pathway can also be executed independently. This can avoid the occurrence of deadlock.

[0014]

As described above, in the parallel processing system according to the first conventional example, there is a problem that any PE cannot send data, that is, a deadlock occurs.

Therefore, as a method for avoiding a deadlock, a plurality of buffers are arranged in parallel in each PE to parallelize a plurality of pathways as in the parallel processing system according to the second conventional example. In some cases, data can be handled independently by division, and a plurality of data transfers are executed independently. Here, since each PE has 20 buffers arranged in parallel, it is possible to acquire 20 channels for the pathway.

However, in the parallel processing system according to the second conventional example, since the upper limit of the number of pathways is determined by the limitation of hardware, when the number of PEs or the amount of communication increases, a process that cannot acquire the pathway occurs. There is a problem in that a process that cannot acquire the information is kept waiting until the pathway is completed. For this reason, the throughput of the entire system decreases, and hardware investment is required to increase the throughput.

The present invention has been made in view of the above, and provides a processor element and a parallel processing system capable of efficiently executing random communication with a small amount of hardware without falling into a deadlock. It is intended for.

[0018]

In order to achieve the above object, the invention of claim 1 is directed to any one of other processor elements.
Data stored in the intermediate data save area of the memory
When the data storage amount exceeds the first predetermined amount,
The transmission of data from the normal area is stopped.

Here, the stop of the transmission of the data is performed by another
From each processor element including the processor element
By the overall transmission stop signal corresponding to the input transmission stop signal
Done.

[0020] Means for solving the problems specifically taken by the invention of claim 1
Is a processor element having a memory and a communication device.
The above memory has a normal area and an intermediate data save area.
And the communication device has a first memory connected to the memory.
Port and a second communicating with the outside of the processor element.
It has a port and a buffer that temporarily holds data,
The communication device updates the data held in the buffer.
Saving intermediate data in the memory through the first port
To be sent to the area.

[0021]Further, the communication device further includes:Note above
The amount of data stored in the intermediate data save area
When the first predetermined amount is exceeded, a transmission stop signal is set and an assertion is made.
The transmitted transmission stop signal is sent to the outside of the processor element.
Transmission stop signal output means for outputting to Middle of the above memory
The storage amount of data stored in the data save area is equal to the first storage amount.
Transmission resumes when the value falls below a second predetermined amount smaller than the predetermined amount.
Set the signal and send the output resume signal asserted
Transmission restart signal output means for outputting to the outside of the sensor element
When,The processor element described above or any other processor
The transmission stop signal asserted by the
Asserted whenThe whole transmission stop signal and,All of
The transmission restart signal asserted from the processor element
Asserted when outputThe entire transmission restart signal
Receiving each,Asserted overall transmission stop signal
Is set and the above-mentioned asserted overall transmission restart signal is asserted.
Send disable signal that generates reset disable signal
Signal generating means, and the processor element
The above-mentioned transmission failure signal generated by the transmission failure signal generation means.
While the issue is asserted,Above buffer or above
Sending data from the intermediate data save area of the memory
Of sending data from the normal area of the memorythe above
Stop sending data from the normal area of memorylike
It is configured.

According to a second aspect of the present invention , when data is transmitted from at least two buffers out of a plurality of buffers to the outside of the processor element through the same port, any one of the buffers may be appropriately used depending on the communication mode. It is possible to select whether to give priority to the data transmission.

Specifically, in the configuration of the first aspect of the present invention , the communication device has a plurality of buffers for temporarily storing data, and the communication device has at least two buffers among the plurality of buffers. When sending data to the outside of the processor element via the second port from the buffer element, a mode in which data is sent in preference to data in a buffer having a relatively large data storage amount, A mode in which data with a relatively long distance to the processor element is transmitted in preference to data stored in the buffer, and data in which the distance from the processor element to the last destination processor element is relatively short are stored. A mode that sends data with priority over the data in the buffer that is It is intended to add a structure to have a delivery mode-selectable.

According to a third aspect of the present invention , when data is transmitted from at least two buffers of a plurality of buffers to the outside of the processor element through the same port, the data received from the intermediate data save area of the memory is stored. The data of the buffer being transmitted is transmitted with the highest priority. Specifically, in the configuration of the invention according to claim 2 , the communication device includes the second buffer from at least two buffers of the plurality of buffers. When sending data to the outside of the processor element through the ports of the above, the buffer data storing the data received through the first port from the intermediate data save area of the memory is sent with the highest priority. It is to be added.

According to a fourth aspect of the present invention , when at least one processor element has a storage amount of data stored in the intermediate data save area of the memory exceeding the first predetermined amount, all the processor elements are stored in the memory. Of the data stored in the intermediate data saving area of the memory of all the processor elements is stopped when all the processor elements are in the normal memory area. The transmission of data from the area is restarted.

A fourth aspect of the present invention is a network for connecting a plurality of processor elements according to any one of the first to third aspects and the plurality of processor elements so as to communicate with each other. The above-mentioned parallel processing system calculates a logical sum of all transmission stop signals output from the communication devices of the plurality of processor elements, and uses the calculation result as an overall transmission stop signal. And a logical sum of all the transmission restart signals output from the communication devices of the plurality of processor elements, and outputs the operation result to the entire transmission restart signal. As a whole transmission restart signal supply means for supplying to all communication devices of the plurality of processor elements as It is an configuration that.

According to a fifth aspect of the present invention , the hardware is reduced by realizing the whole transmission stop signal supply means and the whole transmission restart signal supply means by wired connection . In the configuration of the present invention, the whole transmission stop signal supply means is provided in each of all the communication devices of the plurality of processor elements, and each of the plurality of first MOS transistors or open MOS transistors respectively outputting the transmission stop signal in a negative logic with an open drain. A plurality of first bipolar transistors for outputting a collector and all drains of the plurality of first MOS transistors or all collectors of the plurality of first bipolar transistors are connected to each other and connected to a power supply via a resistor. A first common connection line, and the overall transmission stop signal supply means includes Supply the inverted potential of the potential of the common connection line to all the communication devices of the plurality of processor elements as a whole transmission stop signal, and the whole transmission restart signal supply means supplies all the communication devices of the plurality of processor elements to the communication devices. A plurality of second MOS transistors or a plurality of second bipolar transistors each of which outputs a transmission stop signal in open logic with positive logic or a plurality of second bipolar transistors each of which outputs an open collector, and all drains of the plurality of second MOS transistors or A second common connection line that connects all the collectors of the plurality of second bipolar transistors to each other and is connected to a power supply via a resistor; All communication of the above-mentioned plurality of processor elements is performed using the line potential as the whole transmission restart signal. It is obtained by adding the configuration supplied to the location.

[0028]

The structure of the action] of claim 1 the invention, communication device, Ba
Since the data held in the buffer is sent from the buffer to the intermediate data saving area of the memory through the first port, an empty area can be created in the buffer. As a result, other data in the buffer can be transmitted, the data does not stay at a specific location for a long time, communication efficiency is improved , and transmission from another processor element is performed.
The output data can be received reliably.

Further , the transmission stop signal output means determines that the storage amount of the data stored in the intermediate data save area of the memory is the first.
, A transmission stop signal is output outside the processor element. Any such transmission stop signal
Generated when the processor elements output
The transmission stop signal is generated by the processor
When received from outside the client, the transmission disable signal is set by the entire transmission stop signal. The processor element is
While the transmission disable signal is asserted, the transmission of data from the normal area of the memory is stopped. This allows
The processor element can concentrate on the processing of the data in the buffer and the intermediate data save area of the memory, and can reduce the amount of data stored in the intermediate data save area of the memory. That is, data from the normal area of memory
Of the buffer and memory,
The data in the data save area is free in the buffer as described above.
Transfers and arithmetic processing are performed reliably by creating an area
Is always lost or depleted from the buffer within a finite time.
Since the number is reduced, deadlock can be prevented.

When the storage amount of the data stored in the intermediate data save area of the memory falls below a second predetermined amount smaller than the first predetermined amount, the transmission restart signal output means outputs a processor restart signal to the processor element. Output to the outside of. Such a transmission restart signal is output by all processor elements.
Unreachable transmission of the whole transmission restart signal generated when input
Signal generation means receives from outside the processor element
Then, the transmission disable signal is reset by the whole transmission restart signal, and the transmission of data from the normal area of the memory is restarted. Here, the first and second predetermined amounts are set such that there is no possibility that the data storage amount exceeds the capacity of the intermediate data save area of the memory.

As described above, according to the configuration of the first aspect of the present invention , when there is no more room in the intermediate data save area of the memory, the transmission of new data from the normal area of the memory is stopped, so that the intermediate Since the data storage amount of the data save area can be reduced, the capacity of the intermediate data save area of the memory can be suppressed to a finite amount. As a result, the deadlock can be reliably prevented, and the cost increase due to the needlessly large intermediate data saving area of the memory can be suppressed.

According to the second aspect of the present invention , when data is transmitted from at least two buffers of the plurality of buffers to the outside of the processor element through the second port, communication occurs randomly and deadlock occurs. When there is a high possibility of occurrence or near-field communication, the communication device stores data in a buffer in which data whose distance from the processor element to which the communication device belongs to the last destination processor element is relatively short is stored. When the communication is performed at a higher priority and communication is randomly generated but the possibility of deadlock is low, the communication device determines the relative distance from the processor element to which the communication device belongs to the final destination processor element. Out of the buffer that stores data far from the The communication device sends data with a higher priority than the data in a predetermined buffer when making a decision, and when it is difficult or difficult to predict the data, the communication device gives priority to the data in a buffer with a relatively large data storage amount. It is possible to send it out.

As described above, it is possible to appropriately select from which buffer the transmission of data is prioritized in accordance with the difference in the communication mode, so that the communication efficiency can be greatly improved.

Further, according to the third aspect of the present invention , when transmitting data from at least two of the plurality of buffers to the outside of the processor element through the second port, the communication device can store the intermediate data in the memory. Since the data in the buffer storing the data received from the save area through the first port is transmitted with the highest priority, it is possible to efficiently transmit data that is older in time.

Further, according to the configuration of the fourth aspect of the present invention , the entire transmission stop signal supply means calculates the logical sum of all the transmission stop signals output from the communication devices of the plurality of processor elements, and transmits the operation result as a whole. The supply signal is supplied to all the communication devices of the plurality of processor elements as a stop signal, and the overall transmission resumption signal supply means calculates the logical product of all the transmission resumption signals output from the communication devices of the plurality of processor elements, and performs the operation. The result is supplied to all communication devices of the plurality of processor elements as an entire transmission restart signal.

That is, if there is at least one processor element in which the storage amount of data stored in the intermediate data save area of the memory exceeds the first predetermined amount, all the processor elements can store data from the normal area of the memory. The transmission is stopped, and when the storage amount of the data stored in the intermediate data save area of the memory of all the processor elements falls below the second predetermined amount, all the processor elements stop transmitting the data from the normal area of the memory. Can be resumed.

Therefore, according to the structure of the invention of claim 4 ,
If there is no more room in the intermediate data save area of the memory, stop sending new data from the normal area of the memory,
When there is room in the intermediate data saving area of the memory, transmission of new data from the normal area of the memory can be resumed.

According to the structure of the fifth aspect of the present invention , one processor element is provided with a first common connection line of the whole transmission stop signal supply unit and a second common connection line of the whole transmission restart signal supply unit. It is only necessary to provide four signal lines, and it is not necessary to provide four signal lines for a transmission stop signal, a transmission restart signal, an overall transmission stop signal, and an overall transmission restart signal for one processor element. Wear can be reduced.

[0039]

【Example】

(Processor Element) Hereinafter, a processor element (hereinafter referred to as PE) according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3 and 4. FIG.

FIG. 1 shows a PE 16A according to the first embodiment. In FIG. 1, the PE 16A has a communication device 1A, a memory 10, and a processor (not shown). And an intermediate data save area 11.

FIG. 2 shows the form of the PE 16A. In FIG. 2, 1A is a communication device, 10 is a memory, and 15 is a processor.
There are three types (b) and (c). In any case, the interface on the communication device 1A side is port 2e.
Is used.

In the form (a), the communication device 1A and the memory 1
0 and the processor 15 are commonly connected by a bus 17. The communication device 1A and the processor 15 communicate with each other via a bus 17
And the memory 10 is accessed.

In the form (b), the communication device 1A, the memory 1
0 and the processor 15 are connected in this order. Memory 1
0 has two ports, the communication device 1A and the processor 1
5 access the memory 10 independently of each other.

In the form (c), the communication device 1A, the processor 15, and the memory 10 are connected in this order. Memory 1
0 is under the monitoring of the processor 15, and the communication device 1 </ b> A indirectly accesses the memory 10 via the processor 15.

Although any of the PEs has some advantages and disadvantages, it is not directly related to the effects of the present embodiment. Therefore, in the following description, it is assumed that the PE 16A has the form (a).

FIG. 3 shows the configuration of the communication device 1A of the PE 16A. In FIG. 3, 2a, 2b, 2c, and 2d denote ports serving as second ports leading to the outside of the PE 16A, and 2e denotes a first port. Ports 3a, 3b,
Reference numerals 3c, 3d, and 3e denote selectors for selecting data to be output. Reference numerals 4a, 4b, 4c, 4d, and 4e temporarily store data and buffers 5a, 5b, 5c, 5d, and 5e configured as first-in first-out (FIFO). Is a judging means for monitoring the state of the buffer and generating a full signal FUL when the buffer is full, 6a, 6b, 6c, 6d and 6e are full signal lines for sending the full signal FUL generated by the judging means to the outside of the PE 16A; 7a, 7b, 7c, 7d, 7e are data lines, and 8 is a control means having functions as a transmission stop signal output means, a transmission restart signal output means, and a transmission disable signal generation means. Reference numeral 20 denotes a transmission stop signal line for outputting a transmission stop signal SS set by the control means 8 to the outside of the PE 16A.
S is an entire transmission stop signal line for receiving S, 22 is a transmission restart signal line for outputting a transmission restart signal SR set by the control means 8 to the outside of the PE 16A, and 23 is a control means 8 which receives the entire transmission restart signal ASR. 24 is a transmission disable signal line for the control means 8 to output a transmission disable signal SI set by the asserted overall transmission stop signal and reset by the asserted overall transmission restart signal. .

The communication device 1A has a buffer for each input and a selector of 5 inputs and 1 output for each output. As shown in FIG. 3, the communication device 1A has five ports 2a to 2e and two ports 2a to 2e. To 2e. For example, data flows from port 2a to port 2d as follows.

Port 2a → buffer 4a → selector 3d
→ Port 2d The communication device 1A has buffers 4a to 4d.
e, when data cannot be sent from one buffer to the outside of the PE 16A through the ports 2a to 2d for a predetermined time or longer, the data is transferred from the one buffer to the intermediate data save area 11 of the memory 10 through the port 2e. To send to.

Further, the communication device 1A includes buffers 4a to 4a.
4e, the following four modes are selectable as modes for sending data from the at least two buffers to the outside of the PE 16A through the same port. The first mode is that the data storage amount is relatively small. The mode in which data is sent with a higher priority than the data in the buffer with the largest number is set as the second mode from the PE 16A to the P of the final destination.
A mode in which data with a relatively long distance to E is transmitted in preference to data in a buffer in which data is stored is a third mode in which data with a relatively short distance from the PE 16A to the processor element at the final destination. A mode in which data is transmitted with higher priority than data stored in the buffer is a fourth mode in which data is transmitted with higher priority than data in a predetermined buffer.

Further, the control means 8 of the communication device 1A counts the number of accesses from the port 2e to the intermediate data saving area 11 of the memory 10, and the storage amount of the data stored in the intermediate data saving area 11 of the memory 10 becomes When the transmission stop signal SS exceeds the first predetermined amount, the transmission stop signal SS is set, the asserted transmission stop signal SS is output to the outside of the PE through the transmission stop signal line 20, and the data stored in the intermediate data save area 11 of the memory 10 is output. When the storage amount falls below the second predetermined amount, the transmission restart signal SR is set and the asserted transmission restart signal SR is output to the outside of the PE through the transmission restart signal line 22. Here, the first and second predetermined amounts are set so as to satisfy the first predetermined amount> the second predetermined amount.

FIG. 4 shows a flip-flop 9 which is a part of the control means 8. As shown in FIG. 4, the flip-flop 9 is set by the asserted general transmission stop signal ASS, and is asserted to restart the general transmission. A transmission disable signal SI reset by the signal ASR is generated. While the transmission disable signal SI is asserted, data transmission from the normal area 12 of the memory 10 is not performed.

In the PE 16A according to the first embodiment configured as described above, the communication device 1A
If a state in which data cannot be sent from one of the buffers a to 4e to the outside of the PE 16A through the ports 2a to 2d continues for a predetermined time or more, the data is saved from the one buffer to the intermediate data in the memory 10 through the port 2e. Since the data is sent to the area 11, a free area can be created in the one buffer. As a result, other data in the one buffer can be transmitted, and data does not stay at a specific location for a long time, thereby improving communication efficiency. Further, since data always disappears from the buffer within a finite time, deadlock can be prevented.

In the PE 16A according to the first embodiment, when data is transmitted from at least two of the buffers 4a to 4e to the outside of the PE 16A through the same port, communication occurs randomly. When there is a high possibility that a deadlock will occur or when there are many nearby communications, the communication device 1A gives priority to data in a buffer in which data whose distance from the PE 16A to the final destination PE is relatively short is stored. Sent to
When the communication occurs randomly but the possibility of deadlock is low, the communication device 1A has a higher priority than the data in the buffer in which the data from the PE 16A to the final destination PE is relatively long. When the communication direction is determined statically, the communication device 1A sends out the data in a predetermined buffer with a higher priority than the data in a predetermined buffer. It is possible to send out data in a buffer having a relatively large amount in preference to data in the buffer.

As described above, since it is possible to appropriately select from which buffer the transmission of data is prioritized according to the difference in the communication mode, the communication efficiency can be greatly improved.

Further, in the PE 16A according to the first embodiment, the control means 8 of the communication means 1A determines that the storage amount of the data stored in the intermediate data save area 11 of the memory 10 exceeds the first predetermined amount. Send stop signal SS to PE16A
Output to the outside of. The overall transmission stop signal ASS is generated by such a transmission stop signal SS. If the control means 8 is P
When the whole transmission stop signal ASS is received from outside the E16A, the transmission disable signal SI is set by the whole transmission stop signal ASS. The PE 16A stops transmitting data from the normal area 12 of the memory 10 while the transmission disable signal SI is asserted. Thereby, PE16A
Can concentrate on the processing of data in the buffers 4a to 4e and the intermediate data saving area 11 of the memory 10, and can reduce the amount of data stored in the intermediate data saving area 11 of the memory 10.

When the storage amount of the data stored in the intermediate data save area 11 of the memory 10 falls below a second predetermined amount smaller than the first predetermined amount, the control means 8 sends the transmission restart signal SR to the PE 16A. Output to the outside of. The overall transmission restart signal ASR is generated by such a transmission restart signal SR. When the control means 8 receives the whole transmission restart signal ASR from outside the PE 16A, the whole transmission restart signal ASR
As a result, the transmission disable signal SI is reset, and transmission of data from the normal area 12 of the memory 10 is restarted. In this way, by stopping the transmission of new data from the normal area of the memory when the intermediate data saving area of the memory becomes full, it is possible to reduce the data storage amount of the intermediate data saving area of the memory. Therefore, the capacity of the intermediate data save area of the memory can be suppressed to a finite amount. As a result, it is possible to suppress an increase in cost due to an unnecessarily large intermediate data saving area of the memory.

Hereinafter, the PE according to the second and third embodiments of the present invention will be described with reference to FIGS. 1, 5 and 6 while comparing with the PE 16A according to the first embodiment. Here, a case of three ports will be described for simplification of the drawing. Note that the processor is omitted.

The PE 16A according to the first embodiment shown in FIG.
In, the data read from the memory 10 is first stored in the buffer 4e. The data is sent to the port 2a via the selector 3a, and sent to the port 2d via the selector 3d.

Here, the buffer 4e has a first-in first-out (F
Since the device is an IFO device, data can be transmitted only in the order of storage in the buffer 4e. It is more convenient to send the data in the intermediate data save area 11 of the memory 10 with priority over the data in the buffer 4e that already exists. This is because if the amount of data stored in the intermediate data save area 11 of the memory 10 is large, the transmission of data from the normal area 12 of the memory 10 is stopped, and the data in the intermediate data save area 11 of the memory 10 is stopped. Is old in time.

The PEs according to the second and third embodiments take such points into consideration.

FIG. 5 shows a PE 16B according to the second embodiment, and the same components as those of the PE 16A according to the first embodiment are denoted by the same reference numerals. As shown in FIG. 5, in the communication device 1B, input selectors 13a and 13b are provided on each input side of the buffers 4a and 4d, respectively, and data transmission from the memory 10 is performed as follows. When data is sent from the normal area 12 of the memory 10, the data is temporarily stored in the buffer 4e, and thereafter,
The data is transmitted to the port 2a via the selector 3a, and transmitted to the port 2d via the selector 3d. When data is sent from the intermediate data save area 11 of the memory 10, the data is originally stored in the port 2a.
If the data comes from the port 2d, it is stored in the buffer 4d via the input selector 13b if the data originally came from the port 2d. Thereafter, the data is transmitted to the port 2a via the selector 3a, and is transmitted to the port 2d.
Are transmitted via the selector 3d.

FIG. 6 shows a PE 16C according to the third embodiment, and the same components as those of the PE 16A according to the first embodiment are denoted by the same reference numerals. As shown in FIG. 6, a buffer 14 is provided in the communication device 1C, and data transmission from the memory 10 is performed as follows. When data is sent from the normal area 12 of the memory 10, the data is temporarily stored in the buffer 4e, and thereafter,
The data is transmitted to the port 2a via the selector 3a, and transmitted to the port 2d via the selector 3d. When data is sent from the intermediate data save area 11 of the memory 10, the data is temporarily stored in the buffer 14.
Then, the data is transmitted to the port 2a via the selector 3a, and transmitted to the port 2d via the selector 3d.

As described above, in the PEs 16B and 16C according to the second and third embodiments, the data from the intermediate data save area 11 of the memory 10 can be stored in a buffer other than the buffer 4e. The transmission of data from the intermediate data save area 11 of the buffer 10 is performed by the buffer 4e.
Can be executed prior to the transmission of the data in the data.

(Parallel Processing System) A parallel processing system according to the fourth embodiment of the present invention using the PEs described above will be described with reference to FIGS. 7, 8, 9, 10, and 11. explain. In the following description, the PE may be any of the PEs according to the first, second, and third embodiments. However, unless otherwise specified, the PE 16A according to the first embodiment is used. (A).

First, an outline of a parallel processing system according to the fourth embodiment will be described with reference to FIGS. 7, 8, and 9.

FIG. 7 shows a parallel processing system according to the fourth embodiment. FIG. 7A shows an example of a 4 × 4 crossbar connection, and FIG. 7B shows the PE of the parallel processing system. I have. As shown in FIG. 7, the PE has four ports 2a, 2b, 2c, and 2d to the outside, and numbers [0000] to [1111] are added to each PE. For example, port 2d of PE [0101] and PE [100
1] is connected to port 2a. Also, the PE located at the end will have two or three ports. For example, PE [0000] is the port 2c, 2d of port 2d.
Has two ports.

Communication between PEs in the parallel processing system according to the fourth embodiment is performed as follows. Where P
The data used for communication between Es is as shown in FIG.
FIG. 8A shows a data format of data transferred by the path P1 shown in FIG. 7, and FIG. 8B shows a data format of the data transferred from the horizontal direction part D1, the vertical direction part D2, and the data part D3. The data format of the data transferred by the indicated path P2 is shown.
Such a data format is described in, for example,
No. 4162 ". In short, the horizontal part D1 of the data corresponds to the upper two bits of the number of the destination PE, and the vertical part D2 of the data corresponds to the lower two bits of the number of the destination PE.

In the data transfer on the path P1 shown in FIG. 7, first, the PE [0110] adds [10] to the horizontal part D1 of the data and the vertical part D as shown in FIG.
[01] is added to 2 and the data is transmitted in the vertical direction. Then, since the vertical portion D2 of the data is [01], PE
[0110] sends data to the PE [0101] in which the lower two bits of the PE number are [01] among the PEs on the same vertical line as the PE [0110]. PE [0
101], the horizontal part D1 of the data does not match the upper two bits of the PE number, so that PE [0101] enters the relay operation. Here, the vertical portion D2 of data and PE
Since the lower 2 bits of the number match, communication in the horizontal direction is performed. Since the horizontal portion D1 of the data is [10], the PE [0101] is assigned to the PE [1001] whose upper two bits of the PE number are [10] among the PEs on the same horizontal line as the PE [0101]. Sends data to it. In the PE [1001], the horizontal part D1 of the data matches the upper two bits of the PE number, and the vertical part D2 of the data matches the lower two bits of the PE number. ], The PE [1001] finds itself as the destination, and the PE [1001] captures the data (writes it to the normal area of the memory), and the data transfer ends.

In the data transfer on the path P2 shown in FIG. 7, first, the PE [0110] adds [11] to the horizontal part D1 of the data and the vertical part D as shown in FIG.
[01] is added to 2 and the data is transmitted in the vertical direction. Then, since the vertical portion D2 of the data is [01], PE
[0110] sends data to the PE [0101] in which the lower two bits of the PE number are [01] among the PEs on the same vertical line as the PE [0110]. PE [0
101], the horizontal part D1 of the data does not match the upper two bits of the PE number, so that PE [0101] enters the relay operation. Here, the vertical portion D2 of data and PE
Since the lower 2 bits of the number match, communication in the horizontal direction is performed. Since the horizontal portion D1 of the data is [11], the PE [1101] whose upper two bits of the PE number are [11] among the PEs on the same horizontal line as the PE [0101] is finally obtained. I want to send, but PE [010
1] and PE [1101] are not directly connected,
PE [0101] is the PE [100 on the right side of the same horizontal line.
1]. In PE [1001], since the horizontal portion D1 of the data does not match the upper two bits of the PE number, PE [1001] further relays the data to PE [1101], and PE [1101] Is the horizontal part D1 of the data and the upper two
When the bit matches and the vertical portion D2 of the data matches the lower two bits of the PE number, the PE [110]
1] PE [1101] is found to be the transmission destination
Captures the data, and the data transfer ends.

FIG. 9 is a circuit diagram showing the whole transmission stop signal supply means and the whole transmission restart signal supply means of the parallel processing system according to the fourth embodiment, and is a part of the parallel processing system shown in FIG. This is an excerpt of

In FIG. 9, reference numeral 16A denotes PE, and PE
16A includes a communication device 1A and a memory (not shown) having a normal area and an intermediate data saving area, and the communication device 1A has a control unit 8. 20 is a transmission stop signal S
A transmission stop signal line for S, 21 is an overall transmission stop signal A
Reference numeral 22 denotes a transmission restart signal line for the transmission restart signal SR, reference numeral 22 denotes an entire transmission restart signal line for the transmission restart signal ASR, reference numeral 28 denotes an OR gate, and reference numeral 29 denotes an AND gate. , An OR gate 28, a transmission stop signal line 20, and an entire transmission stop signal line 21 constitute an entire transmission stop signal supply means, and an AND gate 29, a transmission restart signal line 22, and an entire transmission restart signal line 23 constitute an entire transmission restart signal. Supply means is configured.

As shown in FIG. 9, each of the transmission stop signals SS of the PE 16A is input to the OR gate 28 through the transmission stop signal line 20, and the logical sum of all the transmission stop signals SS of the PE 16A is calculated by the OR gate 28. The result is supplied to all PEs 16A through the entire transmission stop signal line 21 as the entire transmission stop signal ASS.
Further, each of the transmission resumption signals SR of the PE 16A is input to the AND gate 29 through the transmission resumption signal line 22, and the logical product of all the transmission resumption signals SR of the PE 16A is calculated by the AND gate 29, and the calculation result is output as the whole transmission resumption signal. The ASR is supplied to all PEs 16A through the entire transmission restart signal line 23.

Next, a data saving operation of the parallel processing system according to the fourth embodiment will be described with reference to FIGS.

In FIGS. 10 and 11, 16x, 16
y and 16z are P similar to those of the PE 16A according to the first embodiment.
E, and the PEs 16x, 16y, and 16z
x, 10y, and 10z and communication devices 1x, 1y, and 1z, respectively, and the memories 10x, 10y, and 10z have normal areas 12x, 12y, and 12z and intermediate data saving areas 11x,
11y, 11z, respectively, and the communication devices 1x, 1
y, 1z are buffers 4x, 4y,
4z, the communication device 1x transmits the data to the buffer 4x when the state in which data cannot be transmitted from the buffer 4x to the outside of the PE 16x continues for a predetermined time or more.
x to the intermediate data save area 11x of the memory 10x. The same applies to the communication devices 1y and 1z.

Here, as shown in FIG.
Data x2, y1, data y2, z in x, 4y, 4z
1, data z2 and x1 are stored, respectively, and PE
It is assumed that data cannot be sent from the buffer to the outside of the PE in each of 16x to 16z. When such a state continues for a predetermined time or more, the buffer 4x,
4y, 4z bottom data y1, z1, x
1 are saved in the intermediate data save areas 11x, 11y, 11z of the memories 10x, 10y, 10z, respectively. FIG. 11 shows a state where the data is saved in the intermediate data saving area of the memory. Thereby, for example, the data x2 in the buffer 4x can be sent to the memory 10x,
x. Similarly, data y2 and z2 in buffers 4y and 4z are stored in normal areas 12 of memories 10y and 10z.
y, 12z. Therefore, the data y1 saved in the intermediate data saving area 11x of the memory 10x can be sent to the normal area 12y of the memory 10y via the buffer 4y, and the data y1 is stored in the normal area 12y of the memory 10y. . Similarly, the data z1 saved in the intermediate data saving area 11y of the memory 10y is stored in the normal area 12z of the memory 10z, and the data x1 saved in the intermediate data saving area 11z of the memory 10z is stored in the normal area of the memory 10x. Area 1
2x, and the data transfer is completed successfully without deadlock.

As described above, according to the parallel processing system according to the fourth embodiment, data does not stay at a specific location for a long time, and random data between PEs is not provided outside the PEs. Communication can be performed efficiently. In addition, deadlock can be prevented because data always disappears from the buffer within a finite time.
Next, a data transmission stop operation and a data transmission restart operation of the parallel processing system according to the fourth embodiment will be described with reference to FIG. As shown in FIG. 9, in each PE 16A,
When the storage amount of the data stored in the intermediate data save area of the memory exceeds the first predetermined amount, the control unit 8 of the communication device 1A
Outputs a transmission stop signal SS from the control means 8 of the communication device 1A when the storage amount of the data stored in the intermediate data save area of the memory falls below the second predetermined amount.
R is output. Therefore, by the connection shown in FIG. 9, if there is at least one PE 16A in which the amount of data stored in the intermediate data save area of the memory exceeds the first predetermined amount, the entire transmission stop signal ASS is asserted. When the storage amount of the data stored in the intermediate data save area of the memory in all PEs 16A falls below the second predetermined amount, the entire transmission restart signal ASR is asserted.

In each PE 16A, the control means 8 generates a transmission disable signal SI which is set by the asserted general transmission stop signal ASS from the OR gate 28 and reset by the asserted general transmission restart signal ASR from the AND gate 29. While the transmission disable signal SI is asserted, new transmission of data (transmission of data from the normal area of the memory) is stopped. Transmission disable signal SI
Is asserted, it is possible to concentrate on sending data in the buffer and in the intermediate data save area of the memory, and since there is no new sending of data, the total amount of data in the parallel processing system is reduced.

Here, the first and second predetermined amounts are set according to the scale of the parallel processing system in consideration of security. That is, the first and second predetermined amounts are set so that there is no possibility that the capacity of the intermediate data save area of the memory will be exceeded. In each of the PEs 16A, the point at which the amount of data that may be relayed by the PE among the data remaining in the parallel processing system is equal to the remaining capacity of the intermediate data saving area of the memory is the border line. Such border lines are predicted in advance, and first and second predetermined amounts are set. The first and second predetermined amounts are set so as to satisfy a first predetermined amount> a second predetermined amount.

As described above, in the parallel processing system according to the fourth embodiment, the transmission of new data from the normal area of the memory is stopped when the intermediate data save area of the memory becomes full, The transmission of new data from the normal area of the memory can be restarted when the intermediate data save area has a margin. When the transmission of data from the normal area of the memory is stopped, the amount of data stored in the intermediate data save area of the memory can be reduced.
The capacity of the intermediate data save area of the memory can be suppressed to a finite amount. As a result, it is possible to suppress an increase in cost due to an unnecessarily large intermediate data saving area of the memory.

Next, the priority of data transmission of the parallel processing system according to the fourth embodiment will be described with reference to FIG. Here, it is assumed that the PE 16B according to the second embodiment is used as the PE of the parallel processing system, which is capable of executing the transmission of the data from the intermediate data save area of the memory with priority. The same applies when the PE 16C according to the third embodiment is used as the PE of the parallel processing system.

As shown in FIG. 5, the PE 16B has three buffers 4a, 4d and 4e. Therefore, there is a case where it is desired to transmit data from a plurality of buffers to the outside of the PE 16B through the same port. At this time, it is necessary to determine which buffer data should be read with priority. The communication device 1B of the PE 16B has the following four modes as a method of assigning a priority when transmitting data. Note that, in any of the following four modes, the port 2
The data in the buffer storing the data received through e is transmitted with the highest priority, and the data in the buffer to be transmitted next with the highest priority is determined according to any of the following four modes.

(1) Data is sent with priority over data in a buffer having a relatively large data storage amount.

(2) P of the final destination from the PE 16B
The data is transmitted with higher priority than the data in the buffer in which data having a relatively long distance to E is stored.

(3) P of the final destination from the PE 16B
The data is transmitted with higher priority than the data in the buffer in which the data whose distance to E is relatively short is stored.

(4) Data is sent out prior to data in a predetermined buffer.

Which of the four modes (1) to (4) is selected depends on the nature of the application to be solved by the parallel processing system. The third mode (3) is selected when communication is randomly generated and the possibility of deadlock is high or when there are many nearby communication, and the communication occurs randomly but the possibility of deadlock is generated. If it is low, the second mode (2) is selected. If the communication direction is statically determined by the application, the fourth mode (4) is selected. Mode (1) is selected.

As described above, according to the parallel processing system of the fourth embodiment, it is possible to appropriately select from which buffer data transmission is prioritized in accordance with the difference in the communication mode. Can be greatly improved. Further, since the data in the buffer storing the data received from the intermediate data save area of the memory is transmitted with the highest priority, the data can be efficiently transmitted from the oldest data.

Hereinafter, a parallel processing system according to a fifth embodiment of the present invention in which hardware reduction is achieved by wired connection will be described with reference to FIG.

FIG. 12 is a circuit diagram showing the whole transmission stop signal supply means and the whole transmission restart signal supply means of the parallel processing system according to the fifth embodiment. In FIG.
Is a PE, the PE 16A has a communication device 1A and a memory (not shown) having a normal area and an intermediate data save area, and the communication device 1A has a control means 8. Also, 2
0 is a transmission stop signal line for the transmission stop signal SS, 21 is an entire transmission stop signal line for the entire transmission stop signal ASS,
22 is a transmission restart signal line for a transmission restart signal SR;
Is a general transmission restart signal line for the general transmission restart signal ASR. Further, 30a and 30b are inverters, 31a
Is a CMOS transistor as a first MOS transistor, and 31b is a CM as a second MOS transistor.
The OS transistor 32a is a first transistor that connects all drains of the CMOS transistor 31a of the PE 16A.
32b is a second common connection line connecting all the drains of the CMOS transistor 31b of PE16A, and 33a and 33b are resistors for pulling up the first and second common connection lines 32a and 32b, respectively. is there.
The transmission stop signal line 20, the whole transmission stop signal line 21, the inverter 30a, the CMOS transistor 31a, the first common connection line 32a, and the resistor 33a constitute a whole transmission stop signal supply means, and the transmission restart signal line 22 and the whole transmission The restart signal line 23, the inverter 30b, the CMOS transistor 31b, the second common connection line 32b, and the resistor 33b constitute an entire transmission restart signal supply unit.

In each PE 16A, the transmission stop signal SS is input to the gate of the CMOS transistor 31a,
The drains of the OS transistors 31a are commonly connected by a first common connection line 32a, and the first common connection line 32a
Is held at a high potential by the resistor 33a. The potential of the first common connection line 32a is equal to the total transmission stop signal ASS.
ASS, which is the inverted signal of the entire transmission stop signal. In each PE 16A, the whole transmission stop inversion signal / AS
S is inverted by the inverter 30a and used as the whole transmission stop signal ASS.

In each PE 16A, the transmission restart signal SR is inverted by the inverter 30b, and the inverted signal is
Input to the gate of the MOS transistor 31b,
The drain of the S transistor 31b is connected to the second common connection line 3
2b, and the second common connection line 32b is held at a high potential by a resistor 33b. Each PE16
At A, the potential of the second common connection line 32b is used as the overall transmission restart signal ASR.

As described above, according to the parallel processing system according to the fifth embodiment, four signal lines required for one PE in the parallel processing system according to the fourth embodiment are connected by wire. With the application, only two are required.

In the parallel processing system according to the fifth embodiment, CMOS transistors are used as transistors of each PE. However, as shown in FIG.
A bipolar transistor may be used as the transistor. When a bipolar transistor is used, the base, collector and emitter of the bipolar transistor correspond to the gate, drain and source of the CMOS transistor, respectively.

As described above, according to the present embodiment, P
According to E and the parallel processing system, random communication between PEs can be executed at high speed with a small amount of hardware without falling into a deadlock. As a result, it is expected that the range of applications in which the parallel processing system can exert its effects is expanded.

In the parallel processing system according to the present embodiment, the connection form of the PEs is a mesh, but the same effect can be obtained in other connection forms such as a ring, a tree, and a hypercube. Obtainable.

[0096]

As described above, according to the processor element of the first aspect of the present invention, the data stored in the buffer is stored.
Tomo was for sending data to the intermediate data save area of the memory from the buffer, enables transmission of other data in the buffer, if it is possible to improve the communication efficiency
The data sent from other processor elements.
You can actually receive it.

When the storage amount of the data stored in the intermediate data saving area of the memory exceeds the first predetermined amount, a transmission stop signal is output and the storage amount of the data stored in the intermediate data saving area of the memory is output. Is smaller than the second predetermined amount, a transmission restart signal is output. And the transmission stop signal
Is output from any of the processor elements.
Is set by the overall delivery stop signal asserted, the
Transmission restart signal is output from all processor elements.
Sending disable signal is reset by the overall delivery resume signal asserted is in while it is asserted, transmission of data from the normal area of the memory is stopped when the. Accordingly, because it is possible to concentrate on the processing of data in the buffer and the intermediate data save area of the memory, the data is time limited
Prevent deadlocks as they will always be out of the buffer in time
Can be stopped. Further, since the amount of data stored in the intermediate data save area of the memory can be reduced, the capacity of the intermediate data save area of the memory can be suppressed to a finite amount. Therefore, it is possible to suppress an increase in cost due to an unnecessarily large intermediate data saving area of the memory.

According to the processor element of the second aspect of the present invention , when data is transmitted from at least two of the plurality of buffers to the outside of the processor element through the second port, depending on the difference in communication mode. Therefore, it is possible to appropriately select from which buffer the transmission of data is prioritized, so that the communication efficiency can be greatly improved. Further, in claim 3
According to the processor element according to the present invention , the data in the buffer storing the data received from the intermediate data save area of the memory is transmitted with the highest priority, so that the data that is older in time can be transmitted more efficiently.

[0099] According to the parallel processing system according to the invention of claim 4, if present processor elements stored amount of data stored in the intermediate data save area of the memory has exceeded a first predetermined amount even one When all the processor elements stop sending data from the normal area of the memory, and when the storage amount of the data stored in the intermediate data save area of the memory of all the processor elements falls below the second predetermined amount, all the processor elements stop sending data. The processor element can resume sending data from the normal area of the memory. Therefore, when there is no more room in the intermediate data saving area of the memory, the transmission of new data from the normal area of the memory is stopped, and when there is room in the intermediate data saving area of the memory, new data from the normal area of the memory is stopped. It is possible to restart transmission of the appropriate data.

According to the parallel processing system of the present invention , it is only necessary to provide two signal lines of the first and second common connection lines, and the hardware can be reduced.

As described above, according to the present invention, it is possible to provide a processor element and a parallel processing system capable of efficiently executing random communication with a small amount of hardware without falling into a deadlock.

The present invention is very useful now that the performance limit of the sequential type system has been revealed and the utilization of the parallel processing system in a wide range of fields is expected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a processor element according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a form of a processor element according to the first embodiment, and FIG. 2A is a block diagram showing a form in which a communication device, a memory, and a processor are connected by a common bus;
(B) is a block diagram showing a form in which a communication device, a memory, and a processor are connected in this order, and (c) is a block diagram showing a form in which a communication device, a processor, and a memory are connected in this order.

FIG. 3 is a block diagram showing a communication device of a processor element according to the first embodiment.

FIG. 4 is a circuit diagram showing a part of control means of the communication device of the processor element according to the first embodiment.

FIG. 5 is a block diagram showing a processor element according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a processor element according to a third embodiment of the present invention.

FIGS. 7A and 7B show a parallel processing system according to a fourth embodiment of the present invention, wherein FIG. 7A is a block diagram showing a form of the parallel processing system, and FIG. 7B shows a processor element of the parallel processing system; FIG.

FIG. 8 shows data of the parallel processing system according to the fourth embodiment, and (a) shows the path P1 of the parallel processing system;
FIG. 4 is a diagram showing a data format of data transferred in
(B) is a diagram showing a data format of data transferred on a path P2 of the parallel processing system.

FIG. 9 is a circuit diagram showing an entire transmission stop signal supply unit and an entire transmission restart signal supply unit of the parallel processing system according to the fourth embodiment.

FIG. 10 is a block diagram showing the operation of the parallel processing system according to the fourth embodiment.

FIG. 11 is a block diagram showing an operation of the parallel processing system according to the fourth embodiment.

FIG. 12 is a circuit diagram showing a parallel processing system according to a fifth embodiment of the present invention.

FIG. 13 is a block diagram showing a parallel processing system according to a first conventional example.

FIG. 14 is a block diagram showing a parallel processing system according to a second conventional example.

[Explanation of symbols]

1A, 1B, 1C, 1x to 1z Communication device 2a to 2d Port (second port) 2e Port (first port) 3a to 3e Selector 4a to 4e, 4x to 4z Buffer 5a to 5e Judging means 6a to 6e Full Signal lines 7a to 7e data lines 8 control means 9 flip-flops 10, 10x to 10z memories 11, 11x to 11z intermediate data saving areas 12, 12x to 12z normal areas 13a, 13b input selectors 14 buffers 15 processors 16A, 16B, 16C, 16x-16z Processor element 17 Bus 20 Transmission stop signal line 21 Overall transmission stop signal line 22 Transmission restart signal line 23 Overall transmission restart signal line 24 Non-transmission signal line 28 OR gate 29 AND gate 30a, 30b Inverter 31a CMOS transistor (first MOS transformer Star) 31b CMOS transistor (second MOS transistor) 32a First common connection line 32b Second common connection line 33a, 33b Resistance ASR whole transmission restart signal ASS whole transmission stop signal SI transmission disable signal SR transmission restart signal SS transmission Stop signal

Claims (5)

(57) [Claims] (1)Processor having a memory and a communication device
In Rement, The memory has a normal area and an intermediate data save area, The communication device has a first port connected to the memory.
A second port leading to the outside of the processor element;
It has a buffer that temporarily holds data, The communication device updates the data held in the buffer.
Saving intermediate data in the memory through the first port
To be sent to The communication device,further,  Of the data stored in the intermediate data save area of the above memory
Set the transmission stop signal when the storage amount exceeds the first predetermined amount
The asserted transmission stop signal is sent to the processor element.
Transmission stop signal output means for outputting to the outside of the  Of the data stored in the intermediate data save area of the above memory
A second predetermined amount whose storage amount is smaller than the first predetermined amount
If it falls below, the transmission restart signal is set and the transmission restart signal
Sending an open signal to output outside the processor element
Restart signal output means;Any of the above processor elements or any other processor
Output stop signal asserted from the element was output
Sometimes asserted The whole transmission stop signal and, All professionals
Transmission restart signal asserted from Sesa element is output
Asserted when you areThe whole transmission restart signal
Receiving,The asserted general transmission stop signal
Reset and the asserted general transmission restart signal
Disable signal that generates reset disable signal
Generating means, wherein the processor element includes the sending disable signal generating means.
The above-mentioned transmission disable signal generated from is asserted
During,Saving intermediate data in the buffer or memory
Sending data from the area and from the normal area of the above memory
Out of the dataFrom the normal area of the above memory
Processor element characterized by stopping data transmission
Ment. 2. The processor element according to claim 1 , wherein said communication device has a plurality of buffers for temporarily holding data, and said communication device transmits said data from at least two buffers of said plurality of buffers. A mode in which, when data is transmitted to the outside of the processor element through the second port, the data is transmitted with a higher priority than data in a buffer having a relatively large data storage amount, and from the processor element to the final destination processor element. A mode in which data is transmitted with higher priority than data in a buffer in which data of a relatively long distance is stored, and a buffer in which data of a relatively short distance from the processor element to the final destination processor element are stored. Mode to send data with priority over the data in Processor elements, characterized in that it has a mode that preferentially delivered selectable. 3. The processor element according to claim 2 , wherein said communication device transmits data from at least two buffers of said plurality of buffers to outside of said processor element through said second port. A processor element for sending data in a buffer storing data received through the first port from an intermediate data saving area of the memory, with the highest priority. 4. A parallel processing system comprising: a plurality of processor elements according to claim 1; and a network connecting the plurality of processor elements so as to be able to communicate with each other. The parallel processing system calculates a logical sum of all transmission stop signals output from the communication devices of the plurality of processor elements, and uses the calculation result as an entire transmission stop signal to all communication devices of the plurality of processor elements. A logical AND of all the supply stop signal supply means to be supplied and all the transmission restart signals output from the communication devices of the plurality of processor elements, and the operation result is used as an entire transmission restart signal for all of the plurality of processor elements. A parallel processing system comprising: an overall transmission restart signal supply unit that supplies the communication device with a transmission restart signal. 5. The parallel processing system according to claim 4 , wherein said overall transmission stop signal supply means is provided in each of all communication devices of said plurality of processor elements, and outputs a transmission stop signal in a negative logic with an open drain output. A plurality of first MOS transistors or a plurality of first bipolar transistors that output an open collector;
A first common connection line that connects all drains of the plurality of first MOS transistors or all collectors of the plurality of first bipolar transistors and is connected to a power supply via a resistor; The overall transmission stop signal supply means supplies an inversion potential of the potential of the first common connection line as an overall transmission stop signal to all communication devices of the plurality of processor elements. A plurality of second MOS transistors or a plurality of second bipolar transistors which are respectively provided in all the communication devices of the plurality of processor elements and output the transmission stop signal in positive logic and open drain output,
A second common connection line that connects all drains of the plurality of second MOS transistors or all collectors of the plurality of second bipolar transistors and is connected to a power supply via a resistor; The parallel processing system according to claim 1, wherein said whole transmission restart signal supply means supplies the potential of said second common connection line as a whole transmission restart signal to all communication devices of said plurality of processor elements.