JP3282609B2 - CMOS integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS integrated circuit formed on an IC chip, and more particularly to a CMOS integrated circuit having a function of detecting occurrence of latch-up.

[0002]

2. Description of the Related Art A conventional CMOS integrated circuit formed as a logic circuit on an IC chip, particularly a CMOS integrated circuit in which a p-type transistor and an n-type transistor are formed on a silicon substrate by junction separation, has a p-type transistor and an n-type transistor. A parasitic bipolar transistor was generated between the transistor and the transistor. This parasitic bipolar transistor is CM
As a result generated in the OS integrated circuit, a circuit equivalent to a thyristor is formed in the CMOS integrated circuit, and the current is intermittently supplied between a power supply terminal and a ground terminal provided in the CMOS integrated circuit, and is called latch-up. A phenomenon was occurring. This phenomenon called latch-up is shown in FIG.
This will be described below with reference to a cross-sectional view of the OS integrated circuit. FIG.
As shown in FIG. 1, a conventional CMOS integrated circuit includes a Pch transistor 10 and an Nch transistor 2 in a silicon substrate.
0 and is formed, N well and P-well in the silicon substrate is formed, on the silicon substrate surface side of the N-well, N ⁺ layer, the P ⁺ layer as the P ⁺ layer and the drain electrode as the source electrode The formed N ⁺ layer and the source electrode 11 were electrically connected to the upper power supply 53. Further, the source electrode 11 and the drain electrode 1 on the silicon substrate
3, a gate electrode 12 is formed by depositing an insulating layer and a metal. On the other hand, in the silicon substrate surface of the P-well, and the N ⁺ layer as the drain electrodes 23 are N ⁺ layer and the P ⁺ layer formed as a source electrode 21, the source electrode 21 and the P ⁺ layer of the P-well is electrically Was connected to the lower power supply. A gate electrode 22 is formed by depositing an insulating layer and a metal between the drain electrode 23 and the source electrode 21 on the surface of the silicon substrate in the P well, and is connected to the input terminal together with the gate electrode 12 in the N well. It was electrically connected. Further, the drain electrode 13 of the N-well and the drain electrode 23 of the P-well were electrically connected to the output terminal. As can be considered from the circuit configuration diagram shown by the dashed line in FIG. 2, an npn transistor 7 is present on the nMOS transistor side and a pnp transistor 7 is present on the pMOS transistor side, and the connection state of both parasitic transistors is equivalent to a thyristor. The phenomenon caused by forming the above circuit is latch-up. In such a phenomenon, as the miniaturization of the IC chip progresses, the area corresponding to the base width becomes narrower, and the characteristics of the parasitic transistor improve. Therefore, the noise voltage and noise current
By entering the S integrated circuit, the function of a thyristor is generated, and a conduction state is established between both parasitic transistors. That is, similarly to the characteristics of the thyristor, the conduction state between the two parasitic transistors is not released unless the voltage of the power supply provided in the CMOS integrated circuit is reduced, and the IC chip may be destroyed via the CMOS integrated circuit. Was.

In order to prevent the destruction of the CMOS integrated circuit due to such latch-up, the occurrence of latch-up itself is prevented, or even if latch-up occurs, the occurrence of such latch-up is detected and the voltage or current of the power supply is reduced. There were two ways to control. In recent years, SOC (System On)
Chips), microcomputer, RA
An IC chip configuration in which various circuit blocks such as an M, a ROM, a high-voltage driver, an analog circuit, and a power supply circuit are mixed is often used. Therefore, even if a configuration is adopted in which a Pch transistor and an Nch transistor to which an input terminal or an output terminal or the like is connected are subjected to a dielectric isolation process as seen in SOI technology to prevent the occurrence of latch-up itself, When a surge is applied to the power supply terminal, a voltage is applied to all circuit blocks in common, so that a Pch transistor and an Nch transistor subjected to a junction separation process in any circuit block on the semiconductor integrated circuit board. However, it was impossible to prevent the occurrence of latch-up itself as long as there existed. Therefore, even when a dielectric isolation process such as SOI is used, a circuit for detecting the occurrence of latch-up is provided indirectly, as in the case of the conventional prevention of latch-up of a CMOS integrated circuit. The only option was to control the voltage and current of the power supply.

[0004]

However, the conventional technology for detecting the occurrence of latch-up in a CMOS integrated circuit has the following problems. For example, JP-A-9
Japanese Patent Application Laid-Open No. -116022 discloses a technique for detecting the occurrence of latch-up by providing a resistor between a MOS integrated circuit and a well contact. However, all circuit blocks in which latch-up using junction separation can occur are disclosed. However, there is a problem in the process of providing a resistor, and an increase in the circuit scale has to be arranged such that a circuit for detecting latch-up must be arranged according to the number of these circuit blocks.

Further, Japanese Patent Application Laid-Open No. 61-67952 discloses a technique which enables detection and control of latch-up by incorporating a circuit for limiting the amount of current into an internal circuit. However, it is necessary to incorporate a resistor between the power supplies of all internal circuits.
In particular, deterioration of circuit characteristics of analog circuits and drivers has become a problem that cannot be ignored. Further, Japanese Patent Application Laid-Open No. 5-199
FIG. 3 is a plan view of a logic circuit device disclosed in Japanese Patent Application Publication No. 10-101. As shown in FIG. 3, also in this logic circuit device, since the current value monitoring circuit sequentially checks the current of the internal circuit, there is no problem if the logic circuit device is a simple logic circuit. It is difficult to detect latch-up by distinguishing the increase from the increase in the circuit current due to the load drive, and the problem of complicated processes in which a detection circuit for adjusting the current detection accuracy must be distributed for each circuit block. Met. That is, in the conventional CMOS integrated circuit for the purpose of detecting when the latch-up occurs, the main focus is on the detection of the latch-up itself, so that it is not enough to apply to an IC chip having a complicated circuit configuration. No effect could be obtained.

The present invention has been made in view of the above-mentioned problems in the prior art, and has a latch-up generating circuit block capable of reliably detecting latch-up without requiring a complicated process. It is an object to provide a CMOS integrated circuit.

[0007]

The CMOS integrated circuit according to the first invention of the present application, which is provided to solve the above-mentioned problems, is:
A latch-up generating circuit block having a lower latch-up tolerance than each circuit block mounted inside the CMOS integrated circuit is provided in a dielectrically separated manner from other circuit blocks;
A latch-up detection circuit connected to an external output terminal or an internal circuit and a latch-up generation circuit block are electrically connected.

A latch-up generating circuit block having a lower latch-up tolerance than each circuit block mounted inside the CMOS integrated circuit is provided in a dielectrically separated manner from other circuit blocks and connected to an external output terminal or an internal circuit. The electrical connection between the latch-up detection circuit and the latch-up generation circuit block eliminates the need to provide a detection circuit in each circuit system even for a semiconductor integrated circuit in which all circuit systems are mixed. Latch-up can be detected, and as a result, destruction of the IC chip can be prevented.

A CMOS integrated circuit according to a second aspect of the present invention, which is provided to solve the above-mentioned problem, has a structure in which a distance between transistors constituting a latch-up generation circuit block is CMO.
The distance between transistors constituting another circuit block mounted inside the S integrated circuit is shorter than the distance between the transistors.

Since the distance between the transistors forming the latch-up generating circuit block is shorter than the distance between the transistors forming the other circuit blocks mounted inside the CMOS integrated circuit, the other latch-up generating circuit block may be used. Latch-up tolerance is lower than that of a circuit block, and latch-up occurring in a CMOS integrated circuit can be detected in advance.

[0011] The present invention is provided to solve the above-mentioned problems .
The CMOS integrated circuit according to the second invention is characterized in that the well of the latch-up generating circuit block is formed shallower than the wells of other circuit blocks formed in the CMOS integrated circuit.

Since the well of the latch-up generation circuit block is formed to be shallower than the wells of other circuit blocks formed in the CMOS integrated circuit, the latch-up generation circuit block is compared with other circuit blocks. Latch-up tolerance is reduced, and latch-up occurring in a CMOS integrated circuit can be detected in advance.

[0013] The present invention is provided to solve the above-mentioned problems .
In the CMOS integrated circuit according to the third invention, the impurity concentration in the well of the latch-up generation circuit block is CMOS.
It is characterized in that the concentration is lower than the impurity concentration in the well of another circuit block formed in the integrated circuit.

Since the impurity concentration in the well of the latch-up generation circuit block is lower than the impurity concentration in the well of another circuit block formed in the CMOS integrated circuit, the latch-up generation circuit block is connected to other circuit blocks. As compared with this, the latch-up tolerance is reduced, and latch-up occurring in the CMOS integrated circuit can be detected in advance.

[0015]

[0016]

[0017]

[0018]

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a CMOS integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a configuration of a CMOS integrated circuit according to an embodiment of the present invention. FIG.
As shown in FIG.
A plurality of circuit blocks such as a low voltage logic circuit block 2, a high voltage logic circuit block 3, and an output driver 4 having a Pch transistor and an Nch transistor formed by a junction separation process are formed on an I substrate 1 by a dielectric separation process. Become. That is, the CMOS according to the present invention
An integrated circuit is a CMO that combines junction isolation and dielectric isolation.
This is performed using an S integrated circuit. One of these circuit blocks is referred to as a latch-up generation circuit block 101, and P
The distance between the channel transistor and the Nch transistor is smaller than the distance between both transistors formed in another circuit block. On the SOI substrate 1, there is provided a latch-up detecting circuit 102 electrically connected to the latch-up generating circuit block 101.
In order to output the detection result obtained by detecting the current, voltage, or temperature inside the circuit, an external control circuit (not shown) or an external terminal (not shown) of the semiconductor integrated circuit is provided. Also electrically connected.

Here, the CMOS integrated circuit according to the present invention has a latch-up generation circuit block 1 on an SOI substrate 1.
01 itself may be separated from the dielectric, or a circuit block disposed around the dielectric may be separated from the dielectric. In addition, the CMOS integrated circuit according to the present invention may be configured such that the depth of the well of the latch-up generation circuit block 101 is set to CMOS so that the latch-up generation circuit block 101 has a lower latch-up tolerance than other circuit blocks.
It may be formed shallower than wells of other circuit blocks formed in the integrated circuit. In addition, the CMOS integrated circuit according to the present invention includes a guard ring, such as a well contact or a sub-contact, provided on the latch-up generation circuit block 101 in order to relatively improve the latch-up tolerance of circuit blocks other than the latch-up generation circuit block 101. It may be formed between transistors in other circuit blocks. Further, in the CMOS integrated circuit according to the present invention, the impurity concentration in the well of the latch-up generation circuit block 101 is set to CM so that the latch-up generation circuit block 101 has a lower latch-up withstand capability than other circuit blocks.
The impurity concentration may be lower than the impurity concentration in the well of another circuit block formed in the OS integrated circuit.

Next, the operation of one embodiment of the CMOS integrated circuit according to the present invention will be described below with reference to FIG. As shown in FIG. 1, in one embodiment of the CMOS integrated circuit according to the present invention, when a surge is applied to a power supply (not shown) of the CMOS integrated circuit, the power supply electrically connects all circuit blocks. , A voltage under the same condition is applied to all circuit blocks. However,
Pch transistor and Nch transistor alone are SOI
Latch-up does not occur because the circuit block separated by the circuit has no parasitic transistor, while the low-voltage circuit block 2 and the latch-up generation circuit block 101 have a structure by junction separation, so that a predetermined size surge Latch-up occurs only when is added.
The latch-up generation circuit block 101 sets the latch-up withstand capability to be weaker than the other circuit blocks, so that before the low-voltage circuit block 2 or the high-voltage circuit block 3 latches up, the latch-up generation circuit block 10
1 itself will cause latch-up. Therefore, when the latch-up occurs in the latch-up generation circuit block 101, the occurrence of the latch-up is detected via the detection circuit.
Appropriate signals are transmitted to the outside of the C chip or to a controller or the like that controls the C chip, thereby preventing destruction of the IC chip.

[0022]

According to the CMOS integrated circuit of the present invention, when a surge or the like is applied to the IC chip from the outside from the power supply, the latch-up generating circuit block installed in the circuit block using the junction separation first latches up. Causes
The occurrence of latch-up can be notified to the outside without impairing the function of the CMOS integrated circuit. Therefore, even in a CMOS integrated circuit in which all kinds of circuit systems are mixed, latch-up can be detected without the trouble of providing a latch-up detection circuit for each circuit, and destruction of an IC chip can be prevented. This has the effect.

[0023]

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a configuration of a conventional CMOS integrated circuit.

FIG. 3 is a plan view showing a configuration of a conventional logic circuit device.

[Explanation of symbols]

 1. IC chip 2. 2. Low voltage logic circuit block 3. High voltage logic circuit block Output driver 5. CMOS integrated circuit 6. SOI substrate 7. Parasitic transistor 10. Pch transistor 11. Source electrode 12. Gate electrode 13. Drain electrode 20. Nch transistor 21. Source electrode 22. Gate electrode 23. Drain electrode 51. Input terminal 52. Output terminal 53. Upper power supply 54. Lower power supply 101. Latch-up generation circuit block 102. Latch-up detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8238 G06F 1/28 H01L 27/092

Claims (3)

(57) [Claims] 1. A CMOS integrated circuit in which each circuit block having a Pch transistor and an Nch transistor formed by junction isolation is formed by dielectric isolation.
A latch-up generating circuit block having a lower latch-up tolerance than each circuit block mounted inside such a CMOS integrated circuit is provided in a dielectrically separated manner from other circuit blocks, and is connected to an external output terminal or an internal circuit. A CMOS integrated circuit, wherein an up detection circuit and a latch up generation circuit block are electrically connected. 2. A claims well depth of the latch-up generation circuit block, characterized in that it is shallower than the well for other circuit blocks formed in the CMOS integrated circuit
Item 2. A CMOS integrated circuit according to item 1. 3. A process according to claim concentration of the impurity in the well of the latch-up generating circuit blocks is equal to or lower than the concentration of the impurity in the well for other circuit blocks formed in the CMOS integrated circuit 1 or claim 2 C described in
MOS integrated circuit