JP3279813B2 - Error detection method for two-wire bus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a local area network (hereinafter referred to as LAN) using a two-wire bus.
The present invention relates to a method for detecting an abnormality of the two-wire bus.

[0002]

2. Description of the Related Art FIG. 2 shows an L bus using a general two-wire bus.
It is a figure showing the example of composition of AN. This LAN has a complementary first bus BUS (+) and a second bus BUS (-), and the first bus BUS (+) is connected to a ground (hereinafter, referred to as GND) via a resistor 1. Connected, second bus BU
S (−) is connected to a power supply (hereinafter referred to as VDD) via the resistor 2.
It is connected to the. On the buses BUS (+) and BUS (-), a plurality of nodes 1 composed of computer devices and the like are provided.
0 ₁ to 10 _n are connected. Input and output terminals of each node, each of the transistors 11 ₁ ~11 _n, 12 ₁ through to 12 _n bus BUS (+), BUS (- ) to be connected, these buses BUS (+), BUS (- ) is adapted to be driven by the transistor _{11 1 ~11 n, 12 1 ~12} n. First and second buses BUS
The signal waveforms of (+) and BUS (-) are inverted waveforms. FIG. 3 is a diagram illustrating a pulse width at 41.6 Kbps of pulse width modulation (PWM) in the SAE (American Society of Automotive Engineers) J1850 communication standard as an example of the communication standard. FIG. 4 is a waveform diagram of the SAE J1850 communication standard. In FIG. 2, a node (for example, 10 ₂ ) turns on a transistor (for example, 11 ₂ ) to turn on a bus BUS
(+) Called dominant state bus states occupying the, all nodes 10 ₁ to 10 _n on the LAN turns off the transistor _{11 1 ~11 n, 12 1 ~12} n to bus BUS (+) , BUS (-) are not occupied by the bus. “SOF” in FIG. 3 is Start
Abbreviation of Of Frame, "EOD" is an abbreviation of End Of Data, "EO
“F” stands for End Of Frame, “IFS” stands for Inter-Frame Se
Abbreviation of paration, "BRK" is an abbreviation of Brake. The pulse widths TP1 to TP6 are TP1 = 24 μs, TP2 = 7 μ
s, TP3 = 15 μs, TP4 = 31 μs, TP5 = 4
8 μs and TP6 = 39 μs.

[0003] In the SAE J1850 communication standard, pulse widths TP1 to TP6 are determined as shown in FIG. Then, only one of the signals in FIG. 3 is output on the buses BUS (+) and BUS (-). For example, FIG.
BUS from node 10 ₁ Bus (+), BUS (-) Consider the case of transferring the data onto. Node 10 _{1 in} FIG.
Then, the transistors 11 ₁ and 12 ₁ are turned on and off, and data is output as “H” → “L” → “H” as shown in FIG. All the nodes 10 ₁ to 10 _n commonly connected to the buses BUS (+) and BUS (−)
The data on S (+) and BUS (-) is received. However, the buses BUS (+) and BUS (-) are short-circuited to VDD (or from the beginning),
When shorted to D, the bus BUS (+), BUS
(-) Becomes "H" or "L", and the data cannot be transferred correctly. Therefore, SAE J
The 1850 communication standard also specifies that an abnormality detection function is provided, and FIG. 5 shows an example of the abnormality detection method.

FIG. 5 is a circuit diagram showing a configuration example of a bus abnormality detection circuit used in a conventional two-wire bus abnormality detection method. This bus abnormality detection circuit is provided with a first bus BUS.
A change detection circuit 21 for detecting a change from the passive state to the dominant state (+) and a change from the dominant state to the passive state, and a change from the passive state to the dominant state and the dominant state of the second bus BUS (-). And a change detection circuit 22 for detecting a change from a passive state to a passive state. The output terminal of one change detection circuit 21 is connected to the clock terminal CK of one counter 31 and the reset terminal R of the other counter 32. The output terminal of the other change detection circuit 22 is connected to one counter 31
, And the clock terminal CK of the other counter 32. A carry terminal CA of one counter 31 outputs a BUS (-) abnormality detection signal S31, and a carry terminal CA of the other counter 32 outputs a BUS (+) abnormality detection signal S32. FIGS. 6A to 6C are operation waveform diagrams of the bus abnormality detection circuit shown in FIG. 5, and a conventional two-wire bus abnormality detection method will be described with reference to FIG. FIG.
As shown in (a), after the bus idle, the process proceeds to the communication start. At the start of communication, bus BUS (+), BU
While both S (-) are changing, the counter 3 in FIG.
1 and 32 are reset by the outputs of the respective change detection circuits 21 and 22. Therefore, the counters 31, 32
No signal is output from carry terminal CA of bus BUS
(+), BUS (-) abnormality is not detected.

As shown in FIGS. 6B and 6C, the bus B
Abnormal to US (+) (for example, short to VDD, GN
When a short circuit to D occurs, the change detection circuit 22 detects a change in only the bus BUS (−) and resets one counter 31. However, bus B
Since US (+) does not change, the counter 32 is not reset, and a carry signal, that is, a BUS (+) abnormality detection signal S32 is output from the carry terminal CA by the counting operation of the counter 32, and abnormality is detected. Similarly, when an abnormality occurs in the bus BUS (−), the counter 31
BUS (-) abnormality detection signal S31 from the carry terminal CA
Is output, and an abnormality of the bus BUS (−) is detected. When such a bus error detection result is obtained, for example, appropriate switching to a normal line can be performed. That is, LA in FIG.
N uses a two-wire bus and the two buses BUS
Since the inverted signals are transmitted to (+) and BUS (-), respectively, for example, when an abnormality is detected in one bus BUS (+) by the bus abnormality detection circuit in FIG.
The line is disconnected by means not shown, and the other bus BU
Communication can be continued only with S (-). Such a function of switching to a normal line is called a fault-tolerant function, and is required, for example, in automobile LAN equipment. In the fault tolerant function, communication can be continued even under a fault under a certain condition. The J1850 communication standard also requires an abnormality detection function and a fault-tolerant function.

[0006]

However, the conventional abnormality detection method has the following problems (1) to (4). (1) The conventional abnormality detection method using the bus abnormality detection circuit shown in FIG. 5 only detects which of the two buses BUS (+) or BUS (-) has an abnormality. It is not possible to detect whether an error has occurred. That is, it is impossible to detect whether the bus BUS (+) or BUS (-) is short-circuited to VDD, short-circuited to GND, or opened (disconnected). If you do not know the details of the problem, it is difficult to find the cause of the trouble, and no countermeasures can be taken. Therefore, it takes time to restore the network, such as replacing an abnormal bus line or a connector. (2) In the conventional abnormality detection method, even when the state of the buses BUS (+) and BUS (-) changes due to external noise or the like, the abnormality of the buses BUS (+) and BUS (-) is detected. There is a problem. (3) When both the buses BUS (+) and BUS (-) are in a passive state (that is, the bus idle state), and one of the lines has a failure that changes from passive to dominant (for example, BUS (+) If it is, a VDD short-circuit occurs, and if BUS (-), a GND short-circuit occurs), which cannot be detected by the conventional abnormality detection method. FIG. 7 is a circuit diagram showing a configuration example of a conventional signal switching circuit using the bus abnormality detection circuit of FIG. 8 and 9 are operation waveform diagrams of FIG. The signal switching circuit of FIG. 7 includes a bus abnormality detection circuit 33 of FIG. 5 and two voltage dividing resistors 3 for generating a reference voltage.
4, 35, three differential comparators 36, 37, 38,
And a selector 39. And bus BUS
(+), BUS (-) line status
3, the selector 39 selects one of the output signals S36, S37, S38 of the three differential comparators 36, 37, 38 based on the detection result and outputs the selected signal as the output signal OUT. Has become. Bus BU
When both S (+) and BUS (-) are normal, output signal S3
7, when the bus BUS (+) is abnormal, the output signal S38;
When the bus BUS (-) is abnormal, the output signal S36 is used.

In the conventional abnormality detection method, the selector 3 is normally operated based on the detection result of the bus abnormality detection circuit 33 shown in FIG.
9 is selected and one of the output signals S36, S37, S38 of the differential comparators 36, 37, 38 is selected and output. As shown in FIG. 8, when an abnormality occurs in one of the buses, communication can be continued if the output signal S37 → the output signal S36 and the output signal S37 → the output signal S38 can be appropriately switched. However, in the conventional method,
In the bus idle state, even if a dominant short circuit occurs on one bus, it cannot be detected at that time. As a result, as shown in FIG. 9, the differential comparators 36, 37,
38, both the (+) and (-) input terminals become "H", and the output signal OUT, which is the output signal S37, becomes OUT1, OUT
2, OUT3 is fixed at "L" (or unstable), and communication cannot be continued. As described above, in the conventional abnormality detection method, the differential comparators 36, 37, 3
8 cannot be switched properly, and there is a problem that communication cannot be continued despite the occurrence of an abnormality in only one side line.

(4) As described above, the conventional abnormality detection method cannot detect the types of abnormalities that have occurred in the buses BUS (+) and BUS (-). Difficult for any reason. FIG.
(D) is a waveform diagram showing an example of detecting a bus error content.
As shown in FIG. 10A, after the bus idle, the first bus BUS (+) changes from the passive state to the dominant state, but this rises from "L" to "H" due to a short circuit to VDD. It is unclear at this stage whether the communication has started or whether it has really started communication. Further, in the second bus BUS (−), even after the end of the bus idle, the passive state of “H” which is the same as the level of the bus idle is fixed. It is unknown at this stage whether this is a VDD short or no communication state.

As a first case, at the start of communication shown in FIG. 10A, the first bus BUS (+)
Let us consider a case as shown in FIG. In this case, the first bus BUS (+) is normal, and the second bus BUS (-)
However, there is a high possibility of a VDD short. As a second case, at the start of communication in FIG. 10A, the first bus BUS (+) is set to J1850 as shown in FIG. 10C.
Let us consider a case where “H” continues even if the maximum dominant time of the communication standard exceeds 39 μs. In this case, it is determined that the VDD short-circuit has occurred on the first bus BUS (+). That is, in the J1850 communication standard, as shown in FIG. 3, the break signal “BRK” has the longest dominant time. In this break signal, the pulse width T
Since P6 = 39 μs and the waveform should be as shown in FIG. 10D, the state of FIG. 10C is determined to be a VDD short circuit trouble on the first bus BUS (+) side. As described above, there are some types of abnormal contents that can be immediately detected, and those that are not. Therefore, it is difficult to accurately determine the abnormal contents of the bus. The present invention has a problem that the prior art has a problem that it is difficult to accurately detect even the type of abnormality that has occurred in the bus,
It is another object of the present invention to provide a two-wire bus abnormality detection method which solves the problem of erroneous detection of a bus abnormality due to noise.

[0010]

In the present invention, there is provided a means for solving], in order to solve the above problems, feeding two-wire bus having a plurality of nodes are configured on the connected complementary first and second bus having a receiving function In the two-wire bus abnormality detection method for detecting the occurrence of an abnormality, a communication standard comparison process, a noise removal process, a bus state comparison process, and a bus abnormality determination process are executed. Here, in the communication standard matching process, the occupation state time of the first and second buses is compared with the communication standard by a counting operation, and the occupation state time exceeds the maximum occupation state time specified in the communication standard. Is detected. In the noise elimination process, the presence or absence of noise is detected based on whether or not the occupation state of the first and second buses continues for a predetermined time or more by a counting operation. Pass the signal. In the bus state comparison processing, based on the result of the communication standard comparison processing, a signal is latched when the state of the first and second buses changes, and the states of the first and second buses are compared. . Thereafter, in the bus abnormality determination processing, based on the noise removal processing result, the results of the bus state comparison processing when the states of the first and second buses change are latched, and the first and second buses are latched. Determine the abnormal state.

[0011]

According to the present invention, the occupation state time of the first and second buses (that is, the time of the dominant state) is compared with the communication standard (for example, the J1850 standard or the like) by the communication standard comparison processing, and the dominant state of the first and second buses is compared. Whether or not the state time exceeds the maximum occupancy state time (that is, the maximum dominant state time) specified in the communication standard is detected, and the detection result is sent to the bus state comparison processing. In addition, the noise removal processing detects the presence or absence of noise based on whether or not the dominant state of the first and second buses continues for a predetermined time or more. Only when there is no noise, the signal on the first and second buses is detected. Is sent to the bus abnormality determination processing. In the bus state comparison processing, signals are latched when the states of the first and second buses change, the states of the first and second buses are compared, and the comparison result is sent to the bus abnormality determination processing. Then, in the bus abnormality determination processing, the results of the bus state comparison processing when the states of the first and second buses change are latched, and the abnormal states of the first and second buses are determined. Is output. Therefore, the above problem can be solved.

[0012]

FIG. 1 is a circuit diagram of a bus abnormality detection circuit used in a two-wire bus abnormality detection method according to an embodiment of the present invention. This bus abnormality detection circuit is, for example, a circuit for detecting abnormality of the first and second buses BUS (+) and BUS (-) in the LAN in FIG. 2 and is connected to the first bus BUS (+). An input terminal 41, an input terminal 42 connected to the second bus BUS (-), and a clock input terminal 43 for inputting a clock signal CLK supplied from the outside are provided. Inverters 44 and 45 for signal inversion are connected to the input terminals 41 and 42, respectively, and a bus state comparison circuit 50 for performing bus state comparison processing is connected to the input terminals 41 and 42 and the output terminals of the inverters 44 and 45. Is connected. Also, the input terminal 41 and the inverter 45
Are connected to a communication standard matching circuit 60 for performing a communication standard matching process based on a clock signal CLK and a noise removing circuit 70 for performing a noise removing process based on the clock signal CLK. Are connected to the input terminals of the bus state comparison circuit 50. The output terminals of the bus state comparison circuit 50 and the noise removal circuit 70 are connected to a bus abnormality determination circuit 80 that performs a bus abnormality determination process. The bus state comparison circuit 50 includes data flip-flops (hereinafter, referred to as D-FFs) 51, 52, 53, 54 that latch signals on the first and second buses BUS (+), BUS (-), and D-FF51,
Two-input AND gate 5 for controlling the reset input of 52
5, 56 and 2-input OR gates 57 and 58 are provided. Each of the D-FFs 51 to 54 has an input terminal D for inputting data, a clock terminal CK, a reset terminal R, and an output terminal Q for outputting data.
The set terminals S are provided in the FFs 53 and 54, respectively. Each of the D-FFs 51 to 54 is a circuit that samples input data of the input terminal D according to a signal input to the clock terminal CK and outputs the sampled data from the output terminal Q. The input terminal D of the D-FF 51 is connected to the output terminal of the inverter 44, the clock terminal CK is connected to the output terminal of the inverter 45, the input terminal D of the D-FF 52 is connected to the input terminal 42, and the clock terminal CK is connected to the input terminal 42. Input terminal 41
The input terminal D of the D-FF 53 is the input terminal 41, the clock terminal CK is the input terminal 42, the input terminal D of the D-FF 54 is the output terminal of the inverter 45, and the clock terminal CK
Are connected to the output terminals of the inverter 44, respectively.

A bus comparison result is output from an output terminal Q of each of the D-FFs 51 to 54 and sent to the bus abnormality determination circuit 80. Output terminal Q of D-FF51
Is connected to the input terminal of the AND gate 55 together with the output terminal of the communication standard matching circuit 60, and the output terminal and the input terminal 41 of the AND gate 55 are connected to the reset terminal R of the D-FF 51 via the OR gate 57. Have been. AN
The output terminal of the D gate 55 is connected to the set terminal S of the D-FF 54. The output terminal Q of the D-FF 52 is connected to the output terminal of the communication standard matching circuit 60 and the AND gate 56.
The output terminal of the AND gate 56 and the output terminal of the inverter 45 are connected to the reset terminal R of the D-FF 52 via the OR gate 58. The output terminal of the AND gate 56 is connected to the set terminal S of the D-FF 53. The reset terminal R of the D-FF 53 is connected to the output terminal of the inverter 44, and the reset terminal R of the D-FF 54 is connected to the input terminal 42. The communication standard matching circuit 60 uses the clock signal C
This is a circuit for inputting LK and outputting the result of comparison to the bus state comparison circuit 50. A 2-input OR gate 61, 2-input AND
A gate 62 and an up counter 63 are provided. O
The input terminal of the R gate 61 is connected to the input terminal 41 and the output terminal of the inverter 45, and the output terminal of the OR gate 61 and the clock input terminal 43 are connected to the input terminal of the AND gate 62. The output terminal of the AND gate 62 is connected to the clock terminal CK of the up counter 63, and the carry terminal CA of the up counter 63 is connected to the input terminals of the AND gates 55 and 56 in the bus state comparison circuit 50.

The noise removal circuit 70 is provided with a clock signal CL
This is a circuit for inputting K and outputting a signal from the buses BUS (+) and BUS (-) from which noise has been removed to the bus abnormality determination circuit 80. The input two-input AND gates 71 and 72, the up counter 73, and Two input AND gates 74 and 75 are provided. The inverting input terminal of the AND gate 71 is connected to the clock input terminal 43 and the carry terminal CA of the up counter 73, and the output terminal of the AND gate 71 is connected to the clock terminal CK of the up counter 73. The inverting input terminal of the AND gate 72 is connected to the input terminal 41.
The output terminal of the AND gate 72 is connected to the reset terminal R of the up counter 73 and the reset terminal R of the up counter 63. The carry terminal CA of the up counter 73 is connected to the input terminals of the AND gates 74 and 75, together with the input terminal 41 and the output terminal of the inverter 45. The output terminals of the AND gates 74 and 75 are connected to the bus abnormality determination circuit 80. Connected to input terminal. The bus abnormality determination circuit 80 includes D-FFs 81 to 84 whose input terminals D for data input are respectively connected to output terminals Q of the D-FFs 51 to 54 in the bus state comparison circuit 50, and an output of the D-FF 81. GND on bus BUS (+) connected to terminal Q
Output terminal 85 for outputting short-circuit abnormality detection signal PG
And a bus BUS connected to the output terminal Q of the D-FF
An output terminal 86 for outputting a VDD short-circuit abnormality detection signal NV at (−), an output terminal 87 connected to the output terminal Q of the D-FF 83 and outputting a VDD short-circuit abnormality detection signal PV at the bus BUS (+). , The D-FF
An output terminal 88 connected to the output terminal Q 84 and outputting a GND short detection signal NG on the bus BUS (−).
And it is comprised. The clock terminals CK of the D-FFs 81 and 83 are connected to the output terminal of the AND gate 75, and the clock terminals CK of the D-FFs 82 and 84 are connected to the output terminal of the AND gate 74. The set terminal S of the D-FF 83 is connected to the output terminal of the AND gate 56, and the set terminal S of the D-FF 84 is connected to the output terminal of the AND gate 55.

Next, the abnormality detection methods (1) to (6) of the two-wire bus of the present embodiment using the bus abnormality detection circuit of FIG. 1 configured as described above will be described with reference to FIGS. It will be explained while doing. (1) Passive state fixed detection of bus BUS (+) (B
FIG. 11 is a waveform diagram showing a method for detecting the passive state fixation of the first bus BUS (+) using the bus abnormality detection circuit of FIG. 1. It is. When the second bus BUS (-) changes from the passive state to the dominant state, the inverted signal of the first bus BUS (+) is latched by the D-FF 51. That is, the first
GND short or BUS on bus BUS (+)
The (+) side driver is opened and the bus BUS
If (+) does not change from the passive state to the dominant state, the D-FF 51 is set and its output terminal Q
Becomes “H”. At this time, the output terminals Q of the other D-FFs 52 to 54 are all at "L", and the carry terminal CA of the up counter 63 also remains at "L". Noise removal circuit 7
At 0, the first and second buses BUS (+), BUS (-)
If either of them is in the dominant state, the up counter 73 counts up. If the dominant state continues for a certain period or more, it is determined that the noise is not noise, and a carry signal is output from the carry terminal CA. Then, the AND gates 74 and 75 are activated, and the first and second buses BUS (+) and BUS (-) are sent to the bus abnormality determination circuit 80.
Signal input is permitted. In the D-FF 81 in the bus abnormality determination circuit 80, the D-FF 51 changes from the dominant state of the second bus BUS (-) to the passive state.
Is latched at the output terminal Q. That is, D-
Since the FF 51 is set, the first bus BUS
An abnormality that (+) is fixed in a passive state (short to GND) is detected, and an abnormality detection signal PG output from the output terminal 85 is set to “H”. As described above, when the abnormality detection signal PG becomes “H”, the first bus BUS (+)
Detect passive state fixation of

(2) Passive state fixation detection of bus BUS (-) (VDD short or open detection of BUS (-)) FIG. 12 shows the second bus BUS (-) using the bus abnormality detection circuit of FIG. Fixed passive state detection or BUS
It is a waveform diagram which shows the open detection method of the (-) side driver. When the first bus BUS (+) changes from the passive state to the dominant state, the state of the second bus BUS (-) is latched by the D-FF 52. That is, the second bus B
A VDD short occurs at US (-) and the bus BUS
If (-) does not change from the passive state to the dominant state, the D-FF 52 is set and its output terminal Q
Becomes “H”. At this time, the other D-FFs 51, 53, 5
4 are all "L" and the up counter 6
The carry terminal CA of No. 3 also remains at “L”. The first and second buses BUS (+), BU
It is determined that the signal on S (−) is not noise, and the first and second buses BUS (+) and B
US (-) signal input is permitted. In the D-FF 82 in the bus abnormality determination circuit 80, the D-FF 82 changes from the dominant state to the passive state of the first bus BUS (+).
The output of the output terminal Q in the FF 52 is latched. That is, since the D-FF 52 is set, the D-FF 8 is set.
2, the second bus BUS (-) is fixed in the passive state (V
(Short to DD) is detected, and the abnormality detection signal NV output from the output terminal 86 is set to “H”. Thus, the abnormality detection signal N output from the D-FF 82
When V becomes “H”, the passive state fixation of the second bus BUS (−) is detected.

(3) Fixed detection of dominant state of bus BUS (+) (VDD short detection of BUS (+)) FIG. 13 shows a bus BUS using the bus abnormality detection circuit of FIG.
It is a wave form diagram which shows the dominant state fixed detection method of (+). The D-FF 53 is connected to the first bus B when the second bus BUS (−) changes from the dominant state to the passive state.
Latch the state of US (+). That is, the first bus BU
A VDD short occurs at S (+) and the bus BUS
If (+) does not change from the dominant state to the passive state, the D-FF 53 is set and its output terminal Q
Becomes “H”. At this time, the other D-FFs 51, 52, 5
4 are all "L" and the up counter 6
The carry terminal CA of No. 3 also remains at “L”. By the noise removing circuit 70, the first and second buses BUS (+), BU
It is determined that the signal on S (−) is not noise, and the first and second buses BUS (+) and B
US (-) signal input is permitted. In the D-FF 83 in the bus abnormality determination circuit 80, the D-FF 83 changes its state from the passive state to the dominant state of the second bus BUS (-).
The output of the output terminal Q in the FF 53 is latched. That is, the D-FF 83 detects an abnormality that the first bus BUS (+) is fixed in the dominant state (short to VDD), and outputs an abnormality from the output terminal 87 to the abnormality detection circuit PV.
To “H”. As described above, when the abnormality detection signal PV becomes “H”, the dominant state fixing of the first bus BUS (+) is detected.

(4) Dominant state fixed detection of bus BUS (-) (GND short detection of BUS (-)) FIG. 14 shows a bus BUS using the bus abnormality detection circuit of FIG.
It is a waveform diagram which shows the dominant state fixed detection method of (-). The D-FF 54 latches an inverted signal of the second bus BUS (−) when the first bus BUS (+) changes from the dominant state to the passive state. That is, a GND short occurs in the second bus BUS (-), and
When S (-) does not change from the dominant state to the passive state, the D-FF 54 is set, and its output terminal Q becomes "H". At this time, the output terminals Q of the other D-FFs 51 to 53 are all “L”, and the carry terminal CA of the up counter 63 also remains “L”. The first and second buses BUS (+), BUS
If it is determined that the signal on (−) is not noise, the first and second buses BUS (+),
BUS (-) signal input is permitted. In the D-FF 84 in the bus abnormality determination circuit 80, the first bus BUS (+)
Changes from the passive state to the dominant state,
-Latch the output of the output terminal Q in the FF54. That is, the D-FF 84 detects an abnormality that the second bus BUS (-) is fixed in the dominant state (short circuit to GND), and outputs the abnormality detection signal N output from the output terminal 88.
G is set to "H". Thus, when the abnormality detection signal NG becomes “H”, the dominant state of the second bus BUS (−) is detected to be fixed.

(5) Fixed detection of dominant state of bus BUS (+) (VDD short detection of BUS (+)) FIG. 15 shows the dominant state of the first bus BUS (+) using the bus abnormality detection circuit of FIG. It is a waveform diagram which shows a state fixed detection method. First and second buses BUS (+), BUS
(-) When both are in the passive state, the bus BUS
When (+) is short-circuited to VDD and changes to the dominant state (when BUS (+) is short-circuited to VDD when not communicating), the D-FF 52 is set and the dominant of the bus BUS (+) actually generated. The operation shifts to an operation in which the second bus BUS (−) different from the state fixation detection is in the passive state fixation. At this time, the other D-FFs 51 and 5
All the output terminals Q of 3, 54 remain "L". However, in this case, the abnormality detection signal NV is output when the first bus BUS (+) changes from the dominant state to the passive state. Therefore, the first bus BU
If S (+) is fixed in the dominant state, this abnormality is not output. When the time of the dominant state exceeds the maximum dominant state time defined in the communication standard (for example, J1850), a carry signal is output from the carry terminal CA of the up counter 63, and the D-FF is output.
52 is reset, and D-FFs 53 and 83 are set. The D-FF 83 allows the first bus BUS (+)
Is fixed in the dominant state, and the abnormality detection signal PV becomes “H”. As described above, when the abnormality detection signal PV becomes “H”, the first bus BUS
The (+) dominant fixed state is detected.

(6) Dominant state fixation detection of bus BUS (-) (GND short detection of BUS (-)) FIG. 16 shows the dominant state of the second bus BUS (-) using the bus abnormality detection circuit of FIG. It is a waveform diagram which shows a state fixed detection method. First and second buses BUS (+), BUS
(-) When both are in the passive state, the bus BUS
When (-) is short-circuited to GND and changes to the dominant state (when BUS (-) is short-circuited to GND when not communicating), the D-FF 51 is set and its output terminal Q becomes "H". . At this time, other D-FFs 52 ~
All the output terminals Q of 54 remain "L". However, when the time exceeds the maximum dominant state time of the communication standard (for example, J1850), the D-FF 51 is reset,
D-FFs 54 and 84 are set and the second bus BUS
An abnormality that the dominant state is fixed (-) is detected, and the abnormality detection signal NG becomes “H”. Thus, when the abnormality detection signal NG becomes “H”, the second bus BU
The dominant state fixation of S (-) is detected. As described above, in the present embodiment, the first and second buses BUS (+), B
When the state of US (-) changes, the bus BUS
Since the states of (+) and BUS (-) are compared by the bus state comparison circuit 50, it is possible to accurately detect the types of abnormalities of the buses BUS (+) and BUS (-). The conventional abnormality detection method only detects which of the first and second buses BUS (+) and BUS (-) has an abnormality. Therefore, it has been difficult to find the cause of communication failure. In the embodiment, even the details of the abnormality can be accurately detected. For example, the first bus BUS
If it is found that (+) is short-circuited to GND, it is easy to take measures such as replacing the bus BUS (+) or short-circuiting between shielded cables. In addition, bus BU
The communication is appropriately switched to communication using only S (-). In this way, the ability to detect abnormal contents accurately and at high speed makes it easier to find out the cause of the trouble, enables the network to be restored in a short period of time, and switches the communication line appropriately so that communication can be continued without interruption. Can be expected.
In addition, in this embodiment, since external noise and the like are removed by the noise removing circuit 70, erroneous detection of the external noise and the like can be appropriately prevented.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (A) In the abnormality detection method using the bus abnormality detection circuit of FIG. 1, the communication standard collation circuit 60 and the noise elimination circuit 70 perform collation processing and noise elimination processing by a count operation using the up counters 63 and 73, Further, in the bus state comparison circuit 50 and the bus abnormality determination circuit 80, the comparison processing and the abnormality determination processing are performed by the latch operation using the D-FFs 51 to 54 and 81 to 84. It is also possible to detect an abnormality of the two-wire bus by using. For example, in the communication standard matching circuit 60 of FIG. 1, the first and second buses BUS (+), B
The signal on the US (-) is compared with the communication standard, and the noise removal circuit 70 outputs a signal from which the noise on the buses BUS (+) and BUS (-) has been removed. Then, the first and second buses BUS (+), BUS are determined by the bus state comparison circuit 50 on the basis of the result of the communication standard comparison processing.
Compare the state of (-). Then, the bus abnormality determination circuit 8
0, based on the output of the noise removal processing, the first and second buses BUS
An abnormal state of (+) and BUS (-) is determined. Even if a two-wire bus abnormality detection method is configured by using the bus abnormality detection circuit having such a circuit configuration, substantially the same operation and effect as in the above embodiment can be obtained. (B) As another circuit configuration example of the above (a), for example, the D-FFs 51 to 54 and 81 to 84 are replaced with other flip-flops or latch circuits, or the up counter 6
It is conceivable to replace 3,73 with another counting means such as a down counter. When the abnormality detection of the two-wire bus is performed using such a bus abnormality detection circuit, there is an advantage that the abnormality can be easily and easily detected with a relatively simple circuit configuration. In addition, a central processing unit (hereinafter referred to as CPU) capable of operating at high speed
And the first and second buses BUS (+), BU
If it is detected on S (-) whether or not a pulse specified by the communication standard is generated by a software method using a program, there is an advantage that the circuit configuration can be further simplified. (C) In the above embodiment, the abnormality detection method of the two-wire bus in the LAN has been described. However, the abnormality detection method of the present invention can be applied to a two-wire bus other than the LAN.

[0022]

As described above in detail, according to the present invention, in the communication standard collation processing, whether the occupation state time of the first and second buses exceeds the maximum occupation state time specified in the communication standard. No, and based on the detection result,
In the bus state comparison processing, signals are latched when the states of the first and second buses change, and the states of the first and second buses are compared with each other. When the state of the first and second buses changes, the result of the bus state comparison processing is latched to determine the abnormality. Therefore, it is possible to more easily and accurately detect even the type of abnormality of the bus. Moreover, in the noise removal processing, the presence / absence of noise is detected by whether or not the occupation state of the first and second buses continues for a predetermined time or more by the counting operation, so that the noise can be removed easily and accurately. . In addition, even when a one-sided line dominant short trouble occurs during a bus idle, an abnormal line can be accurately determined. For example, by applying the circuit to a receiver input selection circuit, communication can be continued and a LAN that requires high reliability is required. The system is particularly effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a bus abnormality detection circuit used in a two-wire bus abnormality detection method according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a general configuration example of a LAN.

FIG. 3 is a diagram showing a pulse width of the SAE J1850 communication standard.

FIG. 4 is a waveform diagram of the SAE J1850 communication standard.

5 is a circuit diagram showing a configuration example of a conventional bus abnormality detection circuit used in the LAN of FIG. 2;

6 is an operation waveform diagram showing a conventional two-wire bus abnormality detection method using the bus abnormality detection circuit of FIG. 5;

7 is a circuit diagram of a conventional signal switching circuit using the bus abnormality detection circuit of FIG.

FIG. 8 is an operation waveform diagram of the signal switching circuit of FIG. 7;

FIG. 9 is an operation waveform diagram of the signal switching circuit of FIG. 7;

FIG. 10 is a waveform diagram showing a conventional example of detecting a bus error content.

FIG. 11 shows a bus BUS using the bus abnormality detection circuit of FIG. 1;
It is a waveform diagram which shows the passive state fixation detection method of (+).

FIG. 12 shows a bus BUS using the bus abnormality detection circuit of FIG. 1;
It is a waveform diagram which shows the passive state fixation detection method of (-).

FIG. 13 shows a bus BUS using the bus abnormality detection circuit of FIG. 1;
It is a wave form diagram which shows the dominant state fixed detection method of (+).

14 shows a bus BUS using the bus abnormality detection circuit of FIG. 1;
It is a waveform diagram which shows the dominant state fixed detection method of (-).

FIG. 15 shows a bus BUS using the bus abnormality detection circuit of FIG. 1;
It is a wave form diagram which shows the dominant state fixed detection method of (+).

FIG. 16 shows a bus BUS using the bus abnormality detection circuit of FIG. 1;
It is a waveform diagram which shows the dominant state fixed detection method of (-).

[Explanation of symbols]

 Reference Signs List 50 bus state comparison circuit 51-54, 81-84 D-FF 60 communication standard verification circuit 63, 73 up counter 70 noise removal circuit 80 bus abnormality determination circuit BUS (+), BUS (-) first and second bus CLK Clock signal NG, NV, PG, PV abnormality detection signal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-75629 (JP, A) JP-A-7-154394 (JP, A) JP-A-64-12633 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) H04L 12/40

Claims (1)

(57) [Claims] 1. A plurality of nodes having a transmission / reception function are connected.
And a two-wire bus comprising complementary first and second buses.
For detecting abnormalities in two-wire buses that detect the occurrence of abnormalities in buses
The occupancy of the first and second buses by a counting operation.
State time against the communication standard, and the occupation state time
The maximum occupancy state time specified in the
The occupation state of the first and second buses is determined by a communication standard comparison process to be detected and a count operation.
Detects the presence or absence of noise based on whether the state continues for a certain period of time or more
And the signals on the first and second buses only when there is no noise.
Based on the result of the communication standard collation processing and the noise removal processing
The signal is latched when the bus state changes,
Bus state comparison processing for comparing the states of the first and second buses
If, on the basis of the noise removal processing result, the first and second
The bus state comparison processing result when the bus state changes
To determine the abnormal state of the first and second buses.
And performing a bus abnormality determination process to determine the abnormality of the two-wire bus.