JP3278852B2 - Communication control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control method and a communication method.
It relates to a control device.

[0002]

2. Description of the Related Art When a computer communicates with another computer or a terminal device, the computer is connected to a network transmission line via a communication control device. In this case, the data transmission and reception performed between the computer and the communication control device include, for example, a service request (for example, a data transmission request) from the computer to the communication control device, and an end from the communication control device to the computer in response to the service request. There are a report, an event report (for example, a data reception report) from the communication control device to the computer, and a reception notification from the computer to the communication control device for the event report.

When a computer transmits data, the computer writes transmission data in a transmission buffer area previously allocated on a main memory and issues a transmission request to a communication control device. Upon receiving this data transmission request, the communication control device reads out the transmission data from the main memory, performs a protocol process such as creating a header, and sends it out to the transmission path. On the other hand, when receiving data from the transmission path, the communication control device writes the received data on a reception buffer allocated in advance on the main memory, and issues an event report to the computer indicating that the data has been received. .

Reading of transmission data from the main memory and writing of reception data to the main memory are performed by a direct memory access controller (DMAC).

[0005] In addition, the data transmission request and the event report include, for example, a control data block (hereinafter, referred to as a control block) including a write address of transmission / reception data, a data length, and a command code. This is performed in a format in which the address is written to the area and the address of the control block is notified to the other party (computer or communication control device).

The data communication system between the main computers is described, for example, in Japanese Patent Application Laid-Open No. 63-266948.

[0007]

According to the conventional data transmission / reception system, however, the management of the above-mentioned buffer area for transmission / reception data provided on the main memory and the management of the write area of the control block are performed on the computer side. Have been done. For example, when the communication control device writes the received data to the reception buffer on the main memory, the computer notifies the communication control device of the empty reception buffer and the control block writing area each time, and after receiving this notification, The communication control device starts the write operation of the received data.

That is, conventionally, the communication control apparatus cannot unilaterally report an event, and the communication overhead for notifying the reception buffer area and the control block area is generated. Could not do it fast.

[0009]

In order to achieve the above object, a data transmission / reception system of the present invention allocates a transmission buffer area and a reception buffer area on a main memory, and a main computer stores transmission data in the transmission buffer area. writing,
The communication control device packetizes the transmission data read from the transmission buffer area and sends it out to the communication path, and the communication control device writes the data included in the packet received from the communication path into the reception buffer area, and writes the data into the reception buffer area. In the communication system processed by the computer,
The management of the free area of the transmission buffer on the main memory is performed by the main computer, and the management of the free area of the reception buffer on the main memory is performed by the communication control device.

[0010] For example, a memory capacity capable of forming a reception buffer for a plurality of connections is allocated to the reception buffer area of the main memory, and this is notified to the communication control device in advance.

The communication control device includes, for example, a management table means for storing parameters for controlling data writing to the reception buffer area in connection with the connection. When a packet is received from the communication path, the communication control device refers to the management table based on the connection identifier included in the received packet, and stores the reception data extracted from the received packet in the reception buffer corresponding to the connection identifier. By writing the received data in the area subsequent to the already received data storage area, the received data divided into a plurality of packets and sent is reassembled on the main memory.

[0012] Further, each time the reassembly of data transmitted in a state of being divided into a plurality of packets or data transmitted as a single packet is terminated,
The communication control device notifies the main computer of data reception.

The notification of the data reception is performed, for example, by writing a control information block including a code indicating the data reception, the length of the received data, and the write address of the data in the main memory. In this case, the communication control device informs the main computer of the write address of each control information block on the main memory, the main computer reads the control information block based on the address, and further writes the control information block included in the control information block. The received data may be accessed based on the address.

[0014] The communication control device may read and write data to and from the main memory as described above.
An operation (protocol processing) of creating a header for transmission data or analyzing a header attached to reception data is performed. These operations may be performed by one processor, but a plurality of processors may be used to speed up processing.

For example, the communication control device is composed of first and second processors, the first processor transmits and receives data to and from the main memory, and the second processor performs protocol processing, thereby performing processing. Speed can be increased.

[0016]

According to the present invention, the transmission buffer area on the main memory is managed by the main computer, and the reception buffer area is managed by the communication control device. The reception buffer for writing data can be independently determined by the communication control device.
Further, useless communication between the computer and the communication control device is eliminated, and the speed of reception processing can be particularly increased.

[0017]

(Embodiment 1) A first embodiment of the present invention is shown in FIG.
Will be described with reference to FIG.

FIG. 2 shows a configuration example of a data communication system to which the present invention is applied. This system includes a plurality of computers 1 (1A to 1C), and each computer is connected to a network transmission line 5 via a communication control device 4 (4A to 4C).

FIG. 1 is a block diagram showing details of the computer 1 and the communication control device 4.

The computer 1 comprises a main processor 10 and a main memory 11, and is connected to the communication control device 4 via the computer system bus 2.

The communication control device 4 includes the local processor 2
5, a local memory 24, a communication control circuit 26 connected to the network transmission path 5, and a direct memory
It comprises an access controller (DMAC) 20 and a local bus 23 connecting them, and a bus interface 2 is provided between the system bus 2 and the local bus 23.
1, a first FIFO 22T used for transmitting control information from the computer 1 to the communication control device 4, and a second FIFO 22R used for transmitting control information in the opposite direction. The DMAC 20 allows the local memory 24
When performing data transfer between the information exchange area 12 and the
Control signals and address signals issued from C20 to the computer-side bus arbiter 3 and the main memory 11 are transmitted via the local bus 23, the bus interface 21, and the computer system bus 2 in the same manner as the data path.

The communication control circuit 26 is a modem 29 for transmitting and receiving signals to and from the network transmission line 5.
And a DMAC connected between the local bus 23 and the MODEM 29.

In order to avoid contention for bus use by a plurality of processors or DMACs, the system bus 2
And the local bus 23 are provided with bus arbiters 3 and 5, respectively.

FIG. 3 shows a configuration example of a hierarchical communication protocol applied to the inter-computer communication of FIG. The communication protocol is from the lower layer, physical layer L1, MAC layer L2, L
The communication controller 4 includes an LC layer L2 ', a network layer L3, a transport layer L4, a session layer L5, a presentation layer L6, and an application layer L7. The communication control device 4 performs communication protocol processing for the transport layer L4 and lower. In the following embodiment, class 4 (TP
4) The connection type protocol (CLNP) is applied to the network layer L3, and LLC type 1 is applied to the LLC layer L2 '.

FIG. 4 is a diagram showing a basic configuration of software executed by the local processor 25. The software executed by the local processor 25 is an interface processing unit 1 that performs an interface process with the computer 1.
00, a communication protocol processing unit 200 that processes a header of a communication frame, and a communication control circuit driver unit 300 that performs an interface process with the communication control circuit 26. The communication protocol processing unit 200 corresponds to the layers L4 to L2 of the hierarchical communication protocol shown in FIG.
It comprises a C processing 230 and a MAC processing unit 240.

FIG. 5 shows transmission data DAT handled by the computer 1.
4 shows a relationship between A and a packet 30 transmitted to the transmission path 5. The transmission data DATA includes a plurality of data blocks B1.
.. Bn (segmentation) and sent out on the transmission path as a plurality of packets 30-1 to 30-n.
Each packet 30 includes a header section 31, a data section 32 including the data block, a synchronization bit 33 located at the head of the packet, and a frame check sequence (FCS) section located at the end of the packet.

In this specification, when one message or transmission data is divided into a plurality of blocks and transmitted as described above, the packet 30-1 including the first data block B1 is divided into a first packet (FIRST), The packet 30-n including the packet Bn including the last data block Bn is the last packet (LAST), and the packet including the intermediate data blocks B2 to Bn-1 is the next packet (N
EXT). When the transmission data is shorter than the fixed length, one transmission data as a whole is transmitted as one packet. This packet is converted into a single packet (SI
NGLE).

FIG. 6 shows details of the packet format. The header section 31 includes a MAC header 35, an LLC header 36, a CLNP header 37, and a TP4 header 38. The MAC header 35 includes a destination address (DA) 35A and a source address (S
A) It includes 35B and data length 35C. Also, T
The P4 header section 38 has a header length 38A and a DT code 3
8B, the other party's reference 38C, and the sequence number 3
8D and EOT bit 38E.

The EOT bit 38E is set to "1" for a single packet and the last packet, and "0" for other (next packet).

FIG. 7 is a diagram for explaining the outline of the data transmission / reception operation performed between the computer 1 and the communication control device 4.

The information exchange area 12 on the main memory includes an area 41T for storing transmission data to be transmitted from the computer 1 to the communication partner device, an area 41R for storing reception data from the partner device, and a computer 41. An area 40T for storing a control block for notifying the communication control device 4 of the service request content from the communication control device 1 and an area 41R for storing a control block for notifying the computer 1 of the event report content from the communication control device 4 Consists of

Each of the transmission data area 41T and the reception data area 41R has a plurality of buffer areas (transmission buffer areas 41T1 to 41Tm and reception buffer areas 41R1 to 41Rn) corresponding to connections, respectively. , Each having a memory capacity capable of storing a plurality of control blocks.

In the present specification, the information is stored in an information exchange area on the main memory to distinguish it from a control block (for example, 50T, 50R) for a communication control device stored in a local memory 24 described later. This control block is called a “main control block”, and the control block stored in the local memory is called a “local control block”. When data is transmitted from a computer to a certain device, the computer 1
Writes the transmission data in the empty transmission buffer area 41Ti, generates a main control block 40Ti including an address indicating the head position of the transmission buffer area as a pointer address, writes this in the memory area 40T, and writes the main control block 40Ti to the main control block. An address Ai indicating the head of 40Ti is set in the first FIFO 22T. As shown in FIG. 8, the main control block 40Ti includes a command code 400, a connection ID 402, and a destination address 40 in addition to the pointer address 406 of the transmission data.
4, and the length 408 of the transmission data.

The communication control device 4 includes the first FIFO 22
The addresses set in T are sequentially taken out, the main memory 11 is accessed based on this address, and the contents of the main control block 40Ti are read. Command code 40
When 0 indicates a data transmission request, the head address of the buffer area including the data to be transmitted is written in the pointer address 406.

The communication controller 4 gives the pointer address 406 and the data length 408 to the DMAC, and stores the transmission data in the transmission buffer area 247Tj on the local memory.
To make a DMA transfer. These operations for accessing the main memory are performed by the interface processing unit 100 shown in FIG. When the transmission data is read into the transmission buffer area on the local memory, the interface processing unit 100 divides the transmission data into a plurality of data blocks, and the communication protocol processing unit 200 transmits each data block according to the contents of the main control block. To the header 31.
The destination address 404 of the main control block contains N of the destination device.
The SAP address is specified, and the NSAP address itself is set in a part of the CLNP header 37, and the NSAP address
The MAC address as a part is set in the MAC header 35. Also, the connection ID 402 of the main control block
Is the connection ID (counterpart reference) 38C of the counterpart notified from the counterpart device when the connection is established.
Is set in the header part in the form converted to. When the header processing is completed, the communication control circuit driver unit 300 delivers each packet to the communication control circuit 26.

When the DMA transfer is completed, the communication control device 4 sets the start address Ai of the main control block 40Ti corresponding to the transmission buffer 41Ti to the second FIFO to notify the computer 1 of the release of the transmission buffer 41Ti.
Set to O22R. The FIFO 22R is for setting an address of an event report from the communication control device 4 to the computer 1, mainly for setting an address of a main control block for notifying reception of data. The computer 1 sequentially extracts addresses from the FIFO, and To access the main control block based on When the address Ai is extracted from the FIFO 22T and the main control block 40Ti is accessed, the computer can determine from the contents of the main control block that the transmission data buffer 41Ti has been released. These buffer areas 41Ti to 4Ti for data transmission
The computer 1 manages the 1Tm and the empty / busy state of the main control blocks 40Ti to 40Tm using a management table provided on a main memory (not shown).

Next, an operation of reporting an event from the communication control device 4 to the computer 1 will be described. One feature of the present invention is that the communication control device manages an area on a main memory used for storing a main control block for event reporting and received data. A region 40R for writing a plurality of main control blocks for event reporting and a reception data region 41R are allocated in the main memory by the computer 1 in advance, and are notified to the communication control device 4. The communication control device 4 receives the data from the transmission line 5 while managing the empty / busy state of these areas 40R and 41R by using the control block management table 245 and the reception processing management table 246 provided on the local memory 24 shown in FIG. The data and the main control block generated by the communication control device are written into the main memory. The reception data area 41R is composed of a plurality of reception buffer areas 41R1 to 41Rm. These reception buffers are assigned one by one corresponding to the connection, and the reception buffer is used to convert the reception packet for each connection to the original data (message). Is carried out.

When a received packet from the transmission line 5 is input to the local memory 24 via the communication control circuit 26, the local processor 25 can identify the connection by the reference 38C of the received packet. Also,
The local processor stores the state of the reassembly operation corresponding to the connection, and determines the type of the received packet from the state identifier (hereinafter, simply referred to as status) and the EOT bit 38E included in the received packet. (SINGLE, FIRST, NEXT, LAS
T) can be determined. For example, the status is "1" when a message or original data is being reassembled, and "0" otherwise. In this case, if the status is "0" and the EOT bit of the received packet is "0", the FIRST and EOT bits are "1".
If the status is "1" and the EOT bit is "0", the status is NEXT. If the EOT bit is "1", the status is LAST.

When the packet is received and the header processing is completed, the data unit 32 of the received packet is written by the interface unit 100 into the reception buffer 40Ri corresponding to the connection of the received packet. If the type of the received packet is FIRST or NEXT, no notification is made to the computer, and SINGLE or LAS is not sent.
When the packet of T is received, following the writing of the data in the receiving buffer, a main control block for notifying the reception of data is written in the empty area of the memory area 40R, and the head address Bi of this main control block is set to the second address. FIFO
22R is set.

The computer reads the main control block and the received data (message) based on the address extracted from the second FIFO 22R. Before the reception data is read by the computer, a packet constituting another message may be received on the same connection in some cases. In this case, if there is a free space in the reception buffer, the data block is written. If there is no free space, this data block is temporarily stored in the reception buffer on the local memory side. In order to manage the reception buffer described above, in the present invention, for example, a reception processing management table 246 shown in FIG. 9 is used.

As shown in FIG. 9, the reception processing management table 246 stores a plurality of parameters corresponding to connection IDs. Of these parameters, S / E
Indicates a start address and an end address of the reception buffer 41Ri assigned to one connection, PR indicates a start address of a write data (message) start area in the reception buffer 41Ri, and PW indicates a reception data area. Indicates a write pointer indicating the start address of the free area existing subsequently.
"Status" indicates whether the reception buffer 41Ri is in the middle of a reassembly operation for one message, or is in a state before reassembly is completed or before the start. BP is a block pointer indicating the start address of the message for which the reassembly operation has been completed, and LEN indicates the length of the message. Of these parameters, BP and LEN are the address pointer and data length in the main control block.

The operation of writing the reception data block into the reception buffer area 41Ri and the reception processing table 24
The relationship with the parameter value in 6 will be described below with reference to FIG.

Now, assuming that the first data block has been received for one connection, the parameters PR and PW have initial values, that is, the buffer area 4
It points to the start address Bi of 1Ri.

Assuming that the received data block is a FIRST packet, the parameter LE indicating the message length
Zero value of N, and the value of the PW to the parameter BP to indicate the beginning of the message is set, the received data block (P1) is stored in the memory area of length L _0, which starts from the address indicated by the parameter PW Is done. Upon completion of writing of one data block, the values of PW and LEN is increased by a value corresponding to each data block length L _0.

NEXT packets P ₂ -P ₄ and LAS
Even upon receipt of T packet P _5, similar to the above, data is written to the buffer memory in accordance with the parameter PW, the parameter PW and LE at each end of write
The value of N is updated. However, in the case of the LAST packet,
At the end of the data writing, a main control block including the values of the parameters BP and LEN is generated, and is written in the main control block area for reception on the main memory.

The completion of the reception process of the LAST packet, i.e. after reassembling operation is completed for one message M1, early in the following the FIRST packet P ₆ is received, BP and the values of LEN and the PW are zero Therefore, the same reassembling operation as described above can be executed.

After the computer completes reading the message data, the value of the parameter PR is set to the next message M
2 is updated to the value of the address indicating the reading start point.
Last address position Bl of one buffer area 41Ri
When data is written up to -1, the subsequent data is written to a free area starting from the head of the buffer area 41Ri. The communication control device checks the relationship between the value of the write pointer PW and the value of the read pointer PR for each buffer memory area.
In the case of overtaking R, it is determined that there is no free area, writing of the received data of the channel to the main memory is stopped, and the received data is temporarily stored in the buffer area on the local memory until a free area is created. store.

FIG. 11 shows the configuration of the local memory 24. In the figure, 241P is an interface processing program area, 242P is a communication protocol processing program area, and 243P is a communication control circuit driver program area. These programs correspond to the interface processing unit 100 and the communication protocol processing unit 20 shown in FIG.
0, corresponding to the communication control circuit driver unit 300. 244
Is a communication protocol processing area used during communication protocol processing, 245 is a main control block management table area for managing the event report main control block area 40Rn on the main memory, and 246 is a reception buffer area 41Rn on the main memory. This is a reception processing table area for management. 247T is a local transmission buffer area having a transmission data storage capacity, and 247R is a local reception buffer area having a reception data storage capacity, each having a memory capacity capable of storing a plurality of transmission or reception data (messages). 248T and 24
8R is a management table for managing the local transmission buffer and the local reception buffer (247T, 247R), respectively. Reference numeral 249 denotes an area for storing a local control block 50 used for executing communication protocol processing in the communication control device 4;
0 is a local control block management table area for managing the local control block area 249.

FIG. 1 shows the configuration of the local control block.
It is shown in FIG. The local control block 50 includes a command code 500 indicating a data (message) transmission request, a data (message) reception report, a release request, etc., a connection ID 502 for identifying a TP4 connection, and a MAC address DA (MAC) 504 indicating a transmission destination. And a transmission or reception buffer (247) in the local memory.
T, 247R), the length 508 of the transmitted or received data, and the data bit 509.
And

FIG. 13 shows a communication protocol processing area 2
44 shows the configuration of FIG.

The communication protocol processing request pool 440 and the communication protocol processing end pool correspond to the interface processing unit 100 and the communication protocol processing unit 200 in FIG.
This is an area for storing the address of the local control block exchanged with the local control block. The communication control circuit driver transmission pool 444T and the communication control circuit driver reception pool 444R store addresses of local control blocks exchanged between the communication protocol processing unit 200 and the communication control circuit driver unit 300 in FIG. It is an area to keep.

In the figure, 440 is the interface processing unit 10
0 is completed, and an area (communication protocol processing request pool) for storing an address of a local control block paired with a transmission buffer to be processed next by the communication protocol processing unit 444T is communication protocol processing Area for storing the address of the local control block paired with the transmission buffer to be processed next by the communication control circuit driver unit (communication control circuit driver transmission pool). Area for storing the address of a local control block that is read from the communication control circuit 26 by the circuit driver unit and that is to be processed next by the communication protocol processing unit (communication control circuit driver reception pool) , 442
Is an area for storing the address of the local control block paired with the receiving buffer to be transferred to the main memory by the interface processing unit after the processing by the communication protocol processing unit is completed (communication protocol processing end pool) It is. Reference numeral 446 denotes a table area for managing a TP4 connection, and stores a reference sequence number and an EOT bit for each connection.

FIG. 14 is a flowchart of a program for communication control, which is executed by the local processor.

In the communication control, a routine (transmission sub) 60T for performing data transmission (service request) and a routine (reception sub) 70T for performing data reception (event report) are alternately executed.

FIG. 15 is a flowchart showing the contents of the transmission sub60T. The transmission sub60T includes a routine 62T for performing an interface process with the computer 1;
It comprises a communication protocol processing routine 64T and a communication control circuit driver processing routine 66T.

The above interface processing routine 62T
Then, as shown in FIG. 16, first, the address of the main control block 40 is read from the transmission direction FIFO (620).
Next, the command code 400 of the main control block indicates a data transmission request, and the transmission data (BN) is the maximum data length (4 KB) that can be transmitted on the network transmission path.
If so, a local control block 50 is generated (621). Furthermore, a code (data bit = 1) indicating the end of division of transmission data is added to the command code 500.
09 is set (622).

Next, the DMAC 20 is instructed to read the transmission buffer from the main memory to the local memory (6).
23). The address of the transmission buffer area on the main memory is specified by the pointer address of the main control block.

When the read operation of the transmission buffer by the DMAC 20 is completed, the pointer address of the transmission buffer area in the local memory is set in the field 506 of the local control block 50, and the address of the local control block is set to the local control block for communication protocol processing. It is registered in the request pool 440 (624). Next, the command code 40 of the main control block 40T is sent to the computer 1 to notify the end of the service request.
0 is rewritten to a code indicating a release request (625), and the address of the main control block is registered in the reception direction FIFO 22R (626).

Command code 40 of main control block 40
0 indicates a data transmission request, but the transmission data is 4K
If it is larger than B, the transmission data is divided for every 4 KB, and the transmission processing is passed to the communication protocol processing unit. First, a local control block 50 is generated (627),
A code indicating that the transmission data is being divided (data bit = 0) is set in the command code of the local control block (628), and the DMAC is instructed to read 4 KB of transmission data from the main memory to the local memory. (629).

When the read operation of the transmission data divided into 4 KB is completed by the DMAC, the head address of the transmission buffer divided into 4 KB read into the local memory is set in the local control block 50, and the address of the local control block is transmitted. It is registered in the protocol processing request pool (630). Data length of main control block 4
By decrementing 4 KB from 08 and incrementing 4 KB from the pointer address 406, the length of the remaining transmission data and the address indicating the beginning of the next transmission data to be transmitted are reset in the main control block (631). ). Again, the data length of the main control block is 4
It is determined whether 08 is larger or smaller than 4 KB. If larger than 08 KB, the dividing process is repeated, and if smaller than 08 KB, the process of not dividing the transmission data is performed.

If the command code 400 of the main control block 40Tn is not a data transmission request, that is, if the processing of the reception buffer is notified, the main control block for reception is released (632).

FIG. 17 shows details of the communication protocol processing routine 64T executed following the interface processing routine 62T. In this routine, first
The address of the local control block 50 is read from the communication protocol processing request pool 440 (642), and the connection ID 5 included in the local control block 50 is read.
02, the DA field 504, and the TP4 connection management table 446 on the local memory, the TP4 header, the CLNP header, the LLC header, and the MAC header are sequentially added to the head of the data (644T to 650T). The control code (EOT bit) used for dividing and assembling the TP4 header is EOT bit = 0 if the command code of the local control block indicates that the data is being divided, and EOT if the command code indicates the end of the data division. Bit = 1. Each time the header is created, the values of the buffer start address 506 and the data length 508 of the local control block are updated in accordance with the newly added header length value.

When the creation of the MAC header 35 is completed (6
50T), the address of the local control block 50 is registered in the communication control circuit driver transmission pool 444T (6T).
55), a communication control circuit driver processing routine 66T is executed.

Communication control circuit driver processing routine 66T
Then, as shown in FIG. 18, the address of the local control block 50 is read from the communication control circuit driver transmission pool 444R (662).
A data transmission request is issued by designating the buffer start address 506 and the data length 508 (664).

Next, the data reception (event report) operation executed by the local processor will be described.

FIG. 19 shows the reception sub 70 shown in FIG.
9 is a flowchart showing the contents of R.

The reception sub 70 R includes a communication control circuit driver processing routine 72 R for controlling the communication control circuit 26,
It comprises a communication protocol processing routine 74R and an interface processing routine 76R with the computer 1.

When a packet is received from the network transmission line 5, an empty reception buffer area 247Rn on the local memory is obtained from the communication control circuit 26, and a reception packet from which the synchronization bit 33 and the FCS 34 have been removed is set in the local reception buffer. The communication control circuit driver 300 is notified that the packet has been received. In the communication control circuit driver 300, as shown in FIG. 20, a command code 500 indicating data reception and a start address 5
06 and the reception data length (including the header length) 508 are set (722), and the reception pool 4 for the communication control circuit driver is set.
The address of the local control block 50 is registered in 44R (724), and the communication protocol processing 74R is executed.

FIG. 21 shows the details of the communication protocol processing routine 74R executed following the communication control circuit driver processing routine 72R. In this routine,
First, the MAC processing unit 240 reads the address of the local control block 50 from the communication control circuit driver reception pool 444R (742), and analyzes the MAC header (744R). After the completion of the MAC processing, the LLC processing unit 23
0, the local control block 50 is sequentially delivered to the CLNP processing unit 220 and the TP4 processing unit 210, and header analysis (746R, 748R, 750R) is performed for each protocol. In each header section, after analyzing the header, the address indicating the head of the data excluding the header is reset to the buffer head address of the local control block 50. At the time of header analysis, a CLNP header indicating the other party and TP4
The header information is stored in connection ID 402, D
A (MAC) 404 as the local control block 50
(755). In the TP4 processing unit, after analyzing the TP4 header, the data bits (50
In 9), the EOT bit of the TP4 header is set, the command code (500) is set to a command code indicating a data reception report, the address of the local control block is registered in the communication protocol processing end pool (442), and the interface processing routine 76R Execute

The interface processing routine 76 shown in FIG.
In R, as shown in FIG. 22, first, the local control block 50 is read from the communication protocol processing end pool 442 (761), it is determined whether the report is a data reception report, and a reception processing table corresponding to a connection is selected (R). 762). If there is an empty area in the reception buffer, the received data is written by the DMAC to the position indicated by the PW in the reception processing table (763). If the received data is located at the head of the reception buffer, the status of the reception processing table is 0. In these cases, the head address (PW) of the received data is set to BP, 0 is set to LEN (769), and 1 is set to the status (770). Next, the data length of the local reception buffer written in the local reception buffer is added to PW and LEN of the reception processing table and updated (764). If the data bit 509 of the local control block is "0", assembling of the received data has not been completed, the reception report is not made to the computer, the local control block and the local reception buffer are released, and the interface processing is completed. (768).

If the data bit = “1”, the received data to be processed is either transmitted as a single packet or the last part divided into a plurality of blocks. In this case, it is necessary to report data reception to the computer, set 0 to the status of the reception processing table (765), and set the command code indicating data reception in the main control block and the BP of the reception processing table in the buffer address. The address of the stored reception buffer, the data length stored in the reception processing table LEN, and the connection ID are set (766). Next, the address of the main control block is registered in the reception FIFO 22R ( 767), reports data reception to the computer, releases the local control block and the local reception buffer at the same time, and ends the interface processing (768).

(Embodiment 2) A second embodiment of the present invention is shown in FIG.
3 and FIG.

FIG. 23 is a block diagram of the communication control apparatus 4 provided with a dedicated processor (interface processor) 104 for executing interface processing in addition to the local processor 25.

The interface processor 104 includes:
First local bus 23A and second local bus 23B
The communication control device further includes a direct memory controller (DMAC) 27 connected to the first local bus 23A and a bus interface 21.
And a first FIFO 22T used to transmit control information from the computer 1 to the communication control device 4, and a second FIFO 22R used to transmit control information in the opposite direction.

The communication control device reads out the transmission data written in the reception buffer area on the main memory by the computer, packetizes the data and sends it out to the network transmission line 5, and includes it in the received packet from the network transmission line 5. The received data to be written is written into a pre-allocated reception buffer area on the main memory, and reassembly processing is performed on this area. In addition, the communication control device performs an operation (protocol processing) of creating a header for transmission data or analyzing a header attached to reception data, in addition to an operation of reading and writing transmission / reception data to / from the main memory. In the first embodiment, these operations are performed by one processor, but in the second embodiment, these operations are executed by two processors (the local processor 25 and the interface processor 104) in order to speed up processing. .

That is, the interface processor 10
Reference numeral 4 reads the transmission data written in the transmission buffer area on the main memory, divides the transmission data into a plurality of transmission data blocks, and writes the divided data into the local memory 24. In addition, a reception buffer for each connection is secured in the reception buffer area on the main memory, and while the free area of each reception buffer area is managed, each reception data block written by the local processor 25 on the local memory 24 is received. The data blocks are sequentially written into the empty areas of the reception buffer corresponding to the data blocks.

On the other hand, the local processor 25 forms a packet by adding a header to each transmission data block written in the local memory 24 and sends the packet to the network transmission line 5. Further, for a packet received from the network transmission line 5, after performing header processing, a received data block included in the received packet is written to the local memory. That is, the interface processor 104 performs the interface processing 6 of the transmission / reception operations shown in FIGS.
As shown in FIG. 24, 2T and the interface processing 76R are executed alternately.

As described above, the communication control device is constituted by the local processor and the interface processor, the protocol processing (74R, 64T) and the communication control circuit driver processing (72R, 66T) are performed by the local processor, and the main memory is processed by the interface processor. By performing the interface processing (76R, 62T) between the communication control device and the communication control device, the processing speed can be increased.

[0079]

As is apparent from the above description, according to the present invention, the transmission buffer is managed on the main computer side and the reception buffer is managed on the communication control device side. The write operation to the memory can be executed immediately by the judgment of the communication control device side, and the transmission and reception data processing of the communication control device can be speeded up.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating details of a computer and a communication control device according to a first embodiment of this invention.

FIG. 2 is a diagram showing one configuration example of a data communication system to which the present invention is applied.

FIG. 3 is a diagram illustrating a configuration example of a layered communication protocol.

FIG. 4 is a diagram showing a basic configuration of software provided in the communication control device.

FIG. 5 is a diagram illustrating a relationship between transmission data and transmission packets.

FIG. 6 is a diagram showing a format of a transmission packet.

FIG. 7 is a diagram for explaining an outline of a data transmission / reception operation.

FIG. 8 is a diagram showing a configuration of a main control block.

FIG. 9 is a reception processing management table 2 provided in the communication control device.
FIG. 46 is a diagram illustrating a configuration of a controller 46;

FIG. 10 is a diagram showing a relationship between a write operation of a data block to a main memory performed by a communication control device and a value of a control parameter.

FIG. 11 is a diagram showing a configuration of a local memory 24 included in the communication control device.

FIG. 12 is a diagram showing a configuration of a local control block used in the communication control device.

FIG. 13 is a diagram showing a configuration of a communication protocol processing area provided in a local memory.

FIG. 14 is a basic flowchart of a communication control operation executed by the communication control device.

FIG. 15 is a flowchart showing details of a transmission sub60T in FIG.

FIG. 16 is a flowchart showing details of an interface process 62T in FIG. 15;

FIG. 17 is a flowchart showing details of a communication protocol process 64T in FIG. 15;

18 is a communication control circuit driver processing 6 in FIG.
It is a flowchart which shows the detail of 6T.

FIG. 19 is a flowchart showing the contents of a reception sub 70R in FIG.

20 is a communication control circuit driver process 7 in FIG.
It is a flowchart which shows the detail of 2R.

FIG. 21 is a flowchart showing details of a communication protocol process 74R in FIG. 19;

FIG. 22 is a flowchart showing details of interface processing 76R in FIG. 19;

FIG. 23 is a block diagram illustrating a configuration of a communication control device according to a second embodiment of the present invention.

FIG. 24 is a flowchart showing a control operation executed by an interface processor 104 in the second embodiment.

[Explanation of symbols]

 1A, 1B, 1C Computers 4A, 4B, 4C Communication control devices B1, B2, Bn Data blocks 30-1, 30-2, 30-n Packets 40T1 to 40Tm Main control block 40T Multiple main controls Area for storing blocks 40R1 to 40Rn Main control block 40R Area for storing a plurality of main control blocks 41T1 to 41Tm Transmission buffer area 41T Area for storing transmission data 41R1 to 41Rn reception buffer Area 41R: Area for storing received data 50T: Local control block 50R: Local control block 247T1, 247Tm: Transmission data 247T: Local transmission buffer area 247R1, 247Rn: Reception data 247R: Local reception buffer area

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Junji Fukuzawa 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside Hitachi, Ltd.System Development Laboratory Co., Ltd. (72) Matsuaki Terada 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture (56) References JP-A-1-194547 (JP, A) JP-A-2-55444 (JP, A) JP-A-63-222544 (JP, A) JP-A-63 JP-A-275239 (JP, A) JP-A-59-36222 (JP, A) JP-A-62-108640 (JP, A) JP-A-61-170163 (JP, A) JP-A-63-217457 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 29/00 H04L 13/08 H04L 12/00

Claims (5)

(57) [Claims] 1. A communication control circuit connected to a communication path and a computer having a main memory, the communication control circuit being a connection circuit with the communication path, and means for performing a protocol process on a received packet received by the communication control circuit. A communication control device, comprising: a reception buffer address management unit that holds, updates, and instructs a write address in a reception buffer provided in the main memory; and Data writing means for writing data generated from a packet to the reception buffer of the computer in accordance with an instruction of the reception buffer address management means; address notification means for notifying the computer of an address of the reception buffer in which the data is written A communication control device comprising: 2. The communication control device according to claim 1, wherein said reception buffer address management means manages whether or not one message assembly is completed by generating data from said reception packet, and said address notification means. A communication control device for notifying the address when data for which the assembly of the one message is completed is written to the reception buffer. 3. The communication control device according to claim 1, wherein said reception buffer address management means manages a write address of each of said plurality of reception buffers, and connects each of said plurality of reception buffers to one connection. Communication control device that is assigned to and managed. 4. The communication control device according to claim 3, wherein said reception buffer address management means comprises a management table, and for each of said plurality of reception buffers, a reception buffer head address, a reception buffer length, a transport connection identifier. Means for managing a write pointer; means for performing the protocol processing, comprising means for receiving a packet from the communication path and extracting a transport connection identifier from a header when performing header processing, and wherein the data writing means comprises: A communication control device that writes received data to a write pointer of any one of the reception buffers corresponding to a transport connection identifier managed in a management table. 5. The communication control device according to claim 1, further comprising a first processor and a second processor, wherein the first processor includes a unit that performs the protocol processing. A communication control device that controls the reception buffer address management unit, the data writing unit, and the address notification unit.