JP3275514B2 - Data recording method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recording / reproducing method suitable for high-density recording such as a digital VTR.

[0002]

2. Description of the Related Art At present, researches on digital VTRs for recording video and audio signals by digital signals of 0 and 1 have been conducted for the purpose of high image quality and long-time recording. In particular, a video signal has a lot of information, and in order to record it for a long time, high-density recording for recording a lot of information on a tape is indispensable. Currently, two types of methods have been attempted to perform high-density recording. The first method is a method of shortening the length necessary for recording one bit, that is, a method of increasing the so-called linear density. The second method is to reduce the track width.

Conventionally, linear density has been improved from the viewpoints of recording material and signal processing, and it has become practically possible to record about 1 bit at about 0.25 μm. On the other hand, the track width has been limited to about 10 microns for a VTR from the viewpoint of mechanical accuracy used for recording and reproduction and tracking control for obtaining a stable reproduction output.

For example, in an 8 mm VTR, a pilot signal is superimposed on a video signal or an audio signal and recorded. During reproduction, the pilot signal is extracted from the reproduced signal, and tracking is performed by detecting the amplitude level of the pilot signal. In addition, by assigning this pilot signal to a frequency different from the recording frequency band of the video signal and the audio signal, consideration is given so that the pilot signal does not interfere with the video signal and the audio signal. With such a method, a track width of 10 μm is realized in an 8 mm VTR.

[0005]

In the case of a digital VTR that records a video signal or an audio signal as a digital signal, the amount of information to be recorded is much larger than that of an analog VTR. In other words, a technique for high-density recording is more required than an analog VTR.

In a digital VTR, a signal band to be recorded is much wider than an analog VTR, so that it is difficult to assign the frequency of a pilot signal to a frequency band different from a signal to be recorded, such as an 8 mm VTR. Therefore, the pilot signal frequency must be allocated within the frequency band of the signal to be recorded. Also, in order to achieve a narrow track width, it is necessary to increase the ratio of the signal amplitude level to the noise level of the pilot signal. However, if the amplitude level of the pilot signal is increased, the amplitude of a signal different from the originally recorded signal is increased, so that when reproducing, the pilot signal disturbs and each bit becomes "
The probability of erroneously determining whether the signal is “1” or “0” increases, so that even if a signal different from the signal to be recorded is to be superimposed as a pilot signal, the amplitude of the pilot signal cannot be increased. If the amplitude of the reproduced signal cannot be increased, the S / N ratio of the pilot signal in the reproduced signal is deteriorated, and the tracking accuracy is deteriorated.

As described above, a system in which a signal different from a signal to be recorded is superimposed as a pilot signal has a problem that it is difficult to realize a system with a narrow track width.

The data recording / reproducing method of the present invention aims at solving such a conventional problem.

[0009]

According to the present invention, the following method is newly proposed as means for solving the above-mentioned problems.

That is, the data recording method of the present invention
Along with audio data, video data and additional data
SYN consisting of a period code word and at least one ID code word
Record insert information consisting of multiple C blocks
A data recording method for recording on a medium, wherein the ID code
The word repeats each bit of the m-bit data word once, 2
generating an m-bit code;
2 bits of “01” or “10” for the code of
2T precoding is performed as the period value,
The disparity is always 0 by adding the period value to the beginning 2
Step of generating m + 2 bits of precode data
And the disparity is 0 or
Adds k-bit dummy data of + i or -i
To generate an ID code word of 2m + 2 + k bits.
It is characterized in further comprising a flop.

[0011]

According to the present invention, according to the present invention, since the signal itself of the data sequence to be originally recorded is a pilot signal, the error rate does not deteriorate even if the amplitude level of the pilot signal is increased. .

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows an example of a recording track pattern according to an embodiment of the present invention. In FIG. 3, areas A and V are areas for recording audio and video data, respectively. An area INDEX is an area for recording information such as a time code. G2 to G4 are IN
The DEX, A and V areas are provided so that insert recording can be performed separately. The recording amplifier is turned on / off in these areas. G5 is provided to prevent old data from being erased when overwritten. G
When the data in the A, V, and INDEX areas are rewritten for insert recording,
This is an area for detecting the pilot signal by reproducing the area of 1 and ITI and performing tracking.

Next, by reproducing G1 and ITI,
Explain how to apply tracking. G1 and ITI
FIG. 4 shows a frequency spectrum of a data string recorded in the area of. As shown in FIG. 4, the frequency spectra of the recording patterns in the G1 and ITI areas are F0, F1, F
2, (a) shows the spectrum of the F0 pattern, (b) shows the spectrum of the F1 pattern, and (c) shows the spectrum of the F1 pattern.
These are two patterns of spectrum. As is clear from the figure, the F0 frequency spectrum has no peak at the frequencies f1 and f2. Also, F1 has a peak at frequency f1 and has no peak at frequency f2. F2 is the frequency f2
And a peak at the frequency f1. In this embodiment, the frequencies f1 and f2 of the pilot signals recorded on the GI and ITI are each 1/90 of the recording frequency.
And 1/60.

These patterns are arranged on a tape as shown in FIG. Before and after the track having the spectrum of F0, tracks of the spectrum of F1 and F2 are arranged. When the reproducing head is on the track of F0, the spectrum of F0 originally has no peaks at the frequencies f1 and f2. The reproduced signal of F0 also has peaks at the frequencies f1 and f2 due to the crosstalk from the tracks F1 and F2. When the head being scanned is displaced from the track of F1, the f1 frequency component in the reproduced signal of F0 increases and the f2 component decreases at the same time. On the other hand, when the scanning head is shifted in the direction of F2, the frequency f1 component decreases and the frequency f2 component increases. Thus, by reproducing the track of F0, it is possible to detect in which direction and how much the head is displaced from the track, and by adjusting the tape feed speed to compensate for the displacement. Tracking can be applied.

A pilot signal is generated by recording G1 and ITI as follows. The data recorded in G1 and ITI have a disparity of +2 and -2 every 10 bits.
And a 10-bit code word having a disparity of +2, -2 and 0 every 10 bits, thereby creating a data string of each pattern.

FIG. 13 shows an example of an arrangement of codewords having a disparity of ± 2 and 0 every 10 bits. The F0 pattern is recorded using only a 10-bit codeword having a disparity of 0. The F1 and F2 patterns repeat 10-bit codewords of +2, -2, and 0 in the cycle of the pilot signal. FIG.
FIG. 9 shows the change in the accumulated value of the disparity of the recording pattern of F1. As shown in FIG. 2, in the data of the pattern of F1, the accumulated value of the disparity repeatedly increases and decreases in a cycle of 90 bits. By repeatedly increasing and decreasing at a period of 1/90 of the recording frequency, which is the period of the pilot signal, a pilot signal can be generated at a frequency of 1/90 of the recording frequency. The reason is that the disparity is the average value of the code word. If the increase / decrease is periodic, the spectrum of the frequency corresponding to the period increases, and this frequency component becomes a pilot signal. Similarly, in the recording pattern of F2, since the cumulative value of the disparity repeats increasing and decreasing at a period of 1/60 of the recording frequency, a pilot signal can be generated at a frequency of 1/60 of the recording frequency. If the absolute value of the disparity every 10 bits is increased, the amplitude of the pilot signal can be increased.

FIG. 6 shows a G1 recording pattern of this embodiment. FIG. 6 is an example of the pattern of F1. G1 is composed of three types of codewords: a run pattern A having a disparity of +2, a run pattern B having a disparity of 0, and a run pattern C having a disparity of -2. By disposing the three types of codewords as shown in FIG. 6, the disparity for every 10 bits is arranged as shown in FIG. 13, so that a pilot signal can be generated at the frequency f1. F0 pattern and F2 pattern are also 10
As shown in FIG. 13, the disparity of each bit arranges the run pattern A, the run pattern B, and the run pattern C.

In this embodiment, the ITI region not only generates pilot signals, but also A and V and INDE.
The position information of the X on the tape is also recorded. In the case of insert recording of a video signal or post-recording of an audio signal, in order to rewrite the previously recorded data of A, V, and INDEX, it is necessary to know the position of the recorded data accurately. In the ITI area, 64 sync blocks each including a synchronous codeword and an ID codeword are recorded. In each sync block, the number of the sync block is recorded.
It is recorded continuously from the first sync block of I. The position of the head on the track can be known from the sync block number detected from the reproduction signal. Thereby, it is possible to determine when to record the data of A, V, and INDEX, and it is possible to rewrite each data at an accurate position. In addition, G2 to G4 can be set shorter, and more audio and video data can be recorded. Also IT
By detecting I, the recording positions of A, V, and INDEX are recognized for each track. Therefore, even if the entire track is greatly deviated from the position specified by the standard, the insert or the after-recording can be accurately performed. It can be carried out.

ITI has 64 bits each consisting of 30 bits.
It is composed of sync blocks. FIG. 7 shows the configuration of the sync block. The sync block includes a 10-bit synchronous codeword, a 10-bit ID codeword-L, and a 10-bit ID codeword-U.

FIG. 8 shows a bit pattern of a synchronous codeword in this embodiment. Synchronous codewords have a disparity of +2
SYNC-A, SYNC-B of 0, and SYNC of -2
There are three types of C-C. At the time of recording, there are three types of synchronization code words, SYNC-A, SYNC-B, and SYNC-C. When the partial response class 4 is detected, the first 2 bits are undefined, but the last 8 bits are as shown in FIG.
The three types are the same as shown in FIG. SYNC-
In order to generate a pilot signal from the three types of A, SYNC-B, and SYNC-C, a synchronous codeword is selected by selecting so that the accumulated value of disparity increases or decreases in the cycle of the pilot signal.

The ID code word -L has an ID-LA having a disparity of +2, an ID-LB having a disparity of 0, and a disparity of -2 as in the case of the synchronous code word. There are three types of certain ID-LC. As shown in FIG. 10, the ID code word -L is divided into a block number portion of 8 bits and a dummy portion of 2 bits. In the block number part, 6
The lower three bits of the sync block number represented by bits are encoded and recorded.

FIG. 9 shows an encoding method for three types of block number parts. FIG. 9 shows a case where the lower 3 bits of the block number are 6. First, as shown in FIG. 9, each of the lower three bits of the block number is repeated once to form a 6-bit codeword. The initial values of ID-LA and ID-LB are "0".
2T-precode as "1". ID-LB is "1".
2T-precode with 0 "as an initial value. Two bits as an initial value are added to the head of the 6T-precoded 6T bits to form an 8-bit codeword, and the disparity of the 8-bit codeword is In all three types, the disparity of the 8-bit block number portion is always 0. Therefore, the disparity of the ID code word -L is determined by the dummy portion. Since the disparity is +2, the part is "11" and the ID-
Since the disparity of the dummy portion of LB is 0, “0”
1 ", the disparity of the ID-LC dummy part is-
Since it is 2, it is “00”. ID code word -L is ID-
Since a pilot signal is generated from three types of LA, ID-LB and ID-LC, the accumulated disparity value is selected so as to increase or decrease in the cycle of the pilot.

The ID code word -U includes the ID code word -L.
ID-UA with a disparity of +2 as in
And ID-UB having a disparity of 0 and ID-UC having a disparity of -2. The ID code word -U is divided into a block number portion of 8 bits and a dummy portion of 2 bits, similarly to the ID code word -L shown in FIG. The upper three bits of the sync block number represented by 6 bits are encoded and recorded in the block number portions of the three types of ID code words -U. These three bits are I
It is encoded in the same manner as the block number part of the D codeword-L. Therefore, the disparity of the ID code word -U is also determined by the dummy part. The dummy portion of ID-UA has a disparity of +2 and thus has a value of "11". The dummy portion of ID-UB has a disparity of 0 and has a value of "01".
Since the disparity of the dummy portion of the U-C is -2 "
00 ". Since the ID code word -U generates a pilot signal from among the above three types, the ID code word -U is selected so that the accumulated value of disparity increases or decreases in the cycle of the pilot signal.

Since the lower three bits of the block number are repeatedly recorded in the ID code word -L as shown in FIG. 9, the lower three bits of the reproduced block number are the same unless there is an error. Two values are played. Therefore, whether or not the lower three bits of the two block numbers to be reproduced have the same value can be used as a criterion for judging the presence or absence of an error. Similarly, in the case of the ID code word -U, whether or not the upper 3 bits of the two reproduced block numbers have the same value can be used as a criterion for determining the presence or absence of an error.

FIG. 11 shows the order in which the synchronous codeword, the ID codeword-L, and the ID codeword-U in the F1 pattern are selected. By configuring ITI in this order,
Since the accumulated value of disparity every 10 bits increases or decreases in the pilot cycle, a pilot signal can be generated. Also, at the boundary between G1 and ITI, by recording so that the increase / decrease of the accumulated value for every 10 bits is continuous, a continuous pilot signal can be generated between G1 and ITI.

FIG. 12 shows an ID code word-L and an ID code word-
FIG. 2 shows a block diagram of a 2T-precode used for encoding U. The 2T-precoding is performed in advance at the time of recording in order to determine “1” or “0” in the partial response class 4 from the reproduced signal. In the present embodiment, 2T-precoding is performed on a 6-bit codeword, but "1", "0" or "0", The value of "1" is loaded as an initial value. Each bit of the input 6-bit code word is the output of the D-FF circuit 22 which is the value output from the 2T-precode circuit two bits before, and the EOR circuit 21
Is exclusive-ORed and output. In this manner, the block number portions of the ID code word-L and the ID code word-U can be detected by the partial response class 4.

FIG. 1 is a block diagram showing an embodiment of a recording apparatus for forming the G1 and ITI areas in the track pattern described above. Run pattern A
The generation circuit 1, the run pattern B generation circuit 2, and the run pattern C generation circuit 3 are circuits that generate the run patterns A, B, and C, respectively. The SYNC-A generation circuit 4, the SYNC-B generation circuit 5, and the SYNC-C generation circuit 6
-A, SYNC-B and SYNC-C. ID-LA generator 7 and ID-LB generator 8
And the ID-LC generator 9 correspond to the block number generator 1
3 as the input, the lower three bits of the block number are used as input, and ID-LA, ID-LB, ID-L, respectively.
Generates -C. ID-UA generating circuit 10 and ID-U
The -B generation circuit 11 and the ID-UC generation circuit 12 receive the upper three bits of the block number output from the block number generation circuit 13 as inputs, and output the ID-UA and ID-UA, respectively.
-UB and ID-UC are generated.

The cycle generation circuit 14 outputs a 2-bit control signal. When the pilot signal has a 1 / 90th of the recording frequency as in the case of the F1 pattern, the 2-bit control signal is "0" in the first 40 bits, and the next 1
The 0 bit is “1” and the next 40 bits are “2”.
The cycle generation circuit 14 outputs a 2-bit control signal to G1 and IT
It outputs repeatedly while recording I. In the F2 pattern, “0” and “2” are repeated every 30 bits, and F0
It is always "1" in the pattern.

The switching circuit 15 selects the output of the run pattern A generation circuit 1 when the output of the cycle generation circuit 14 is "0", and selects the output of the run pattern B generation circuit 2 when the output is "1". , "2", the output of the run pattern C generating circuit 3 is selected. The switching circuit 16 includes a period generation circuit 14
When the output is "0", the output of the SYNC-A generation circuit 4 is selected. When the output is "1", the output of the SYNC-B generation circuit 5 is selected. When the output is "2", the SYNC-C generation circuit is selected. 6 is selected. The switching circuit 17 selects the output of the ID-LA generation circuit 7 when the output of the cycle generation circuit 14 is “0”, and selects the output of the ID-LB generation circuit 8 when the output of the cycle generation circuit 14 is “1”. When it is "2", the output of the ID-LC generator 9 is selected. The switching circuit 18 selects the output of the ID-UA generation circuit 10 when the output of the cycle generation circuit 14 is "0", and selects the output of the ID-UB generation circuit 11 when the output is "1". When it is "2", the output of the ID-UC generator 12 is selected.

The data switching control circuit 20 outputs a 2-bit control signal, which is "0" when G1 is recorded and "0" when a synchronous codeword is recorded in ITI.
1 "to record the ITI ID codeword -L
2 "to record the ITI ID codeword -U
The switching circuit 19 selects the output of the switching circuit 15 when the control signal input from the data switching control circuit is "0", and the control signal from the data switching control circuit is "1". In the case of (3), the output of the switching circuit 16 is selected, in the case of "2", the output of the switching circuit 17 is selected, and in the case of "3", the output of the switching circuit 18 is selected. From G1 and I
TI data can be output.

In this embodiment, an example of realizing the configuration as shown in FIG. 1 has been described. However, the bit string output in this embodiment is stored in a storage circuit in advance, and the bit string is output from the storage circuit. Even in this case, the same effect as in the present embodiment can be obtained.

The above embodiment has been described in connection with the case where the pilot frequencies f1 and f2 are respectively 1/90 and 1/60 of the recording frequency.
Even when 1 and f2 are 1/60 and 1/40, respectively, the disparity of every 10 bits of the G1 and ITI bit strings is arranged as shown in FIG. Can occur. By arranging a 10-bit code word in this way, in the case of the F0 pattern, the accumulated value of the disparity every 10 bits is always 0, and 1 in the F1 pattern.
The cumulative value of disparity for every 0 bit increases and decreases in a cycle of 60 bits. Further, the accumulated value of disparity every 10 bits of the F2 pattern increases or decreases in a cycle of 40 bits.
Thus, the frequency F1 of the F1 pattern and the frequency f2 peak of the F2 pattern are obtained. The peak levels of the frequency f1 and the frequency f2 of the F0 pattern are respectively equal to the frequency f1 and the frequency f1 of the F2 pattern.
2 is sufficiently smaller than the peak level.

The pilot frequencies f1 and f2 are:
Even in the case of 1/60 and 1/40, respectively, data recording can be realized using the circuit of the block diagram shown in FIG. In this case, the period generation circuit 14 in FIG. 1 may output a control signal so that the disparity for every 10 bits is as shown in FIG.

[0035]

As described above, according to the data recording / reproducing method of the present invention, since the bit string to be recorded itself generates a pilot signal, a pilot signal having a large amplitude level is generated without increasing the error rate. Can do things. This can improve tracking accuracy,
It is easy to realize a system with a narrow track width.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a recording apparatus capable of realizing a data recording / reproducing method of the present invention.

FIG. 2 is a diagram showing an increase / decrease of a cumulative value of disparity in one embodiment of the present invention.

FIG. 3 is a configuration diagram of a track recorded by the data recording / reproducing method of the present invention.

FIG. 4 is a diagram showing an example of a frequency characteristic of a data string recorded by the data recording / reproducing method of the present invention.

FIG. 5 is a layout diagram on a tape of a data sequence recorded by the present invention.

FIG. 6 is a diagram showing an example of a selection order of each codeword in a G1 area recorded by the data recording / reproducing method of the present invention.

FIG. 7 is a diagram showing an example of the configuration of a sync block in an ITI area recorded by the data recording / reproducing method of the present invention.

FIG. 8 is a diagram showing an example of an ITI synchronization codeword recorded by the data recording / reproducing method of the present invention.

FIG. 9 shows IT recorded by the data recording / reproducing method of the present invention.
FIG. 3 is a view for explaining an example of an encoding method of a block number part of an ID codeword-L of I

FIG. 10 shows I recorded by the data recording / reproducing method of the present invention.
The figure which shows the structure of D code word-L, and an example of a dummy part

FIG. 11 is a diagram showing an example of a selection order of each codeword in an ITI area recorded by the data recording / reproducing method of the present invention.

FIG. 12 is a block diagram showing an example of a 2T-precode used in the data recording / reproducing method of the present invention.

FIG. 13 is a diagram showing an example of a disparity of a code word for every 10 bits of a data sequence recorded by the data recording / reproducing method of the present invention.

FIG. 14 is a diagram showing another example of the disparity of the code word for every 10 bits of the data sequence recorded by the data recording / reproducing method of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 run pattern A generation circuit 2 run pattern B generation circuit 3 run pattern C generation circuit 4 SYNC-A generation circuit 5 SYNC-B generation circuit 6 SYNC-C generation circuit 7 ID-LA generation circuit 8 ID-LB Generation circuit 9 ID-LC generation circuit 10 ID-UA generation circuit 11 ID-UB generation circuit 12 ID-UC generation circuit 13 Block number generation circuit 14 Period generation circuit 15 Switching circuit 16 Switching circuit 17 Switching circuit 18 Switching circuit 19 Switching circuit 20 Data switching control circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Makoto Goto 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-7-6515 (JP, A) JP-A-6-342585 (JP, A) JP-A-1-317280 (JP, A) JP-A-59-75416 (JP, A) JP-A-4-80620 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 15/467 G11B 20/14 G11B 5/09

Claims (10)

(57) [Claims] 1. Audio data, video data and addition
Along with the data, a synchronization codeword and at least one ID code
An SYNC block consisting of multiple words
This is a data recording method for recording certificate information on a recording medium.
And the ID code word is each bit of an m-bit data word.
Is repeated once to generate a 2m-bit code
And “01” or “1” for the 2m-bit code.
With 2 bits of 0 ”as initial values, 2T precoding is performed.
And the initial value of 2 bits is added
2m + 2 bit pre-coded data that always has 0
Generating a pre-coded data;
K-bit data whose parity is 0 or + i or -i
2m + 2 + k bit ID codeword
Generating a data record
Recording method . 2. The data recording method according to claim 1, wherein:
The disparity of the synchronization codeword is + i or 0 or
-I is one of the three
Data recording method to be used . 3. The data recording method according to claim 1, wherein
Disparity of dummy data in the ID code word
Is 0 or + i or -i.
A data recording method, characterized in that the data is recorded by recording . 4. The data recording method according to claim 2, wherein
And the disparity of the digital data to be recorded
The synchronous code word and the synchronous code word so that the cumulative value changes periodically.
Data that selects and records dummy data.
Data recording method . 5. The data recording method according to claim 4, wherein:
If the accumulated value of the disparity is 90 bits or 60 bits
To change in either the bit or the 40 bits
Selecting a synchronization code word and the dummy bit.
Data recording method . 6. The data recording method according to claim 3, wherein
In selecting the synchronous codeword and the dummy data,
The synchronous code word having a disparity of 0 and the dummy data
A data recording method characterized by selecting data . 7. The data recording method according to claim 5, wherein
And the synchronous code word and an ID code of 2m + 2 + k bits
Data Symbol bit length of Gogo is characterized in that it is a 10
Recording method . 8. The data recording method according to claim 7, wherein:
A data recording method, wherein m is 3 . 9. The data recording method according to claim 7, wherein
Is 2, the data recording method . 10. according to any one of claims 1 to 9 Day
Data recording method, wherein i is 2.
Data recording method .