JP3268216B2 - Phase-locked oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked oscillation circuit realized by digital elements.

[0002]

2. Description of the Related Art A phase-locked oscillation circuit (hereinafter, referred to as a "PLL circuit") is a circuit widely used as a standard signal generator and a tuning circuit in the communication field and the like.

FIG. 4 shows a first prior art. FIG. 4 shows a generally known PLL circuit configuration. The phase comparison circuit 41 shown in FIG. 4 is configured such that the input signal fs and the voltage controlled oscillator (VC
The phase with the output fo of the O-circuit 44 is compared to generate a difference signal voltage corresponding to the phase difference between the two signals. The difference signal voltage output from the phase comparison circuit 41 is filtered by a low-pass filter 42, further amplified by an amplifier 43, and
The oscillation frequency of the circuit 44 is controlled. The phase difference signal voltage is
It is applied to the control terminal of the VCO circuit and its oscillation frequency fo
Is controlled in a direction to reduce the difference from fs. That is, if the input signal and the VCO signal frequency are sufficiently close, fo becomes fs
And the phase difference disappears. In the circuit of the related art, the VCO circuit is analog-controlled by the phase difference signal voltage.

Next, a second prior art is shown in FIG. Recently, a method of configuring a PLL circuit with a digital circuit has been attempted, and FIG. 5 shows one example. A digitally operated phase comparison circuit 51 compares the input clock signal with the output clock signal of an oscillation circuit (voltage controlled oscillator) 53, and outputs whether the phase is advanced or delayed, and outputs the delay of the oscillation circuit. To match the phase with the input clock signal. The digital phase comparison circuit 51
If the output signal is behind the phase of the input signal, the output signal UP is activated, and if the phase is advanced, the output signal DOWN is activated. The UP or DOWN signal controls the oscillation circuit 53 through the charge pump 52. The oscillation circuit portion is configured using a CMOS inverter, but the control of the oscillation frequency is controlled in an analog manner by the output voltage value of the charge pump. A PLL circuit similar to this is disclosed in JP-A-6-276092.

However, in this prior art, each part is CMOS.
Although constituted by digital elements, the control of the oscillation circuit is performed in an analog manner, so that it cannot be said that this is a complete digital circuit.

[0006]

As described in the previous section,
If a PLL circuit, which has been conventionally designed using analog circuit technology, can be implemented as an LSI with a complete CMOS digital circuit, there are various advantages over analog circuits. For example, by configuring a CMOS digital circuit, it is possible to reduce power consumption, and it is not affected by fluctuations in the voltage amplitude of an input signal. The tendency of configuring a PLL circuit with a complete digital CMOS circuit has been increasing in recent years, and one of the main methods is to obtain an oscillation clock signal using a ring oscillator. The number of inverter stages in the ring oscillator is switched by a selector. The maximum operating frequency allowed by the oscillator circuit of this configuration must consider at least the gate delay time of the selector and the CMOS inverter.
Not suitable for operation in high frequency band.

An object of the present invention is to configure a PLL circuit with a completely digital circuit without using an analog circuit technique such as a low-pass filter or a voltage-controlled oscillation circuit, and to control the oscillation frequency for a shorter time. It is an object to provide a circuit which can be performed in units.

[0008]

A digital PL according to the present invention.
The L circuit connects two CMOS inverters in series,
One transfer gate, which is a combination of one PMOSFET and one NMOSFET, connected in series to the above-described inverter row, is connected in n stages in parallel, and one inverter is arranged in a feedback loop from its output to its input. A ring oscillator oscillating circuit in which two CMOS inverters are connected to the output stage to stabilize the potential; a phase comparing circuit for comparing the phase of the input clock signal with the phase of the frequency of the output signal of the oscillating circuit; A control circuit that receives an output of the phase comparison circuit as an input and outputs a signal for controlling the oscillation frequency of the oscillation circuit. The n transfer gates of the above-described ring oscillator have different R values by adjusting the transistor size.
It is designed to have a C value (resistance value and capacitance value), and only one of n gates is turned on by the output of the control circuit, and the oscillation frequency of the oscillation circuit is controlled according to the RC value of the gate. It has a configuration that can be used. Since the digital PLL circuit of the present invention can digitally control everything from the phase comparison to the oscillation operation, low power consumption can be achieved, and high integration can be achieved because the circuit is constituted by CMOS elements. Further, as described in the above-mentioned subject, the oscillation circuit portion is formed by the selector using the CMOS.
Instead of switching the number of inverter stages, the same CMO
The oscillation frequency is controlled by adjusting the RC value of the output transfer gate with the number of S inverters.
It becomes possible to control the phase of the oscillation frequency with a smaller delay time.

[0009]

FIG. 1 shows an embodiment of the present invention. The digital PLL circuit of the present invention is suitable for manufacturing using CMOS integrated circuit technology. In the embodiment of FIG. 1, the input digital clock signal CKI is input to a first input of a digital phase comparison circuit 11, and the phase is compared with a second input signal of the phase comparison circuit 11, and the phase comparison circuit 11 A U / D signal is output to the control circuit 12. The control circuit 12 receives the U / D signal and outputs an n-bit control signal CTL. The control circuit 12 sets an arbitrary one bit in advance, shifts the set bit to any adjacent bit according to the logical value of the U / D signal, and outputs it as an n-bit output signal CTL. The oscillation circuit 13 receives the control signal CTL as an input, controls the oscillation frequency of the output clock signal CKO of the oscillation circuit 13, and outputs it. The output clock signal CKO of the oscillation circuit 13 is
Used as a second input of the above-described phase comparison circuit 11,
The phase is compared with the input clock signal CKI.

FIG. 3 is a circuit diagram of the oscillation circuit 13 of the present embodiment.
Shown in The oscillating circuit 13 includes two CMOS inverters connected in series, a switching circuit in which units U1 to Un connected to transfer gates G1 to Gn are connected in parallel, and a CMOS inverter 31 arranged in a feedback loop in the switching circuit. And a ring oscillator in which CMOS inverters 32 and 33 are connected to the output node. The transfer gates G1 to Gn in FIG.
On / off is switched by [1] to CTL [n]. When the transistor sizes of G1 to Gn are adjusted so that oscillation occurs fastest when G1 is turned on and the lowest frequency is obtained when Gn is turned on, the frequency of the output clock signal CKO can be controlled by the CTL signal.

FIG. 2 shows a case where an n-bit L / R shift register with reset 12 'is used for the control circuit 12 in this embodiment. The n-bit L / R shift register 12 'in FIG. 2 has a reset input, and when the reset signal becomes active, an n-bit output signal CT
L [n: 1] is configured so that only one arbitrary bit is set and all other bits are reset. Further, the shift register receives a U / D signal as input, and if the logical value of the U / D signal is 1, the set bit is shifted to the upper side, and if the logical value of the U / D signal is 0, the set bit is shifted to the lower side. It is possible.

For example, assume that CTL [5] is initially set. When the transfer gate G5 is turned on, the oscillation circuit 13 oscillates at the frequency f5. The phase comparison circuit 11 compares the phases of CKO and CKI, and
If the phase is ahead of KI, the U / D signal is output with a logical value of 1, whereby the set bit of the CTL signal goes higher, that is, in this case, CTL [6] is newly set to a logical value of 1. , CTL [5] have a logical value of 0. In response to this, the oscillating circuit 13 turns off the transfer gate G5 by CTL [6], turns on the transfer gate G6 having an RC value larger than G5, and oscillates at a frequency f6 lower than f5. Also, CKO oscillating at f5
If the phase is behind the CKI, U / D becomes 0 and the set bit of CTL shifts down by one,
CTL [4] is set to logical one. CTL [4]
Turns on the transfer gate G4 and the oscillation circuit f
It oscillates at a frequency f4 faster than 5. As described above,
The frequency of the output clock signal CKO of the PLL circuit is set to CKI
Can be locked.

In this embodiment, as described above, the oscillation circuit 13
, The delay time in the loop in the oscillation circuit depends only on the two CMOS inverters and the RC value of the transfer gate, so that an oscillation circuit with less jitter can be provided.

[0014]

As described above, according to the present invention, the transfer gate for controlling the frequency of the oscillation circuit using the signal representing the advance or delay of the phase outputted from the phase comparison circuit by a logical value is provided. Complete digital PLL controlled digitally by switching
A circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing a case where a shift register is used for a control circuit 12 in the embodiment of FIG. 1;

FIG. 3 is an oscillation circuit 13 in the embodiment of FIG. 1 or FIG.
FIG. 3 is a circuit configuration diagram of FIG.

FIG. 4 is a block diagram of a conventional PLL circuit.

FIG. 5 is a block diagram of a conventional PLL circuit.

[Explanation of symbols]

 Reference Signs List 11 phase comparison circuit 12 control circuit 13 oscillation circuit 12 'L / R shift register G1 to Gn transfer gate 31 CMOS inverter CKI input clock signal CKO output signal CTL control signal U / D up / down signal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-95057 (JP, A) JP-A-7-95054 (JP, A) JP-A-2-2214 (JP, A) JP-A 61-950 65620 (JP, A) JP-A-4-165809 (JP, A) JP-A-5-315899 (JP, A) JP-A-6-140890 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H03L 7/06 H03K 3/03 H03L 7/089

Claims (1)

(57) [Claims] 1. A phase-locked oscillation circuit comprising: a phase comparison circuit; an oscillation circuit; and a control circuit that outputs a control signal for controlling an oscillation frequency of the oscillation circuit based on an output from the phase comparison circuit. The phase comparison circuit for comparing the phase of the input clock signal with the phase of the output signal of the oscillation circuit has a phase delay (or advance).
U / D expressed by a logical value 0 or 1 (or 1 or 0)
The control circuit has an n-bit output in which an arbitrary bit is in a set state and other bits are in a reset state, and sets a set bit based on a U / D signal from the phase comparison circuit. The oscillation circuit is composed of a circuit in which two inverters and one transfer gate are connected in series and n in parallel, and a ring oscillator using a feedback inverter, and each of the transfer gates is , Each having a different resistance value and capacitance value, according to the output of the control circuit,
A phase-locked oscillation circuit characterized in that one of the n transfer gates is turned on to control the frequency of the output signal.