JP3267199B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is to minimize the generation of residues such as black silicon when forming trenches for insulating isolation or forming capacitors in a semiconductor substrate such as a silicon substrate by dry etching. The present invention relates to a semiconductor wafer and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art It has been proposed, for example, in Japanese Patent Application Laid-Open No. 5-109882 to form a trench for element isolation in a semiconductor wafer, for example, a silicon wafer.
When forming a trench, an oxide film is
An opening is formed in the oxide film by photolithography corresponding to the trench formation region and used as an etching mask. Then, silicon is selectively etched by a reactive ion etching (RIE) process or the like in the trench formation region exposed by the oxide film to form a trench having a depth dimension of, for example, about 10 to 15 μm.

[0003]

In the conventional trench etching, however, there is a problem that contamination by particles is not small. When the cause of the contamination is sought, silicon is widely exposed to the periphery of the wafer during the trench etching. An area is created, and the area around FIG.
It has been found that this is caused by the generation of so-called black silicon as schematically shown in FIG. This will be described below.

In FIG. 13A, a silicon wafer subjected to a trench etching process has a so-called bonded SOI (Silicon On Insulator) structure in which two silicon wafers 1A and 1B are bonded via a buried oxide film 1C. Have With the oxide film 2 formed as a mask material for trench etching on the main surface 1a of the silicon wafer 1, an opening 2a for a trench is formed in the oxide film 2, and using this as a mask, reactive ion etching is performed. The trench 3 is formed by selectively etching the exposed silicon. If there is a portion 5 where silicon is widely exposed at the peripheral portion of the wafer 1 during the trench etching, black silicon 6 is likely to be generated, and during a subsequent process (for example, a cleaning process), the protrusion at the tip of the black silicon 6 is removed. It breaks and becomes particles. It has been found that the black silicon 6 tends to be generated even in a region where the width of the trench 3 is wide, as indicated by reference numeral 4 in the drawing.

The problem that black silicon 6 is likely to be generated during trench etching is not limited to a bonded SOI wafer as shown in FIG.
As shown in FIG. 13B, this also occurs when a trench for separating elements or a trench capacitor structure is formed in a bare silicon wafer. When the black silicon 6 is generated on the silicon wafer 1 and becomes a particle, it causes electrical insulation failure, and as a result, the production yield is adversely affected.

One of the causes of the large exposed silicon region 5 on the peripheral surface of the silicon wafer during the trench etching is that a trench opening 2a is formed in the oxide film 2 as a mask member for the trench etching process. There is a photolithography process to be performed. The photolithography process includes the steps of resist application, exposure / development, and etching. In this resist application, a silicon wafer 1 is rotated at a high speed by a spin coater or the like, and a resist material 7 such as a photoresist is applied to the silicon wafer. Since the resist material 7 that has reached the outer peripheral portion by the centrifugal force is partially applied from the peripheral portion of the silicon wafer 1 to the back surface side, there is a phenomenon (FIG. 14 ( a)). When the resist material 7 is applied to the peripheral portion of the silicon wafer 1,
Since the peripheral edge of the wafer comes into contact with a positioning portion in each process to cause particles, or in other devices such as an exposure apparatus, the generation of the particles causes a decrease in resolution at the time of exposure. It is necessary to remove by means.

In general, in order to remove the resist material 7 wrapping around the outer peripheral portion of the silicon wafer 1, a side rinse (edge rinse) process of applying a solvent to the peripheral resist at the time of applying the resist is performed. This is because, while the silicon wafer 1 is rotated, the resist material 7 is applied by dripping from the vicinity of the center of rotation, and the rinsing agent is dripped onto the peripheral portion, whereby the resist material applied on the outer peripheral portion of the silicon wafer 1 is applied. 7 is removed (see FIGS. 14B and 14C). As a result, the resist material 7 wrapped around the back surface is also peeled off at the same time.
The above-mentioned problem can be avoided. Similarly, a back rinse for applying a rinsing liquid to the back surface of the wafer during or immediately after application of the resist to remove the resist adhering to the back surface, or selectively exposing the periphery of the wafer to remove the peripheral resist during development. There is also a technique called peripheral exposure, which is to prevent the generation of particles due to lack of resist in the peripheral portion.

Therefore, in the photolithography process for forming the opening 2a in the mask oxide film 2 at the time of trench etching, the oxide film in the peripheral portion of the silicon wafer 1 from which the resist material 7 has been removed by the side rinsing process described above. 2 will also be removed by etching.
As a result, at the time of trench etching, a large area where silicon is exposed is formed on the outer peripheral portion of the silicon wafer 1, and the above-described black silicon is generated.

The present invention has been made in view of the above circumstances, and has as its object even if a side rinse process is performed when forming a trench opening in a mask member at the time of trench etching. It is another object of the present invention to provide a method of manufacturing a semiconductor wafer and a semiconductor device capable of preventing generation of black silicon in a trench etching step.

[0010]

In order to solve the above problems, according to the present invention, in a semiconductor wafer in which a trench is formed by dry etching, a semiconductor region is exposed in a region other than the trench forming region during the trench etching. It is characterized by being prevented from being performed.

More specifically, a semiconductor wafer to be subjected to dry etching for forming a deep groove or a deep hole in the chip forming region, and an oxide film to be etched during the dry etching in a peripheral region thereof. A thicker oxide film is formed before the dry etching. That is, since a thick oxide film is previously formed on the semiconductor wafer, the thick oxide film functions as an etching preventing insulating film when forming a trench (deep groove or deep hole). Even when the side rinse process is performed when forming the opening for the semiconductor, the semiconductor surface is formed on the main surface of the semiconductor wafer except for the opening for the trench of the mask insulating film formed in the chip forming region. There is no exposed part. Further, even if the thick oxide film disposed around the wafer during the trench etching is exposed on the wafer surface by the side rinsing process described above, its thickness is set to be larger than the oxide film that can be etched during the trench etching. Therefore, the oxide film remains in the outer peripheral region of the wafer even after the trench etching is completed. That is, when the trench etching process is performed, the semiconductor is not etched in a wide area other than the trench forming area, and generation of a residue such as black silicon can be suppressed.

The minimum thickness of the thick oxide film formed in the peripheral region may be set based on the product of the trench depth of the semiconductor during trench etching and the etching selectivity of the oxide film to the semiconductor. Further, it can be set in consideration of the amount of over-etching at the time of patterning the mask insulating film (at the time of forming the trench opening). By setting the thick oxide film, that is, the etching preventing insulating film, the etching preventing insulating film can be left even at the time of forming the trench,
Generation of a residue such as black silicon can be reliably prevented.

Even if a semiconductor is exposed in a region other than the trench forming region during the trench etching, if the size of the exposed region is set to be smaller than the width of the trench opening, black silicon or the like is used. The effect of suppressing the generation of residues can be expected. When the present invention is applied to a so-called SOI wafer formed by sticking two semiconductor wafers, a buried oxide film sandwiched between the two semiconductor wafers can be used as an etching preventing insulating film. After the alignment, the SOI wafer may be oxidized to selectively form a thick oxide film on the outer peripheral portion, thereby forming an insulating film for preventing etching.

Further, when the width of the trench opening of the mask insulating film formed on the semiconductor wafer is set to 10 μm or less, generation of a residue such as black silicon in the trench region can be prevented.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which the present invention is applied to a case where a bonded SOI wafer is used as a semiconductor wafer will be described below with reference to FIGS. When a semiconductor element is formed on a silicon substrate by element isolation, an element isolation trench is formed in a silicon wafer state. Further, before forming each semiconductor element in each element formation region, an element isolation trench is formed. In this case, as a silicon wafer to be used, a bonded SOI (silicon on insulat) as shown in a schematic cross section in FIG.
or) A wafer 11 is used. This SOI wafer 11
Is a buried oxide film 13 made of a thermal oxide film formed on the surface of the first silicon wafer 12 and buried in the SOI wafer, and a buried oxide film on the main surface side of the silicon wafer 11. It is composed of a second silicon wafer 14 attached with the film 13 interposed therebetween.

In this case, the buried oxide film 13 has a portion located on the outer periphery of the first silicon wafer 12 and serves as the etching prevention insulating film of the present invention.
3a, the thickness Dsio of the portion of the oxide film 13a for preventing etching is, for example, 0.8 to 1.1 [mu] m, depending on conditions of a trench etching process described later.
, Preferably in the range of about 0.9 to 1.0 μm.

In a general SOI wafer,
The thickness of the buried oxide film 13 on the first silicon wafer 12 is about 0.9 to 1.0 μm at a portion located at the interface with the second silicon wafer 14, which will be described later. Due to a problem in manufacturing an SOI wafer, the film thickness Dsio at the outer peripheral portion is actually about several tens percent smaller than that, and is as thin as about 0.4 to 0.5 μm. In the present embodiment, the thickness Dsio of the oxide film 13a at the outer peripheral portion is set to 0.9 to 0.9% so that the thickness Dsio of the outer peripheral portion functions as an oxide film for preventing etching as described later. The thickness of the buried oxide film 3 is set to, for example, about 1.2 μm so as to have a thickness of about 1.0 μm.

As a result, after the oxide film etching step (third step) and the trench etching processing step (fifth step), which will be described later, the underlying silicon is not exposed. The silicon is not exposed over a large area (especially in the outer peripheral portion of the wafer) and the etching does not proceed, so that the generation of black silicon can be suppressed.

Next, the details of the step of forming a trench for element isolation will be described with reference to FIGS.
In this case, the above-mentioned bonded SOI wafer 11 (see FIG. 1A) is used as a semiconductor wafer. As a first step, as shown in FIG.
Oxide film 1 as a mask insulating film on the upper surface side of the semiconductor device, that is, on the surface on which the second silicon wafer 14 is provided.
5 is deposited by a method such as a CVD method. If the oxide film for the mask is formed by thermal oxidation, the thickness of the oxide film 15 formed on the surface of the outer peripheral portion of the wafer where the oxide film 13a for etching prevention is previously exposed becomes insufficient. The film 15 needs to be a deposited film by a CVD method. Further, in this case, the thickness Dcvd of the mask oxide film 15 to be formed is set to be about 1.0 μm. The set value of the film thickness is set to be sufficiently larger than the film thickness of the oxide film that is slightly etched together with silicon in a trench etching process described later. In the outer peripheral portion of the SOI wafer 11, the underlying oxide film 13 is used as an oxide film 13a for preventing etching, and a mask oxide film 15 is further laminated thereon. The thickness becomes about 2.0 μm.

Next, as a second step, the SOI wafer 1
A photoresist 16 as a resist material is applied to the surface on which the one mask oxide film 15 is formed, and is patterned by photolithography. In this case, the photoresist 16 is applied by dripping the photoresist 16 in a liquid form using a general spin coater.
The photoresist 16 remaining on the outer peripheral portion is removed by the above-described side rinsing process at the time of or immediately after the application.

In the side rinsing process, the developing solution is dropped on the outer peripheral portion of the photoresist 16 immediately after the application to remove the rinse, whereby the photoresist 16 wrapping around from the outer peripheral portion to the back surface is removed, and a subsequent process is performed. The purpose is to improve the processing accuracy. Therefore, through the side rinsing process, the etching preventing oxide film 13a on the outer peripheral portion of the SOI wafer 11 is partially exposed. In this case, the positional relationship between the end of the photoresist 16 and the end of the second silicon wafer 14 is as follows.
The latter is always arranged inside in the plane of the wafer. This is to prevent the silicon surface from being exposed from the side surface of the end of the second silicon wafer 14 after the patterning of the mask oxide film 15 described later.

Subsequently, the photoresist 16 is exposed by using a mask corresponding to a portion to be subjected to the trench etching process, and the photoresist 16 is developed. As shown in FIG. Form a pattern. The pattern of the photoresist 16 thus formed is formed in the opening 15a in the mask oxide film 15 in the next step.
Is formed.

Next, as a third step, the mask oxide film 15 is subjected to dry etching using a mixed gas of CF ₄ , CHF ₃ , Ar, etc., as shown in FIG. Then, an opening 15a is formed in the trench formation portion. The width of the opening 15a at this time is, for example, 10 μm.
m is set so as not to exceed m. This is because black silicon is expected to be generated as the width of the opening is increased, as described later. In this dry etching process, in order to surely remove the mask oxide film 15 in a portion corresponding to the opening 15a, generally, the thickness Dcvd of the mask oxide film 15 to be etched is set to 30%. The conditions for over-etching of about% are set.

Therefore, in the dry etching process of the mask oxide film 15, the mask oxide film 15 in the portion where the photoresist 16 has been removed by the side rinse process on the outer peripheral portion of the SOI wafer 11 is simultaneously etched and removed. By the above-mentioned over-etching, the underlying oxide film 13a for preventing etching also has a thickness d.
Only one is etched. In this case, the thickness of the oxide film 13a for preventing etching is set to 0.1 as described above.
Since the thickness is set to about 9 to 1.0 μm, about 0.7 μm remains even after the over-etching period.

After the patterning of the mask oxide film 15, as a fourth step, the photoresist 16 remaining on the SOI wafer 11 is peeled off (see FIG. 1C). Thus, the opening 15a for trench etching is formed in the mask oxide film 15 on the SOI wafer 11. In the outer peripheral portion of the SOI wafer 11, the mask oxide film 15 has been removed by etching, but the etching prevention oxide film 13a formed as a base thereof has been left. It is in a state where the surface of the silicon wafer 12 is covered.

Next, as a fifth step, HBr, SiF
_4, the SF _6, He / O ₂ reactive ion etching (RIE) process using a reactive gas comprising a mixed gas such as, as shown in FIG. 2 (a), the opening formed in the mask oxide film 15 The silicon exposed at the portion 15a is selectively dry-etched (trench-etched).
In this reactive ion etching process, the etching selectivity of silicon is set to about 50 to 1 with respect to the oxide film. Accordingly, when the trench 17 is formed by etching silicon to the depth (TEsi) of the second silicon wafer, that is, about 15 μm, the oxide film 15 for masking and the oxide film for preventing etching at the outer peripheral portion are formed. 13a is also slightly etched.

Thereafter, the reaction products deposited on the side walls in the trenches are removed using an etchant such as HF, and then thermal oxidation is performed to form an oxide film 18 on the silicon surface in the trenches 17. Then, polysilicon 19 is deposited by a method such as LPCVD (low pressure CVD) so as to fill the trench 17, and the polysilicon deposited on a portion (wafer surface) other than the trench 17 is etched back by dry etching. As shown in FIG. 2B, the separation groove is buried.

Through these steps, the SOI wafer 11
A plurality of island-shaped silicon regions that are insulated and separated from each other are formed in the chip formation region, and a semiconductor element is formed in each of the island-shaped silicon regions. In the above description, the outline steps of this embodiment have been described focusing on the outer peripheral portion of the SOI wafer, but details such as a trench etching step and a semiconductor element formation step in a chip formation region are described in, for example,
See No. 109882.

As described above, in this embodiment, the film thickness Dsio of the oxide film 13a for preventing etching on the outer periphery of the wafer is set so that silicon is not exposed in regions other than the trench formation region during the reactive ion etching of silicon. And the opening width of the trench formation region is also 10 μm.
m, so that black silicon is not generated. As a result, it is possible to prevent generation of particles due to breakage of the projections of the black silicon in a later step, and to perform processing with high accuracy, thereby contributing to improvement in yield.

Next, the fact that black silicon is likely to be generated when silicon is exposed over a large area during trench etching will be described. As described above, as an etching mask for trench etching, an oxide film is generally used as a mask member so that etching selectivity can be obtained for silicon as a material to be etched. Then, a reactive dry etching process is designed in a process so as to increase the selectivity of silicon etching during trench etching. The etching mechanism of the reactive dry etching is that the reaction gas is supplied to the wafer in a plasma state, ions in the plasma are accelerated by the electric field and collide with the wafer surface, and Si exposed on the wafer surface is combined with F. And highly volatile S
It is considered that the etching proceeds due to volatilization as i-F. Here, it is considered that Br has an effect of damaging the Si surface and promoting the generation of Si-F. Naturally, the volatilization of Si-F also occurs on the surface of the oxide film, but is slower than the reaction on the surface of the Si film, so that the etching rate on the surface of the oxide film is small. On the other hand, when a large amount of oxygen is supplied to the reaction gas, the volatile Si-
F reacts with oxygen molecules to generate Si—O, which deposits on the wafer surface (on the mask oxide film), on the side walls of the trenches, etc., to prevent the progress of etching in the side wall direction, or to remove the mask oxide film. The speed can be suppressed, and the etching selectivity of silicon to an oxide film can be increased. However, if the selectivity of etching of silicon is set high, in other words, if the supply rate of oxygen is increased and the deposition rate of Si—O is increased, particularly in a large area where silicon is exposed, Is also high, the generation reaction of Si—O becomes excessive, and the probability of redepositing on the silicon to be etched surface increases. Then, the adhered reaction product acts as a mask member for etching, whereby the etching proceeds while leaving the reaction product adhered portion, and when such a re-adhered portion becomes excessive, As a whole, fine silicon protrusions are formed on the etched surface, which results in the generation of so-called black silicon as schematically shown in FIG.

Incidentally, it is conceivable to set the etching selectivity low enough not to generate black silicon by controlling the supply amounts of oxygen and fluorine, but in this case, the trench side surface is formed by the reaction product Si-O. Protection is also suppressed, and the cross-sectional shape of the trench becomes a so-called bowing in which the cross-sectional shape swells at the center, and as a result, when the trench is filled with polysilicon or the like in a subsequent process,
There is a problem that a so-called "su" hollow portion is generated, and the selection ratio cannot be easily reduced.

Therefore, in order to suppress the generation of columnar residues such as black silicon, as in this embodiment, etching is prevented so that silicon is not widely exposed outside the trench formation region (particularly the outer peripheral portion of the wafer) during trench etching. It is effective to set the film thickness Dsio of the oxide film for use 13a or to set the size of the exposed region to be smaller than the opening width of the trench opening 15a even if it is exposed.

Next, when forming the oxide film 13a for preventing etching as described above, the present inventors have found that the film thickness Dsi
Experiments were conducted to confirm how much o should be set. FIG. 3 shows this result, and the experimental conditions in this case are as follows. That is, in this experiment, the trench etching process was performed on the dimension of the thickness Dsio of the oxide film for etching prevention remaining on the outer peripheral portion of the silicon wafer, and as a result, the film thickness De of the oxide film remaining on the outer peripheral portion finally remained. Confirms the correlation of the degree.

In this case, the experimental conditions of each part are set as follows. Film thickness Dcvd of mask oxide film (formed by CVD) = 1.
5 μm Silicon etching depth dimension TEsi = 15 μm Etch selectivity k = 50-2 for silicon and oxide film
00 Amount of over-etching during patterning of oxide film for mask = + 30% As described above, under this condition, the film thickness Dsio of the oxide film for etching prevention needs to be at least about 0.63 μm, and this embodiment is not implemented. About 0.4-0.5μm in case
It has been found that under some circumstances, the underlying silicon may be exposed during the trench etching. The variation in film thickness on the wafer surface due to the process variation is 0.3%.
It turns out that it is sufficient to expect about μm.

Now, based on the above results, the required dimensions of the thickness Dsio of the oxide film for preventing etching will be estimated. First, considering the actual etching process, the condition is to satisfy the following expression (1).

[0036]

## EQU1 ## De = (Dcvd + Dsio)-(Dcvd + d1 + d2)> 0 (1) where De is the film thickness of the finally remaining etching preventing oxide film, Dsio is the film thickness of the etching preventing oxide film, D
cvd is the thickness of the masking oxide film, d1 is the thickness of the etching preventing oxide film etched in the dry etching process of the masking oxide film, and d2 is the film of the etching preventing oxide film etched in the trench etching process. It is thick.

Therefore, when the condition of the thickness Dsio of the oxide film for etching prevention is obtained from the above equation (1), the equation (2) is obtained.
become that way.

[0038]

## EQU2 ## Dsio> d (= d1 + d2) (2) Therefore, a dimension d that limits the film thickness Dsio will be obtained. The following relationship is set for each of the dimensions shown by the above equation (2).

[0039]

D1 = 0.3 × Dcvd (3)

[0040]

D2 = TEsi / k (4)

[0041]

Dcvd = 0.1 × TEsi (5) where TEsi is the depth dimension of the silicon to be etched by the trench etching process, and k is the etching selectivity of the silicon to the oxide film at the time of the trench etching.
si / TEsio) = (50-200). In the equation (5), the film thickness Dcvd is set by estimating about 10% of the silicon trench depth TEsi so that the mask oxide film remains on the silicon wafer surface during the trench etching. , The minimum value can be set using the trench depth TEsi and the selectivity k.

Therefore, when the value of d is obtained by substituting the relations of the above equations (3) to (5) into the equation (2), the following equation (6) is obtained.

[0043]

D = (0.03 + 1 / k) × TEsi = (0.035-0.05) × TEsi (6) From the above results, the value obtained when the dimension of TEsi is 15 μm is estimated and calculated. From the equation (6), d is equal to 0.
The dimension is between 525 μm and 0.75 μm. From this, it can be seen that a value substantially matching the result of the experiment is obtained. Next, a practical value of Dsio that satisfies the relationship of equation (2) will be estimated. In consideration of the above-described manufacturing variation, the thickness is to be formed to be about 0.3 μm. In this case, the thickness Dsio of the oxide film 13 a for etching prevention is about 0.8 μm to 1.1 μm. It is understood that it is preferable to perform

That is, as described in this embodiment, the thickness of the etching preventing oxide film 13a is 0.9 to 1.0 μm.
The degree (0.8 to 1.1 μm) is set on this basis. Incidentally, if the film formation accuracy in manufacturing is improved, it may be set to a dimension larger than the above-mentioned dimension d, and conversely, the estimated film thickness Dsio (= 0.8 to 1.1 μm)
It goes without saying that a dimension larger than m) can be used.

In the first embodiment, the second
The thickness of the buried oxide film is controlled so that the oxide film thickness Dsio on the outer periphery of the wafer becomes a film thickness remaining after the trench etching according to the thickness of the silicon wafer, that is, the trench etching depth TEsi. However, this point will be described below. A method for manufacturing the bonded SOI wafer 11 will be briefly described with reference to FIGS. First, a first silicon wafer 12 serving as a base
A thermal oxide film serving as a buried oxide film 13 is formed on the surface of
Is prepared (see FIG. 4A), and their mirror surfaces are bonded to each other by a known direct bonding method in a clean atmosphere and then annealed (see FIG. 4B). And the second
After the surface of the silicon wafer 14 is ground and thinned (see FIG. 4C), the outer peripheral portion 14A is ground to prevent edge chipping (see FIG. 4D). Thereafter, the masking tapes 100a and 100b are applied to the upper and lower surfaces of the bonded wafer, respectively (see FIG. 4E).
Then, the outer peripheral portion of the second silicon wafer 14 is removed by wet etching with a chemical solution (see FIG. 4F), and after the masking tapes 100a and 100b are peeled off, final polishing is performed from the surface of the second silicon wafer 14. This is performed (see FIG. 4G) to obtain a bonded SOI wafer 11 having an SOI layer having a desired thickness (TEsi).

During the production, the thickness Dsio of the oxide film on the outer peripheral portion is several tens percent smaller than the thickness of the buried oxide film on the central portion of the wafer as described above. That is, as shown in FIG. 5, the thickness of the oxide film 13 formed on the outer peripheral surface of the first silicon wafer 12 is
It becomes thinner (T _A <T sio) than the region where the second silicon wafer 14 is present on the surface, and becomes thinner (T _B <T _A ) as it approaches the outer periphery. This is due to the wet etching of the wafer edge in the step of FIG. 4 (f), and also the over-etching to completely remove silicon from the outer peripheral surface at that time.

In the first embodiment, this wet etching (0.8 to 1.1 μm) is required to ensure the film thickness Dsio (0.8 to 1.1 μm) necessary for the outer peripheral oxide film to function as the etching preventing oxide film 13a. The film thickness of the buried oxide film 13 is set in consideration of the etching amount in the step (f) of FIG.
That is, as shown in FIG. 6, the thickness of the thermal oxide film before bonding is increased to about 1.2 μm in advance (T ′> Tsio).
).

As another modification, the film thickness after the bonding step shown in FIG. 4B is ensured so that the film thickness Dsio necessary to allow the oxide film on the outer peripheral portion to function as the oxide film 13a for preventing etching can be secured. A method in which the annealing is changed from an inert atmosphere to an oxidizing atmosphere to selectively increase the thickness of the oxide film at the outer peripheral portion of the wafer from Tsio to T ″ (FIG. 7)
(See (a) and (b)) and increasing the amount of grinding in the grinding step of FIG. 4 (c) (thinning Tsi) to reduce the etching amount VEsi of the outer periphery of the wafer in the wet etching step of FIG. 4 (f). A reduction method (see FIGS. 8A and 8B) can be adopted.

As shown in FIG. 6, the most effective method is to increase the thickness of the oxide film before bonding as described in the first embodiment, but the oxide film formed by thermal oxidation is most effective. There is a problem that the thickness is limited to about 1.3 μm and the throughput becomes lower. Further, it is considered that an oxide film is formed on the second silicon wafer side. Inferior bondability, poor bondability when deposited by CVD instead of thermal oxide film,
Further, considering that the heat dissipation is deteriorated by increasing the thickness, the thickness of the oxide film is made as thick as possible by the method shown in FIG. 6 and the method shown in FIGS.
The oxide film on the outer periphery of the wafer is an oxide film 13a for preventing etching
The manufacturing process of the bonded SOI wafer 11 may be adjusted so that the film thickness Dsio necessary for functioning as a function can be secured.

Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, a normal bare silicon wafer 20 is used instead of the SOI wafer 11. That is, the present invention relates to a case where a trench for insulating isolation or forming a capacitor is formed in the silicon wafer 20. Hereinafter, the second embodiment will be described in accordance with the manufacturing steps shown in the drawings.

First, a thin pad oxide film 21 is formed on the surface of a normal silicon wafer 20 shown in FIG. 9A by a CVD method, thermal oxidation, or the like (see FIG. 9B). This pad oxide film 21 is formed to prevent defects due to stress from a silicon nitride film described later. Then, as shown in FIG. 9C, a silicon nitride film 22 is formed thereon by a predetermined thickness by LPCVD or the like. The silicon nitride film 22 is used as a mask member in a LOCOS step in a later step. Next, a photoresist 23 is applied to the wafer surface using a normal spin coater or the like, and the above-described side rinsing process, peripheral exposure, and development process are performed, and as shown in FIG. The photoresist 23 is removed. In the step shown in FIG. 9D, first, as shown in FIG. 10A, the photoresist applied to about 3 mm on the outer periphery of the wafer by the side rinsing process and the photoresist wrapped around the back surface are sprayed with a rinsing liquid. In the subsequent peripheral exposure, the photoresist 23 around the wafer including the orientation flat portion of the wafer is removed at the time of development, as shown in FIG. 10B. Then, the exposed portion of the silicon nitride film 22 in the outer peripheral portion is removed by dry etching (see FIG. 11A).

Then, after the photoresist 23 is stripped off, the oxidation is performed by using the silicon nitride film 22 disposed at a portion other than the outer peripheral portion of the silicon wafer 20 as a mask (LOCOS step), so that the oxide film 24 for etching prevention becomes zero. It is formed with a film thickness of about 0.9 to 1.0 μm (about 0.8 to 1.1 μm) (see FIG. 11B). Thereafter, the silicon nitride film 22 used as a mask member is removed by an etching process.

Next, as a first step, a mask oxide film 25 is formed on the entire surface of the silicon wafer 20 by CVD.
It is formed by a method or the like (see FIG. 11C). The thickness of the mask oxide film 25 is set to about 1.0 μm in consideration of the trench depth, similarly to the first embodiment. An etching preventing oxide film 24 and a pad oxide film 21 having different thicknesses are formed on the surface of the silicon wafer 20 so as to cover the entire surface. There is a step.

Thereafter, as shown in FIG.
As a step, a photoresist 26 as a resist material is applied by photolithography to form a predetermined pattern corresponding to the trench formation portion. At this time,
In the process of applying the photoresist 26, since the side rinse process is performed as described above, a region where the photoresist 26 is not applied is formed on the outer peripheral portion of the silicon wafer 20. Subsequently, as a third step, FIG.
As shown in FIG. 7, openings 25a are formed in the mask oxide film 25 and the pad oxide film 21 corresponding to the pattern formed in the photoresist 26 by the dry etching process. At this time, the condition of the over-etching is set to be about 30% with respect to the thickness (about 1.0 μm) of the mask oxide film 25. Therefore, in the outer peripheral portion of the silicon wafer 20 from which the photoresist 26 has been removed in the above-described side rinsing process, after the mask oxide film 25 is etched off, the etching prevention oxide film 24 Part will be etched.

Next, as a fourth step, the photoresist 2
6 is peeled off. As a result, the silicon of the silicon wafer 20 for trench formation is exposed in the opening 25a using the mask oxide film 25 as a mask member. Subsequently, as shown in FIG. 12B, as a fifth step, trench etching is performed in the same manner as in the first embodiment by reactive ion etching to form a trench 27 in the silicon wafer 20. At this time, trench 2
7 has a depth dimension of, for example, about 15 μm, the etching selectivity k between silicon and the oxide film is set to 50 to 200, and the oxide film 24 for etching prevention on the outer peripheral portion of the silicon wafer 20 is partially formed. Will be etched.

Since the film thickness of the oxide film 24 for etching prevention is set so as to remain under the fifth step, similarly to the above-described first embodiment, the trench formation of the silicon wafer 20 is performed. The silicon outside the region is not etched, and therefore, no black silicon is generated. As a subsequent process relating to the trench 27, there is a polysilicon filling process as shown in FIG. 12 (c).
The description is omitted here because it is the same as the embodiment,
As a result, an oxide film 28 is formed on the inner wall portion of the trench 27, and the inside is filled with polysilicon 29.

Therefore, according to the second embodiment, the same effects as those of the first embodiment can be obtained. The present invention is not limited to the above embodiments, but can be modified or expanded as follows.
The semiconductor wafer can be applied to a normal silicon wafer, a CZ wafer, an epiwafer, or an embedded epiwafer.
The present invention is also applicable to semiconductor wafers other than silicon wafers.

The region where the oxide film for preventing etching is formed is not limited to the portion where the oxide film for mask is exposed by the side rinse process, but may be formed in advance in the portion where the oxide film for exposure is expected under other conditions. . Also, as a method of leaving an oxide film on the outer circumference during trench etching, a wafer holder that removes a resist on only the back surface of the wafer by back rinsing and pattern an oxide film for a mask so that a clamp ring does not cover the upper surface of the wafer during dry etching. If it is used, the removal of the mask oxide film due to the removal of the resist on the outer peripheral upper surface of the wafer is eliminated, and the mask oxide film can be used as an oxide film for preventing etching.

[Brief description of the drawings]

FIG. 1 is a schematic vertical sectional side view of a silicon wafer in each step of a first embodiment of the present invention.

FIG. 2 is a schematic vertical sectional side view of a silicon wafer in each step of the first embodiment of the present invention.

FIG. 3 is a correlation diagram between an initial formed film thickness of an etching preventing oxide film and a final film thickness after processing.

FIG. 4 is a schematic vertical cross-sectional side view of the wafer in each step for explaining the manufacturing steps of the bonded SOI wafer.

FIG. 5 is a schematic vertical cross-sectional side view of a wafer for explaining a film thickness distribution of an oxide film at an edge of the wafer.

FIG. 6 is a schematic vertical cross-sectional side view of the bonded SOI wafer used in the first embodiment, showing a characteristic portion in the manufacture of the wafer.

FIG. 7 is a schematic vertical cross-sectional side view of a wafer showing a characteristic part in manufacturing a bonded SOI wafer according to a modified embodiment of the first embodiment.

FIG. 8 is a schematic vertical cross-sectional side view of a wafer showing a characteristic part in the manufacture of a bonded SOI wafer according to a modification of the first embodiment.

FIG. 9 is a schematic vertical sectional side view of a silicon wafer in each step of the second embodiment of the present invention.

FIG. 10 is a schematic plan view of a silicon wafer in a step of FIG. 9D of the second embodiment of the present invention.

FIG. 11 is a schematic vertical sectional side view of a silicon wafer in each step of the second embodiment of the present invention.

FIG. 12 is a schematic vertical sectional side view of a silicon wafer in each step of the second embodiment of the present invention.

FIG. 13 is a schematic vertical sectional side view at an edge of a wafer showing silicon black generated at the time of trench etching.

FIG. 14 is a schematic vertical sectional side view or a plan view of a wafer used for explaining a side rinsing step.

[Explanation of symbols]

11 bonded SOI wafer (semiconductor wafer) 12 first silicon wafer 13 buried oxide film 13a oxide film for etching prevention (insulating film for etching prevention) 14 second silicon wafer 15 oxide film for mask (insulating film for mask) 15a Opening 16 Photoresist (resist material) 17 Trench 18 Oxide film 19 Polysilicon 20 Silicon wafer 21 Pad oxide film 22 Silicon nitride film 23 Photoresist (resist material) 24 Oxide preventing oxide film (Etching preventing insulating film) 25 Mask Oxide film (insulating film for mask) 25a opening 26 photoresist (resist material) 27 trench 28 oxide film 29 polysilicon.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-6-163341 (JP, A) JP-A-5-109883 (JP, A) JP-A-61-141171 (JP, A) JP-A-3-3 76118 (JP, A) JP-A-61-220333 (JP, A) JP-A-8-162395 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3065 H01L 21 / 822 H01L 21/76

Claims (6)

(57) [Claims] A first step of forming an insulating film for a mask on a main surface of a semiconductor wafer; a second step of applying a resist material to the insulating film for a mask to perform patterning; A third step of forming an opening for a trench by etching the insulating film for a mask using the resist material patterned by the mask as a mask, and a fourth step of removing the resist material on the semiconductor wafer.
Forming a trench having a predetermined depth in the trench opening of the semiconductor wafer by performing dry etching using the mask insulating film as an etching mask.
In the method of manufacturing a semiconductor device comprising the steps of: forming a region where a semiconductor is exposed on the main surface of the semiconductor wafer other than the trench opening in the process from the first step to the fifth step; Is assumed, the etching prevention insulating film is formed in advance corresponding to the region where the semiconductor is exposed, so that the semiconductor in that portion is not etched in the dry etching process in the fifth step. It is characterized in that it is covered with an insulating film or at least the exposed region of the semiconductor is an opening that is equal to or less than the width of the opening for the trench , and the insulating film for etching prevention is further characterized in that , The second step
Side performed after applying resist material at
Peripheral area where resist material is removed by the rinsing process
A method for manufacturing a semiconductor device, characterized by being formed in accordance with (1) . 2. A method of manufacturing a semiconductor device according to claim 2, wherein said etching preventing insulating film is separated by overetching after said mask insulating film is removed when said mask insulating film is etched in said third step. The expected thickness d1 of the insulating film, and the thickness d2 of the insulating film that is simultaneously etched when the semiconductor wafer is etched in the fifth step.
The thickness d (= d1 + d) of the sum of the thicknesses d1 and d2
2. The method for manufacturing a semiconductor device according to claim 1 , wherein the size is set to be larger than 2). 3. The semiconductor wafer is a semiconductor substrate formed by attaching a second semiconductor substrate for element formation to a main surface of a first semiconductor wafer on which the insulating film for etching prevention is formed in advance. 3. The method of manufacturing a semiconductor device according to claim 1 , wherein: 4. The semiconductor wafer according to claim 1, wherein a second semiconductor substrate for forming an element is attached to a main surface of the first semiconductor wafer, and a peripheral portion of the semiconductor substrate is selectively oxidized. claim, characterized in that by forming a film is obtained without a part of the etching preventing insulating film 1
4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3 . Wherein said etch stop insulating film, a method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that it is formed by a LOCOS method on the semiconductor wafer. 6. The semiconductor device according to any one of claims 1 to 5 wherein the width of the trench opening of the mask insulating film formed on a semiconductor wafer characterized in that it is set to 10μm or less Production method.