JP3266949B2 - Stepping motor control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stepping motor control circuit for a facsimile machine and the like, and more particularly to a stepping motor control circuit suitable for improving motor controllability by software.

[0002]

2. Description of the Related Art In a conventional stepping motor control circuit, the excitation phase is determined before the motor control is started, and the phase switching is not performed during the motor control. Also,
The motor stepping speed is controlled by slew-up / down and speed control by skipping four, three, and two with respect to the fixed clock. In such devices, the software had to always be involved in motor control. Related devices of this type include, for example, Japanese Unexamined Patent Application Publication No.
There is 123173.

[0003]

In the above prior art, the load of software is large, and there is a problem in motor controllability by software. SUMMARY OF THE INVENTION An object of the present invention is to provide a stepping motor control circuit which solves such problems and is suitable for improving controllability by software such as phase switching, through-up / through-down, excitation ON / OFF, and data request. Is to do.

[0004]

In order to achieve the above object, a stepping motor control circuit according to the present invention comprises: a shift register for generating driving pulses of a stepping motor in different excitation phases; and storing a motor stepping pulse speed as a counter value. A motor status register, a clock counter that counts a basic clock, a comparator that compares the value of the motor status register with the value of the clock counter, a step pulse generation circuit that generates a motor stepping pulse when the comparators match , Motor status register
A data set register that sets
The contents of the data set register are generated when the motor stepping pulse is generated.
And a data shift controller for shifting the
Characterized in that the motors state set value in the register was arbitrarily change the motor stepping pulses speed. Further, a clock selector for selecting a basic clock according to a clock selection bit set in the motor status register is provided. Further, by setting the data for a plurality of steps content to the motor state register, shifting the data to the motor status register, automatically plurality
A motor stepping pulse over a step can be generated . Further, the set counter values between the motor state registers constituting the data set register are compared, and if the values are equal, the shift of the data stored in the data set register by the data shift controller is stopped, and the step pulse generation circuit is caused to stop. A preset auto-loading comparator for prompting the generation of equally spaced motor stepping pulses is provided. If the data set in the data set register is the same for two consecutive steps , the data is used when the motor stepping is controlled by the data. Motor stepping pulse can be generated to drive the motor at a constant speed
The feature is that it has been enabled. When the data stored in the data set register falls below a predetermined number of steps due to a shift accompanying the motor stepping, a DMA request generating circuit for generating an interrupt to the system is provided, and the CPU is provided with an interrupt. to generate the data set register is characterized in that to allow notification became vacant. Further, a register for an auto-preset loading end bit for instructing cancellation of the constant velocity motion is provided. Further, in a circuit for controlling the driving of the stepping motor, a shift register for generating a driving pulse of the stepping motor in a different excitation phase,
A motor status register that stores a motor stepping pulse speed as a counter value, a clock counter that counts a basic clock, a comparator that compares the value of the motor status register with the value of the clock counter, and when the comparators match. , multiple and step pulse generating circuit for generating a motor stepping pulses, the clock selection bits set in the motor status register, a clock selector for selecting the clock, the motor status register
A data set register having steps, a data shift controller that shifts the contents of the data set register every time a motor stepping pulse is generated, and data stored in the data set register that is shifted in a predetermined step by the motor stepping. A DMA request generating circuit which enables an interrupt to be generated in the CPU when the number becomes equal to or less than the number . Further, a control register for setting control information including bits indicating motor start, excitation OFF, and constant speed driving of the motor is provided, and the CPU can recognize the control information and perform motor control.

[0005]

In the present invention, the shift registers for different excitation phases are shifted in synchronization with the motor, so that the motor rotates smoothly even if the excitation phase is suddenly changed, and the phase is switched without lowering the image reading accuracy. Can be. Further, since the counter value set by the software is arbitrary, the stepping pulse interval of the motor can be freely set, and thus the speed of the motor can be arbitrarily set. Further, since the basic clock can be selected, the motor speed can be finely set by software.
For example, in a copying machine or the like, it is possible to match the recording cycle to a printer system. Further, it is easy to change the reduction ratio to an independent printer system. In addition, since the software has a data set register extending over several lines, the software can finish writing the motor control data (DMA or normal write operation) at a time, so that the motor controllability by the software is dramatically improved. Also, if only the motor through-up is set by software using the preset auto-loading comparator, automatic control is performed by hardware at the time of constant speed driving, so that the load of software is greatly reduced. Further, the software can know how much the data set in the data set register has been shifted and used, so that the software does not have to go to read each time, and the load on the software can be reduced. By providing a control register, instructions from the CPU can be easily set,
Since the CPU can know the state of motor control, motor controllability by software is improved. Further, the constant speed driving of the motor can be released by software.

[0006]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a stepping motor control circuit of a facsimile apparatus according to one embodiment of the present invention. The two-phase shift register 1, the 1-2-phase shift register 2, and the W1-2-phase shift register 3 shown in FIG. 1 automatically generate a 2-phase / 1-2-phase / W1-2-phase excitation pattern, respectively. The pattern is shifted one by one by the shift pulse (SP). This 2-phase / 1-2-phase / W1
The -2 phase is as shown in FIG. 2, and in FIG.
Represents two phases of motor phase excitation, (b) represents 1-2 phases, and (c) represents W
Phases 1-2 are shown. Motor (4-phase motor)
The reference signal for control is as shown in FIG. 3, and the reference voltages VrefA and VrefB for the phase excitation are a hexadecimal cycle counter (not shown) and each of the shift registers 1 to
Create from the output of 3. The initial value (initial position of the motor) of each excitation phase is (A, -A, B, -B) = (1, 0,
1, 0) and are set at the time of reset and at the time of clearing. Also, the 1/2 frequency divider circuits 4 and 5 in FIG.
The shift pulse entering the 1-2 phase is divided by の of the shift pulse entering the W1-2 phase, and the shift pulse entering the two phases is reduced to 1-2.
The frequency is set to パ ル ス the frequency of the shift pulse for the phase. As a result, as shown in FIGS. 4 and 5, the pulses generated from each of the shift registers 1 to 3 are simultaneously shifted in synchronization with the rotation of the motor, so that even when the excitation phase is suddenly changed while the motor is being driven. , Without stopping the motor,
Keep running smoothly. In FIG. 4, (a)
Indicates the relationship between the motor position and the motor control signal (reference signal) in each cycle of the excitation phase W1-2 phase,
FIGS. 4B and 5 show 1-2 phase and 2 phase, respectively. The W1-2-phase reference voltage generation circuit 6, the 1-2-phase reference voltage generation circuit 7, and the two-phase reference voltage generation circuit 8 of FIG. 1 generate a reference voltage for driving the motor. ,
Similarly to the above, the 1/2 frequency dividers 9 and 10 use the W1-2 phase,
Synchronize the first and second phases. Also, the selector 11
The selector 12 switches the W1-2 phase, the 1-2 phase, and the two-phase excitation, and switches the reference voltage of each phase excitation. The selector 13 switches between forward rotation / reverse rotation pulses. The selector 14 switches the clock signal to be counted, and the clock counter 15 counts the clock signal.

The data set register 16 is a register for setting motor control data, and is set by writing by DMA or ordinary software. The data written here is, as shown in FIG.
Motor excitation mode (forward / reverse, W1-2 phase, 1-2 phase,
2), a basic clock selection bit, and a motor step count value indicating how many basic clocks are counted before a motor shift pulse is generated. The contents of the data set register 16 are shifted by the data shift controller 18 to obtain the motor state register 1.
Enter 7. The content of the motor status register 17 is the status of the currently loaded motor. Further, the motor step counter value held in the register 17 is constantly compared with the clock counter 15 by the comparator 19, and when they match, a step pulse is generated by the step pulse generating circuit 20. This step pulse corresponds to the above-mentioned automatic excitation generation block (shift register 1).
To 3, reference voltage generating circuits 6 to 8).
The motor is driven. Further, the preset auto-loading comparator 21 notifies the data shift controller 18 of the pulse rate after motor through-up.
As a result, when the same value is written to the data set register 16, the hardware automatically drives the motor at a constant speed, so that the load of software after motor through-up can be reduced. The DMA request generation circuit 22
Is a circuit for generating an interrupt pulse (circuit for generating a register empty interrupt pulse) for notifying the CPU that the data set register 16 has become empty due to the shift. The DMA request interval register 24
The data set register 16 is shifted according to the value to be set.
Generates an interrupt pulse when it becomes empty
Can be set. First, the step pulse counter 23
Step pulses are counted. For example, DMA request
It is assumed that 3 is set in the strike interval register 24. The result
As a result, the step pulse counter 23 counts 1 or 2.
When the DMA request generation circuit 22
The signal does not go, but at the third pulse the signal is a DMA request.
The strike comparator 25 opens the through gate 26 and
No. passes. According to this, DMA request occurrence times
Road 22 issues an "INT empty signal". Also, as shown in FIG. 7, the control register 23 has a bit to be set when starting the motor, an auto preset load end bit for canceling the motor constant speed movement, and a bit for knowing that the software is moving at a constant speed. The speed bit, the current control bit, the excitation OFF bit, and the like are retained, and controllability by software is further improved. For example, when the motor is automatically driven at a constant speed, the software can predict the constant speed based on the value of the data set register 16, but can also confirm the constant speed driving based on the constant speed bit.

Next, the relationship between the motor step counter value during motor driving (during copying), the magnification, and the pulse rate will be described with reference to FIG. 8, the horizontal axis represents the motor speed (dpi) and the magnification (%), the vertical axis represents the number of pulses required per unit time to drive the motor, and n represents the counter value set in the clock counter 15. Show. In this embodiment, as shown by the arrow, when the motor speed is gradually increased, the through-up / through-down can be performed smoothly only by writing the counter value n and the excitation phase to the data set register 16. Therefore, it is possible to change the scanner motor speed by changing the scanner motor speed from a state in which the recording system is driven at a constant speed at a speed of 400 dpi (magnification 100%). Further, by appropriately selecting the counter value n and the basic clock, it is possible to change the magnification in increments of 1%. In this embodiment, the case where a four-phase motor is used has been described. However, the same effect can be obtained when there is a different excitation method for one type of motor. For example, in the case of a 5-phase motor, 4-phase, 4-5-phase, 5-phase excitation may be used.

[0009]

According to the present invention, since the shift registers for different excitation phases are shifted in synchronization with the motor, the motor rotates smoothly even if the excitation phase suddenly changes to a different excitation phase, and the image reading accuracy is improved. Phase can be switched without dropping. Further, the motor controllability by software can be improved by a data set register, a control register, and the like, and the load on software can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a stepping motor control circuit of a facsimile apparatus according to one embodiment of the present invention.

FIG. 2 is a diagram showing a motor excitation phase in one embodiment of the present invention.

FIG. 3 is a diagram showing a reference voltage in one embodiment of the present invention.

FIG. 4 is a diagram showing motor control signals of each motor excitation phase in one embodiment of the present invention.

FIG. 5 is a diagram showing motor control signals of each motor excitation phase in one embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a data set register in one embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a control register in one embodiment of the present invention.

FIG. 8 is a diagram showing a relationship between a motor step counter value, a scaling factor, and a pulse rate during motor driving according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 2-phase shift register 2 1-2-phase shift register 3 W1-2-phase shift register 4 1/2 frequency divider 5 1/2 frequency divider 6 W1-2 phase reference voltage generator 7 1-2 phase reference voltage generator Circuit 8 Two-phase reference voltage generating circuit 9 1/2 frequency divider 10 1/2 frequency divider 11 selector 12 selector 13 selector 14 selector 15 clock counter 16 data set register 17 motor status register 18 data shift controller 19 comparator 20 step pulse Generation circuit 21 Preset auto-loading comparator 22 DMA request generation circuit 23 Control register

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-57-91697 (JP, A) JP-A-1-274696 (JP, A) JP-A-58-198198 (JP, A) JP-A-2- 207659 (JP, A) JP-A-63-103697 (JP, A) JP-A-2-26399 (JP, U) JP-B-63-34720 (JP, B1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02P 8/00 H04N 1/04

Claims (8)

(57) [Claims] 1. A circuit for controlling the driving of a stepping motor, comprising: a shift register for generating drive pulses for the stepping motor in different excitation phases; a motor state register for storing a motor stepping pulse speed as a counter value; A counter that counts the clock counter, a comparator that compares the value of the motor status register with the value of the clock counter, a step pulse generation circuit that generates a motor stepping pulse when the comparators match, and a motor status register. For multiple steps
A data set register to be set and the data set register
Shift the contents of the register each time the motor stepping pulse is generated
That a data shift controller, a stepping motor control circuit, characterized in that was arbitrarily change the motor stepping pulses speed by the value set in 該Mo over data status register. 2. The stepping motor control circuit according to claim 1, further comprising a clock selector for selecting a basic clock according to a clock selection bit set in said motor status register. 3. The motor set register includes a plurality of stages.
Tsu by setting up of data, the data shifted to the motor status register, automatically stepping motor control according to claim 1, wherein that you have to be generated for motor stepping pulses across multiple step circuit. 4. A set counter value between the motor status registers constituting the data set register is compared. If the values are equal, the shift of the data stored in the data set register by the data shift controller is stopped. The generation circuit is provided with a preset auto-loading comparator that prompts the generation of equally spaced motor stepping pulses. If the data set in the data set register is the same for two consecutive steps , the data is used to control the motor stepping. the motor stepping pulses allows occur to drive at a constant speed motor at a speed of the data
Stepping motor control circuit according to claim 3, wherein a was. 5. The method according to claim 1, wherein the data stored in the data set register is a predetermined number of steps in a shift accompanying the motor advance.
A DMA request generating circuit for generating an interrupt to the system when the following condition is satisfied is provided, and an interrupt is generated for the CPU to enable notification that the data set register becomes empty. A stepping motor control circuit according to claim 4. 6. A stepping motor control circuit according to claim 4, further comprising a register for an auto-preset loading end bit for instructing release of said constant velocity movement. 7. A circuit for controlling driving of a stepping motor, comprising: a shift register for generating drive pulses for the stepping motor in different excitation phases; a motor status register for storing a motor stepping pulse speed as a counter value; A counter that counts the clock count, a comparator that compares the value of the motor status register with the value of the clock counter, a step pulse generation circuit that generates a motor stepping pulse when the comparator determines a match, and a motor status register. A clock selector for selecting a clock according to the set clock selection bit, a data set register having the motor status register for a plurality of steps , and shifting the contents of the data set register every time a motor stepping pulse is generated Data shift controller And over La, data stored in the data set register, a predetermined shift caused by the motor stepping
A stepping motor control circuit, comprising: a DMA request generating circuit for generating an interrupt to the CPU when the number of steps becomes equal to or less than the number of steps . 8. The stepping motor control circuit according to claim 7, further comprising a control register for setting control information including bits indicating motor start, excitation OFF, and constant speed driving of the motor, and wherein the CPU recognizes the control information. A stepping motor control circuit characterized in that motor control can be performed by using a motor.