JP3265904B2 - Driving method of flat display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a flat display panel for displaying an image by discharge light emission.

[0002]

2. Description of the Related Art As this type of flat display panel, for example, an AC plasma display panel (hereinafter referred to as an AC PDP) has been proposed.

As an AC type PDP, a two-electrode type ADP which performs an address discharge (selective discharge) and a sustain discharge with two electrodes is used.
It can be classified into a C-type PDP and a three-electrode type AC PDP that performs an address discharge using a third electrode.

Here, an AC type PDP for performing color display
Although the phosphor emits a desired color by exciting the phosphor with ultraviolet rays generated by the discharge, this phosphor has a drawback that it is weak against the impact of positively charged cations generated by the discharge.

However, the AC-type PDP of the two-electrode type has a configuration in which cations generated by discharge directly hit the phosphor, and the cations generated by discharge may cause deterioration of the phosphor. Has defects.

Therefore, an AC type PDP for performing color display
In general, a three-electrode structure using surface discharge, which is a structure that can avoid the impact of cations generated by electric discharge on the phosphor, is generally used.

FIG. 9 shows a three-electrode / surface-discharge type AC.
FIG. 10 is a schematic plan view showing an example of a type PDP, and FIG.
The PDP main _{body, 2 1, 2 2 ··· 2} N are address electrodes formed in parallel in a direction perpendicular to the display line.

Reference numeral 3 denotes an X electrode which forms one sustain electrode formed so as to have a portion parallel to the display line for each display line, 4 ₁ , 4 ₂ ... 4 _M denotes each display of the X electrode 3. This is a Y electrode that forms the other sustaining electrode paired with the line portion.

5 ₁ , 5 ₂ ... 5 _{N + 1} are barriers (ribs, barriers) formed between address electrodes for breaking horizontal spatial coupling of display cells, and 6 is a display cell. In this example, the disconnection of the spatial connection in the vertical direction of the display cell is performed by optimizing the distance between the electrodes.

FIG. 10 is a schematic sectional view taken along an address electrode of the AC PDP shown in FIG. 9, and FIG. 11 is a schematic sectional view taken along a Y electrode of the AC PDP shown in FIG.
10 and 11, 7 is a front glass substrate, 2 _i , 2
_{i + 1} , 2 _{i + 2} are address electrodes, 4 _j , 4 _{j + 1} are Y electrodes,
5 _i , 5 _{i + 1,} 5 _{i + 2} , 5 _{i + 3} are barriers, and 6 _{j + 1.i} is a display cell.

In the X electrode 3 and the Y electrodes 4 _j , 4 _{j + 1} , 8, 9 _j , 9 _{j + 1} are transparent electrodes made of an ITO film containing indium oxide as a main component, 10, 11 _j , 11 _j . _{j + 1} is a low-resistance bus electrode for preventing a voltage drop at the transparent electrodes 8, _9j , _{9j + 1} , respectively.
11 _j and 11 _{j + 1} are formed of copper Cu, chromium Cr or the like.

Reference numeral 12 denotes a dielectric layer made of glass;
Reference numeral 3 denotes an MgO film serving as a protective film for protecting the surface of the dielectric layer 12.

Reference numeral 14 denotes a rear glass substrate facing the front glass substrate 7, and 15 _i , 15 _{i + 1} , and 15 _{i + 2} cover address electrodes 2 _i , 2 _{i + 1} , and 2 _{i + 2} , respectively. The formed phosphors, and these phosphors 15 _i , 15 _{i + 1} , 15
_{i + 2} has red, green, and blue emission characteristics, respectively.

[0014] In this example, the front surface and the surface of the MgO film 13 for protecting the glass substrate 7 the dielectric layer 12 formed on, the back glass substrate 14 which is formed on the barrier 5 ₁ ~5 N + ₁ roof The front glass substrate 7 and the rear glass substrate 14 are assembled such that the substrates adhere to each other.

FIG. 12 is a block circuit diagram schematically showing a peripheral circuit for driving the AC PDP shown in FIG. 9. In FIG. 12, reference numeral 17 denotes the AC PDP shown in FIG.
8 address pulse A1 to the address electrodes 2 ₁ to 2 _N
An address driver 19 that supplies .about.AN is an X-side common driver that supplies an address pulse Pw and a sustain discharge pulse Ps to the X electrode 3.

[0016] 20 Y scan driver supplies a scan pulse Psc to the Y electrode ₄₁ to _M, 21 via the Y scan driver 20 Y electrode ₄₁ to sustain pulse to _M Ps Is a Y-side common driver.

A control circuit 22 controls the address driver 18, the X-side common driver 19, the Y-scan driver 20, and the Y-side common driver 21.

In the control circuit 22, reference numeral 23 inputs a dot clock CLOCK and display data DATA.
A display data control unit that controls the address driver 18 is a frame memory for temporarily storing display data for one frame.

Reference numeral 25 denotes a panel drive control unit for inputting a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC, 26 denotes a scan driver control unit for controlling the Y scan driver 20, 27 denotes an X side common driver 19 and Y
It is a common driver control unit that controls the side common driver 21.

FIG. 13 is a waveform diagram showing one example of a conventional driving method of the AC type PDP shown in FIG. 9, showing one subfield period. In this example, one subfield period is a reset period. , An address period, and a sustain discharge period. That is, this method of driving an AC PDP shows an example of a conventional method of driving an AC PDP by a separate address / sustain discharge period / write address system.

[0021] Here, FIG. 13A is the address electrodes 2 ₁ to 2 _N
13B is a driving waveform of the X electrode 3, and FIG.
The Y electrode 4 _first drive waveform, Figure 13D Y electrode 4 _{and second} driving waveforms, FIG. 13E shows a driving waveform of the Y electrode 4 _M.

[0022] That is, in the reset period, first, all the Y electrodes 4 ₁ to 4 _M are to 0V, and the address electrodes 2 ₁ to
2 _N , a voltage Vaw, for example, 100 V is applied, and a write pulse _PW with a voltage of Vs + Vw, for example, 330 V and an application time of 10 μs is applied to the X electrode 3, and the sustain discharge in the immediately preceding subfield is performed. Regardless of the lighting state during the period, discharge is performed in all display cells in the panel, and wall charges are accumulated in all display cells.

Next, the address electrodes 2 ₁ to 2 _N and X electrode 3
Is set to 0 V. As a result, in all the display cells in the panel, the voltage of the accumulated wall charge itself exceeds the discharge start voltage, and discharge is started.

This discharge is caused by the X electrode 3 and the Y electrodes 4 ₁ to 4 _M
Since there is no potential difference between them, no wall charge is formed, and the space charge self-neutralizes and the discharge is terminated.This self-erasing discharge causes the state of all display cells in the panel to change. A uniform state without wall charges is obtained, and the next address discharge can be stably performed regardless of the lighting state in the sustain discharge period of the immediately preceding subfield.

In the next address period, an address discharge for writing the display data DATA, that is, a display cell to be lit by performing a sustain discharge during the sustain discharge period in accordance with the display data DATA is selected. Are performed line-sequentially.

In this case, a voltage Vx, for example, 5
0V is applied, and the Y electrode 4 ₁ of the first display line is applied.
Scan pulse Ps of voltage -Vy, for example, -150 V
c is applied, and an address pulse A1 of a voltage Va, for example, 50 V, is selectively applied to an address electrode of a selected display cell.

The immediate result, the discharge between Although discharge between the address electrode and the Y electrode 4 _first display cell to be selected occurs, the X electrode 3 and the Y electrode 4 ₁ This priming as (priming) proceeds to thereby, the wall charges of the X electrode 3 and Y electrode 4 ₁ on the amount that can sustain discharge on the surface of the MgO film 13 of the selected display cells is accumulated.

Hereinafter, the other display lines will be sequentially described.
The same operation is performed, and new display data DATA
, And an address pulse A2... AN is supplied to the selected display cell.

In the next sustain discharge period, the Y electrode 4 ₁
４4 _M and the X electrode 3 alternately, the voltage is Vs, for example, 18
The sustain discharge pulse Ps of 0 V is applied to perform the sustain discharge, and the image display of one subfield is performed.

In the driving method of the address / sustain discharge separation type / write address system, the luminance is determined by the length of the sustain discharge period, that is, the number of times of supply of the sustain discharge pulse Ps.

FIG. 14 shows the AC type PDP shown in FIG.
In this example, a driving method for displaying 256 gradations is shown. In this example, one frame for displaying one complete image is composed of eight subfields SF1 to SF8. Incidentally, 29 _{1-29 3} 29 ₈ is an address line indicating a display line address discharge is performed.

Here, in subfields SF1 to SF8, the reset period and the address period have the same length, but the sustain discharge period has the same length.
The ratio is 1: 2: 4: 8: 16: 32: 64: 128.

Therefore, these subfields SF1
To SF8, a subfield for lighting the display cell is selected, so that 25 levels from 0 to 255 are selected.
The six levels of luminance differences can be displayed.

Here, an example of the actual time distribution is as follows. That is, the rewriting frequency of the screen is set to, for example, 6
Assuming 0 Hz, the time (length) of one frame is 16.6.
ms (1 / 60s).

If the number of sustain discharge cycles in one frame is, for example, 510, the number of sustain discharge cycles in each of subfields SF1 to SF8 is:
Subfield SF1 twice, subfield SF2 four times, subfield SF3 eight times, subfield S
F4 is 16 times, subfield SF5 is 32 times, subfield SF6 is 64 times, and subfield SF7 is 12 times.
Eight times, the subfield SF8 becomes 256 times.

The time for one sustain discharge cycle is set to 8
Assuming μs, the total number of sustain discharge cycles in one frame is 8 μs × 510 times = 4.08 ms, and eight reset periods and address periods are allocated in the remaining approximately 12 ms.

The reset period in each of the subfields SF1 to SF8 requires 50 μs, and the time required for an address cycle (scan per display line) is 3 μs. , 48
When there are 0 display lines, a time of 3 μs × 480 = 1.44 ms is required as an address period.

[0038]

Here, in the driving method of the AC type PDP shown in FIG. 13, the address discharge and the self-erase discharge are performed for all the display cells during the reset period, so that the wall charge is applied to all the display cells. It is said to create a uniform state without any.

As a result, at least two discharges are performed in the reset period of the next subfield regardless of the lighting state of the display cell in the sustain discharge period of the immediately preceding subfield. As shown, one frame is composed of eight sub-fields SF1 to SF8 and 256
In the case of performing the gradation display, the invalid light emission is performed 16 times in one frame.

Here, from the viewpoint of the display quality, when the level of the video signal is 0 V, it is desirable to perform a complete black display with no light emission. However, the conventional AC PDP shown in FIGS. In the driving method described above, the contrast ratio is set to about 50: 1 even in a dark room because there is invalid light emission of about 2% of the maximum luminance.

As a result, in the conventional AC PDP driving method shown in FIGS. 13 and 14, when the maximum video signal level has a luminance of, for example, 200 cd / m ² , the luminance of black display is In a dark room, it is 4 cd / m ² , and there is a problem that a good contrast ratio cannot be obtained.

The conventional AC shown in FIGS.
In the driving method of the type PDP, white light emission of about 2% is always present.
% Of white color, resulting in poor color reproducibility.

In view of the above, the present invention relates to a method of driving a flat display panel for displaying an image by discharge light emission, which reduces ineffective light emission, improves contrast ratio and color reproducibility, and improves display quality. It is an object of the present invention to provide a method of driving a flat display panel which can be achieved.

[0044]

A method of driving a flat display panel according to the present invention is directed to a flat display panel having at least a pair of electrodes for performing discharge light emission and a plurality of display cells defined by the pair of electrodes. A display panel driving method, including a reset period for erasing wall charges in a display cell, and a discharge period for causing discharge light emission in an arbitrary display cell; in the reset period, The erasing discharge is performed only on the display cells that have been lit during the immediately preceding discharge period.

[0045]

According to the present invention, in the reset period,
Erasing discharge is performed only on the display cells that were lit in the immediately preceding discharge period, and erasing discharge is not performed on the display cells that were in the non-lit state during the immediately preceding discharge period. Can be reduced.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
The AC-type PDP shown in FIG.
Will be described by taking as an example the case of driving so as to perform 256 gradation display.

FIG. 1 is a time chart for explaining a first embodiment of the present invention. In the first embodiment, one complete image is displayed. The frame has eight subfields SF1 to SF1.
SF8. Note that 29 _{1 to} 29 ₃ , 29
₈ is an address line as described above.

In these subfields SF1 to SF8, the reset period and the address period are respectively
Although the length is the same, the length of the sustain discharge period is 1:
The ratio is 2: 4: 8: 16: 32: 64: 128.

In the first embodiment, the driving method shown in FIG. 2 is executed in subfields SF1 to SF8.

[0050] Here, FIG. 2A is a driving waveform of the address electrode 2 ₁ to 2 _N, FIG. 2B is a driving waveform of the X electrode 3, Figure 2C Y electrode 4 _first drive waveform, FIG. 2D driving of the Y electrode 4 ₂ Waveform, Figure 2
E indicates a drive waveform of the Y electrode 4 _M.

That is, in the reset period, first, all the Y electrodes 4 ₁ to 4 _M are set to 0 V, and the address electrodes 2 ₁ to 2 _N
The voltage Vaw, for example, applies a 100 V, the X electrode 3, the voltage Vs + Vw, for example, a 330V, the application time by applying a write pulse P _W to 1 [mu] s, then the address electrodes 2 ₁ to 2 _N and The potential of the X electrode 3 is set to 0V.

The application of the address pulse Pw does not perform the address discharge and the self-erase discharge on the display cell which was in the non-lighting state during the sustain discharge period of the immediately preceding subfield, and does not perform the discharge during the sustain discharge period of the immediately preceding subfield. An object of the present invention is to cause a writing discharge and a self-erasing discharge to be performed only on a display cell that has been turned on, thereby to make all display cells have no wall charge.

In this driving method, when a wall pulse acting in a manner superimposed on the address pulse Pw is present and when no wall charge is present, when a voltage pulse exceeding the start of discharge is applied, the rising of the pulse From the point of time until the start of discharge, that is, the characteristic of the PDP that there is a large difference in the discharge delay time is used.

The actual discharge delay time corresponds to the address pulse Pw
Although there is a difference depending on the voltage Vs + Vw, as a typical example, when wall charges exist, the discharge delay time is 100 n
s to 300 ns, and 1.5 when there is no wall charge.
μs to 2.0 μs.

FIG. 3 is a waveform diagram for explaining the operation during the reset period performed in the first embodiment.
Driving waveform of FIG. 3A X electrode 3, Figure 3B is Y electrodes 4 ₁ to 4 _M
3A, and the broken line 31 in FIG. 3A shows the case of the conventional example.

FIG. 3C shows the discharge current of the display cell lit during the sustain discharge period of the immediately preceding subfield in the first embodiment. FIG. 3D shows the sustain current of the immediately preceding subfield in the first embodiment. It shows a discharge current of a display cell that was in a non-lighting state during a discharge period.

FIG. 3E shows the discharge current of the display cell lit during the sustain discharge period of the immediately preceding subfield in the driving method shown in FIG. 13. FIG. 3F shows the discharge current of the display cell in the driving method shown in FIG. It shows a discharge current of a display cell that was in a non-lighting state during a sustain discharge period of a subfield.

That is, in the first embodiment, the voltage is set to, for example, 330 V, and the writing pulse _PW for applying the voltage for 1 μs is applied. Therefore, the light is turned on during the sustain discharge period of the immediately preceding subfield. Only the display cells having the wall charges capable of sustaining discharge start discharging and start forming wall charges, but the display cells that were in the non-lighting state during the sustaining discharge period of the immediately preceding subfield are discharged. And no wall charge is formed.

When the application time of 1 μs ends,
Since trying to the potential of the address electrodes 2 ₁ to 2 _N and X electrode 3 and 0V, is lit in the sustain discharge period of the immediately preceding subfield is performed a large discharge by a write pulse Pw, a lot of wall charges The self-erasing discharge occurs only in the accumulated display cells, the wall charges are neutralized, and nothing occurs in the display cells that were not lit during the sustain discharge period of the immediately preceding subfield.

As described above, in the first embodiment, only the display cells that were lit during the sustain discharge period of the immediately preceding subfield are subjected to the address discharge and the self-erase discharge. It is stated that there is no wall charge, and the next address discharge is stably performed regardless of the lighting state of the immediately preceding subfield.

In the next address period, an address discharge for writing the display data DATA, that is, a display cell to be lit by performing a sustain discharge during the sustain discharge period in accordance with the display data DATA is selected. Are performed line-sequentially.

[0062] In this case, the voltage to the X electrode Vx, for example, applies a 50 V, the voltage -Vy to the Y electrodes 4 ₁ of the first display line, for example, by applying a scan pulse Psc of -150 V, and, A voltage Va, for example, an address pulse A1 of 50 V, for example, is selectively applied to the address electrode of the selected display cell.

[0063] Thus, although discharge between the address electrode and the Y electrode 4 _first display cell to be selected occurs, which as the pilot flame, X electrode 3 and the Y electrode 4 of the display cell to be selected
Immediately proceeds to the discharge between the _1, whereby the amount of wall charge is accumulated that can sustain discharge on the surface of the X electrode 3 and the Y electrode 4 ₁ on the MgO film 13 of the selected display cell .

Hereinafter, the other display lines are sequentially
The same operation is performed to supply the address pulse A2... AN based on the new display data DATA, and perform writing to the selected display cell.

In the next sustain discharge period, the Y electrode 4 ₁
４4 _M and the X electrode 3 alternately, the voltage is Vs, for example, 22
A sustain discharge pulse Ps of 0 V is applied to perform a sustain discharge, and an image display of one subfield is performed.

Here, the sustain discharge pulse Ps is usually set to 180 V, which is a voltage approximately halfway between the minimum discharge start voltage Vf, for example, 280 V, and the minimum sustain discharge voltage Vsm, for example, 130 V.

By the way, when the address pulse Pw is applied during the reset period, the delay time of the discharge start when the address pulse Pw is applied becomes shorter when the address pulse Pw is previously applied, and the discharge time is reduced. The scale is also increased, and more wall charges can be accumulated.

Further, the self-erasing discharge is performed more reliably as a large amount of wall charge is present, and the residual wall charge after the discharge ends is reduced. Therefore, the voltage Vs of the sustain discharge pulse Ps can be changed. Higher is better.

However, when the voltage Vs of the sustain discharge pulse Ps is set to the minimum discharge starting voltage Vf, for example, a value close to 280 V, for example, 230 V, during the sustain discharge period, the X electrode 3 and the Y electrodes 4 ₁ to 4 _M Has a disadvantage that self-erasing discharge occurs at the timing when the voltage becomes 0V.

Therefore, if the voltage Vs of the sustain discharge pulse Ps is increased within a range that does not cause the self-erasing discharge, the sustain discharge is performed, and when the write pulse Pw is applied during the reset period, a large amount of wall charge is held in advance. As a result, the delay time of the start of discharge upon application of the address pulse Pw is shortened, and the magnitude of the discharge is increased, so that more wall charges can be accumulated.

Therefore, in the first embodiment, the voltage Vs of the sustain discharge pulse Ps is set to 220 V in a range that does not cause the self-erasing discharge, and is higher than 180 V in the conventional example.

As described above, in the first embodiment, in the reset period, the write discharge and the self-erase discharge are not performed for the display cell which was in the non-lighting state in the sustain discharge period of the immediately preceding subfield. Write discharge and self-erasing discharge are performed only on the display cells that were lit during the sustain discharge period of the immediately preceding subfield, and all display cells are in a state without wall charges, so that it is possible to reduce invalid light emission.

Therefore, according to the first embodiment, 3
In the case of performing 256 gradation display for an electrode / surface discharge type AC PDP, the contrast ratio and the color reproducibility can be increased, and the display quality can be improved.

Second Embodiment FIG. 4 to FIG. 6 FIG. 4 is a time chart for explaining a second embodiment of the present invention. In this second embodiment, one frame is composed of eight sub-frames. The fields are divided into fields SF1 to SF8.

The subfields SF1 to SF1
In F8, the reset period and the address period have the same length, but the sustain discharge period has a length of 1: 2: 4: 8: 16: 32: 64: 128. Is the same as in the first embodiment.

In the second embodiment, the driving method shown in FIG. 5 is executed in subfields SF1 to SF8.

[0077] Here, FIG. 5A driving waveform of the address electrode 2 ₁ to 2 _N, FIG. 5B is driving waveforms of the X electrodes 3, Figure 5C Y electrode 4 _first drive waveform, FIG. 5D driving of the Y electrode 4 ₂ Waveform, FIG.
E indicates a drive waveform of the Y electrode 4 _M.

[0078] That is, in the reset period, first, all the Y electrodes 4 ₁ to 4 _M and to 0V, and the address electrodes 2 ₁ to 2 _N
The voltage Vaw, for example, applies a 100 V, the X electrode 3, the voltage Vs + Vw, for example, a 260 V, application time and application of address pulse P _W to 10 [mu] s, then the address electrodes 2 ₁ to 2 _N and The potential of the X electrode 3 is set to 0V.

As in the case of the first embodiment, the application of the address pulse Pw does not perform the address discharge and the self-erase discharge on the display cell which has been turned off during the sustain discharge period of the immediately preceding subfield. The purpose of the present invention is to cause only the display cells that have been lit during the sustain discharge period of the immediately preceding subfield to perform the address discharge and the self-erase discharge, thereby keeping all the display cells free of wall charges.

In this driving method, the voltage required to start the discharge differs between the case where the wall charge acting in the form superimposed on the address pulse Pw and the case where the wall charge does not exist. Does not exist, a voltage exceeding the discharge starting voltage must be applied between the X and Y electrodes.
Although the discharge is not started, if a wall charge exists, a characteristic lower than that of the discharge start voltage is used to start the discharge when a voltage lower than the discharge start voltage is supplied.

The actual discharge starting voltage is between 280 V and 320 V due to the variation of the display cells.
Then, discharge can be started only in the display cells in which wall charges exist.

FIG. 6 is a waveform chart for explaining the operation during the reset period performed in the second embodiment.
Figure 6A is driving waveforms of the X electrodes 3, Figure 6B is Y electrodes 4 ₁ to 4 _M
6A, the broken line 33 in FIG. 6A indicates the case of the conventional example.

FIG. 6C shows the discharge current of the display cell lit during the sustain discharge period of the immediately preceding subfield in the second embodiment. FIG. 6D shows the sustain current of the immediately preceding subfield in the second embodiment. It shows a discharge current of a display cell that was in a non-lighting state during a discharge period.

FIG. 6E shows the discharge current of the display cell lit during the sustain discharge period of the immediately preceding subfield in the driving method shown in FIG. 13, and FIG. 6F shows the discharge current of the display cell in the driving method shown in FIG. It shows a discharge current of a display cell that was in a non-lighting state during a sustain discharge period of a subfield.

That is, in the second embodiment, the voltage is lower than the minimum discharge start voltage, but is higher than 220 V which is the voltage Vs of the sustain discharge pulse Ps.
Write pulse P with 60V applied and 10μs applied time
_{Since W} is applied, only the display cells that have been turned on during the sustain discharge period of the immediately preceding subfield and have wall charges capable of sustain discharge start discharging and start forming wall charges. However, the display cells in the non-lighting state during the sustain discharge period of the immediately preceding subfield do not start discharging and do not form wall charges.

[0086] When the 10μs application time is finished, since the potential of the address electrodes 2 ₁ to 2 _N and X electrode 3 is set to a 0V, are lit in the sustain discharge period of the immediately preceding subfield, address pulse A large-scale discharge is performed at Pw, and a self-erasing discharge occurs only in a display cell in which a large amount of wall charge is accumulated, the wall charge is neutralized, and the display cell that has been in a non-lighting state during the sustain discharge period of the immediately preceding subfield is discharged. Nothing will happen.

As described above, in the second embodiment, only the display cells that were lit during the sustain discharge period of the immediately preceding subfield are subjected to the address discharge and the self-erasing discharge. It is stated that there is no wall charge, and the next address discharge is stably performed regardless of the lighting state of the immediately preceding subfield.

In the next address period, an address discharge for writing the display data DATA, that is, a display cell to be turned on by performing a sustain discharge in the sustain discharge period in accordance with the display data DATA. Are performed line-sequentially.

In this case, a voltage Vx is applied to the X electrode 3, for example,
50 V is applied, and the Y electrode 4 ₁ of the first display line is applied.
Scan pulse Ps of voltage -Vy, for example, -150 V
c, and a voltage Va, for example, an address pulse A1 of 50 V, is selectively applied to the address electrode of the display cell to be selected.

[0090] Thus, although discharge between the address electrode and the Y electrode 4 _first display cell to be selected occurs, this immediately to the discharge between the X electrode 3 and the Y electrode 4 ₁ as the pilot flame The X-electrode 3 of the selected display cell is shifted.
Surface sustain discharge amounts of the wall charges in the Y electrode 4 ₁ on the MgO film 13 is accumulated with.

Hereinafter, the other display lines will be sequentially described.
The same operation is performed to supply the address pulse A2... AN based on the new display data DATA, and to write into the display cell to be selected.

In the next sustain discharge period, the Y electrode 4 ₁
４4 _M and the X electrode 3 alternately, the voltage is Vs, for example, 22
A sustain discharge pulse Ps of 0 V is applied to perform a sustain discharge, and an image display of one subfield is performed.

The application of the sustain discharge pulse Ps having this voltage of 220 V performs the sustain discharge as in the case of the first embodiment, and applies the address pulse Pw during the reset period.
Is applied, a large amount of wall charges is stored in advance, the delay time of the start of discharge upon application of the address pulse Pw is shortened, the scale of the discharge is increased, and more wall charges are accumulated. .

As described above, in the second embodiment, in the reset period, the write discharge and the self-erase discharge are not performed for the display cells that were in the non-lighting state during the sustain discharge period of the immediately preceding subfield. Write discharge and self-erase discharge are performed only on the display cells that have been turned on during the sustain discharge period of the immediately preceding subfield, and all display cells are in a state without wall charges, so that invalid light emission can be reduced.

Therefore, according to the second embodiment, 3
In the case of performing 256 gradation display for an electrode / surface discharge type AC PDP, the contrast ratio and the color reproducibility can be increased, and the display quality can be improved.

Third Embodiment FIG. 7 FIG. 7 is a time chart for explaining a third embodiment of the present invention. Also in this third embodiment, one frame includes eight subfields SF1 to SF1. It is classified into SF8.

Then, these subfields SF1 to S
In F8, the reset period and the address period have the same length, but the sustain discharge period has a length of 1: 2: 4: 8: 16: 32: 64: 128. Is the same as in the first embodiment.

In the third embodiment, the subfield SF1
In the reset period, the conventional driving method shown in FIG. 13 is executed to cause all the display cells to perform a write discharge and a self-erase discharge. In the address period of the subfield SF1, the sustain discharge period, and the subfields SF2 to SF8, , The driving method shown in FIG. 2 is executed.

Here, in the case of the above-described first embodiment, no display is performed, and if lighting is attempted for the first time after several seconds to several hours, no discharge is performed during that time, so that no space is generated. There will be no charge.

Normally, even after the discharge is completed, a small amount of electric charge exists in the space for several milliseconds. When writing is performed, the existence of such a small amount of electric charge causes the writing probability to exceed a certain level. (Priming effect).

However, in the case of the first embodiment, there is a possibility that a state in which no discharge occurs for a long time and a state in which no charge exists in the space may occur. Probability may be reduced.

Therefore, the third embodiment is an improvement over the first embodiment, in which the write discharge and the self-erase discharge are performed in all the display cells once per frame, as in the conventional case, and the space in the space is reduced. To avoid a state in which no charge is present at all.

The subfield in which the address discharge and the self-erase discharge are performed for all the display cells is the reset period of the subfield in which the write discharge and the self-erase discharge are performed for all the display cells in the next frame from the end of the reset period. Is arranged so that the period up to the address period of the subfield immediately before is the shortest.

According to the third embodiment, the amount of invalid light emission is slightly increased as compared with the case of the first embodiment, but the amount of invalid light emission can be reduced as compared with the conventional example. A
When a 256-level display is performed on a C-type PDP, the contrast ratio and the color reproducibility can be increased, and the display quality can be improved.

FIG. 8 is a time chart for explaining a fourth embodiment of the present invention. Also in this fourth embodiment, one frame includes eight subfields SF1 to SF1. It is classified into SF8.

In these subfields SF1 to SF8, the reset period and the address period are respectively
Although the length is the same, the length of the sustain discharge period is 1:
The ratio of 2: 4: 8: 16: 32: 64: 128 is the same as in the first embodiment.

In the fourth embodiment, the subfield SF1
In the reset period, the conventional driving method shown in FIG. 13 is executed to cause all the display cells to perform a write discharge and a self-erase discharge. In the address period of the subfield SF1, the sustain discharge period, and the subfields SF2 to SF8, , The driving method shown in FIG. 5 is executed.

Here, in the case of the second embodiment described above, the first
As in the case of the embodiment, no display is performed, and if it is attempted to light up for the first time after a few seconds or several hours, no electric charge is present in the space because no discharge was performed at that time. become.

Therefore, the fourth embodiment is an improvement over the second embodiment, in which the write discharge and the self-erase discharge are performed on all the display cells once per frame, as in the conventional case, so that the To avoid a state in which no charge is present at all.

The subfield in which the address discharge and the self-erase discharge are performed for all the display cells is from the end of the reset period to the reset period of the subfield in which the address discharge and the self-erase discharge are performed for all the display cells in the next frame. As in the case of the third embodiment, arranging so that the period up to the address period of the immediately preceding subfield is the shortest enables the priming effect to be maximized.

According to the fourth embodiment, the amount of invalid light emission is slightly increased as compared with the case of the second embodiment, but the amount of invalid light emission can be reduced as compared with the conventional example. A
When a 256-gradation display is performed on a C-type PDP, the contrast ratio and the color reproducibility can be increased, and the display quality can be improved.

[0112]

As described above, according to the present invention, in the reset period, only the display cells that were lit in the immediately preceding discharge period are subjected to the erasing discharge, and the non-lighted state is set in the immediately preceding discharge period. Since the erasing discharge is not performed for the display cell that has been used, invalid light emission can be reduced, the contrast ratio and color reproducibility can be increased, and the display quality can be improved.

[Brief description of the drawings]

FIG. 1 is a time chart for explaining a first embodiment of the present invention.

FIG. 2 is a waveform chart showing a driving method executed in a subfield according to the first embodiment of the present invention.

FIG. 3 is a waveform chart for explaining an operation in a reset period performed in the first embodiment of the present invention.

FIG. 4 is a time chart for explaining a second embodiment of the present invention.

FIG. 5 is a waveform chart showing a driving method executed in a subfield according to a second embodiment of the present invention.

FIG. 6 is a waveform chart for explaining an operation in a reset period performed in a second embodiment of the present invention.

FIG. 7 is a time chart for explaining a third embodiment of the present invention.

FIG. 8 is a time chart for explaining a fourth embodiment of the present invention.

FIG. 9 is a schematic plan view showing an example of a three-electrode / surface-discharge type AC PDP.

10 is a schematic cross-sectional view along an address electrode of the AC PDP shown in FIG.

11 is a schematic sectional view along a Y electrode of the AC type PDP shown in FIG.

12 is a block circuit diagram schematically showing a peripheral circuit for driving the AC PDP shown in FIG.

13 is a waveform diagram showing an example of a conventional driving method of the AC type PDP shown in FIG.

14 is a time chart showing a driving method in the case of performing 256 gradation display in the AC PDP shown in FIG. 9;

[Explanation of symbols]

29 _{1-29 3} 29 ₈ address lines Pw write pulse A1~AN address pulse Psc scan pulse Ps sustain discharge pulse

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-313598 (JP, A) JP-A-5-241528 (JP, A) JP-A-11-352931 (JP, A) JP-A-7- 295507 (JP, A) JP-A-4-280289 (JP, A) JP-A-3-179489 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/28 G09G 3 / 288

Claims (6)

(57) [Claims] 1. A method for driving a flat display panel comprising a pair of electrodes for performing at least discharge light emission, and a plurality of display cells defined by the pair of electrodes, wherein a wall in the display cell is provided. A reset period for erasing electric charges, and a discharge period for performing discharge light emission in an arbitrary display cell. In the reset period, discharge occurs only in the display cell that was lit in the immediately preceding discharge period Voltage value like
Or apply write pulse with pulse width to all display cells
And then the wall charge itself accumulated by the discharge
A method for driving a flat display panel, wherein a self- erasing discharge for starting a discharge by a potential difference is performed. 2. The method according to claim 2, wherein the voltage is applied during the reset period .
The write pulse has a voltage exceeding the discharge starting voltage, and has a polarity in which the voltage by the wall charge formed by the last discharge in the immediately preceding discharge period is added.
The application time no wall charge, a driving method of a flat display panel of claim 1, wherein the display cell which was a non-lighting state, characterized in that a time that does not start discharge. 3. The method according to claim 2, wherein the voltage is applied during the reset period .
The write pulse has a voltage lower than the discharge start voltage,
The flat display according to claim 1, wherein the polarity is a polarity to which a voltage due to wall charges formed by the last discharge in the immediately preceding discharge period is added.
Panel driving method. 4. The discharge in the discharge period is performed by applying a pulse of a voltage close to the minimum discharge start voltage and not causing a self-erasing discharge to the display cell. 4. The method for driving a flat display panel according to claim 1, 2 or 3. 5. A frame is erased from wall charges in a display cell.
Reset period and release at any display cell.
A plurality including a discharge period for causing electroluminescence.
Flat display composed of sub-fields
A method of driving a panel, wherein the plurality of sub-fields
Is the voltage and pulse that will cause discharge to all display cells.
A write pulse with a width is applied and then the discharge
Discharge is started by the potential difference of the accumulated wall charge itself
A first reset period for performing a self-erasing discharge
Only the first subfield and the display cells that were lit during the immediately preceding discharge period are released.
Write pulse with a voltage value or pulse width such that
Is applied to all display cells and then stored by the discharge.
Self that starts discharge by the potential difference of the accumulated wall charge itself
A second reset period for performing an erase discharge;
Flat data, including sub-fields.
The driving method of the display panel. 6. A method according to claim 1, wherein a predetermined number of said plurality of subfields is
From the end of the reset period in the subfield of
Of the frame located immediately before the subfield of the frame
The period up to before the discharge period of
The predetermined sub-field in the first sub-field.
Field, and the other subfield is the second subfield.
6. The flat plate according to claim 5, wherein
Driving method of display panel.