JP3263058B2 - Method of implanting impurities into semiconductor inner wall - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for uniformly and continuously implanting impurities into an inner wall of a trench or a groove provided on a surface of a semiconductor.

[0002]

2. Description of the Related Art Conventionally, as a part of improving the degree of integration of a semiconductor device, a technique has been known in which a trench is provided on the surface of a semiconductor substrate and a semiconductor resistance element and a semiconductor capacitance element are formed in the trench. Alternatively, a method of forming an element isolation region using the trench is known.
In order to form these elements or isolation regions, it is necessary to diffuse impurities into the trench inner wall. Conventionally, the implantation of impurities into the inner wall has been performed by ion implantation or so-called bled deposition.

[0003]

However, in the case of ion implantation, since ions of impurities to be implanted are implanted at an accelerated rate, there is inevitably a directivity of implantation. Therefore, there is a problem that impurities cannot be implanted at a uniform concentration and a uniform depth over the entire inner wall of the trench. In addition, when so-called pre-deposition is used, since the impurity is diffused through an inert film on the inner wall of the trench, it is difficult to control the diffusion concentration and the diffusion depth.

[0004]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a method capable of uniformly and continuously implanting impurities into the inner wall of a trench. I do.

FIG. 1 is a process chart for explaining the concept of the impurity implantation method according to the present invention. In the step shown in FIG. 1A, a recess 2 is provided on the surface of a semiconductor substrate 1. The recess 2 is, for example, a trench and has an inner wall 3. The inner wall 3 here is a concept including the side wall and the bottom wall of the recess 2. The inner wall 3 is inevitably covered with an inert coating 4.

In the step shown in FIG. 1B, the inactive coating existing on the surface of the inner wall 3 is removed to expose the active surface.
When the semiconductor substrate 1 is made of silicon, the inert coating 4 is a silicon oxide film. The concave portion 2 or the trench is usually formed by reactive ion etching. After the reactive ion etching is completed, the inner wall 3 of the concave portion 2 is quickly covered with the inert film. Therefore, FIG.
It is necessary to clean the inner wall 3 of the concave portion 2 to expose the active surface by the step shown in FIG. This cleaning process is performed by holding the semiconductor substrate 1 in a heated state and leaving it in a high vacuum. At this time, if a reducing gas such as hydrogen gas is introduced, purification is promoted.

In the step shown in FIG. 1C, a gas having an impurity component, for example, diborane, is supplied to the exposed active surface of the inner wall 3 to adsorb the impurity component or the compound of the impurity component to thereby form an impurity film 5. To form The adsorption treatment of the impurity film 5 is performed by introducing diporane gas at a predetermined vapor pressure under a high vacuum. The impurity film 5 is substantially selectively adsorbed only on the active surface.

Finally, in a step shown in FIG. 1D, the semiconductor substrate 1 is heated to diffuse impurities such as boron forming the impurity film 5 toward the inside of the inner wall 3 and activate it. As a result, an impurity diffusion layer 6 is formed along the inner wall. The impurity diffusion layer 6 has a desired conductivity and impurity diffusion concentration by controlling the amount of the adsorbed impurity film 5 and the like. As a result, the impurity diffusion layer 6 becomes a resistor layer, an electrode layer,
Alternatively, it can be used as an electrical isolation layer.

Next, the operation of the present invention will be described in detail with reference to FIGS. FIG. 2 is a block diagram showing an implantation apparatus for performing the impurity implantation method according to the present invention.
As shown, a silicon substrate 1 is made of a quartz chamber 12.
It is installed near the center of the interior. The silicon substrate 1 is provided with a trench in advance, and a mask is applied to portions other than the inner wall of the trench. The temperature of the silicon substrate 1 is controlled by a heating system 13 using an infrared lamp heating method or a resistance heating method, and can be maintained at a predetermined temperature. The inside of the chamber 12 can be evacuated to a high vacuum using a high vacuum evacuation system 14 including a plurality of pumps using a terpo molecular pump as a main evacuation pump. The degree of vacuum inside the chamber 12 is constantly monitored by the pressure gauge 15. The transfer of the silicon substrate 1 is performed using the transfer mechanism 18 between the load chamber 17 connected to the chamber 12 via the gate valve 16a and the chamber 12 with the gate valve 16a opened.

The load chamber 17 is usually evacuated to a high vacuum by the load chamber exhaust system 19 with the gate valve 16b open except when the silicon substrate 1 enters and exits from the load chamber 17 and during transport. I have. A gas supply source 21 is connected to the chamber 12 via a gas introduction control system 20.
The gas supply source 21 incorporates a plurality of gas cylinders for storing various source gases required for the impurity injection process.

The type, amount and time of gas introduced from the gas supply source 21 into the chamber 12 are controlled by a gas introduction control system 20.

Next, the step of implanting impurities into the inner wall formed in the surface of the silicon substrate 1 using the implantation apparatus shown in FIG. 2 will be described in detail, taking the case of doping with boron as an example. First, a process for cleaning the inner wall of the trench formed in the silicon substrate 1 will be described.

The silicon substrate 1 has a background pressure of 1
It is set at the center of the vacuum chamber 12 maintained at × 10 ⁻⁴ Pa or less. Then, the silicon substrate 1 is maintained at 850 ° C., and hydrogen gas is introduced for a predetermined time under such conditions that the pressure inside the chamber 12 becomes 1.3 × 10 ⁻² pa, for example. As a result, the natural oxide film formed on the inner wall of the silicon substrate 1 is removed, and the chemically active silicon surface is exposed.

Subsequently, an adsorption layer of boron or a compound containing boron is formed on the activated inner wall. That is, after the cleaning of the inner wall surface is completed, the introduction of hydrogen gas is stopped, and the substrate temperature is set to, for example, 800 ° C. After the temperature reaches the set temperature and stabilizes, the raw material gas obtained by diluting diborane (B ₂ H ₆ ), which is a compound gas containing boron, to 5% with nitrogen gas in the chamber 12 is cooled to 1%, for example. It is introduced for a certain period of time under the condition of 3 × 10 ⁻² pa. As a result, an adsorption layer of boron or a compound containing boron is adsorbed on the activated inner wall of the silicon substrate 1. At this time, at the same time as the formation of the boron adsorption layer or the boron-containing compound adsorption layer, the diffusion of boron into the bulk at a certain rate determined by the substrate temperature and diborane introduction pressure during the introduction of diborane also partially proceeds. Seems to be. Subsequently, heat treatment, that is, annealing of the silicon substrate 1 is performed. After the boron impurity film is adsorbed on the inner wall, the introduction of diborane gas is stopped, and heating is performed for a predetermined time in a vacuum. The substrate temperature at this time is preferably set to be slightly higher than the substrate temperature used in the impurity adsorption treatment.

By performing this annealing, an impurity diffusion layer using a boron impurity film as a diffusion source is formed along the inner wall, and at the same time, the diffused impurity atoms are activated. In the present invention, an impurity diffusion layer having a desired impurity concentration and diffusion depth can be obtained by controlling the amount of absorbed boron and the annealing conditions (substrate heating temperature and heating time).

FIG. 3 is a graph showing the dependence of the peak concentration of doped boron on diborane introduction time when the diborane introduction pressure is used as a parameter in the above-described process. FIG.
As shown in (1), as the diborane introduction pressure is increased, the amount of adsorbed boron increases, and the peak concentration of boron to be injected increases accordingly.

As the time for introducing the diborane gas is increased, the amount of adsorbed boron increases, and accordingly, the peak concentration of the injected boron also increases. Thus, by appropriately setting the introduction pressure and introduction time of diborane, the boron peak concentration of the impurity diffusion layer can be adjusted, and as a result, the boron diffusion layer can be used for various applications.

As is apparent from the above description, the present invention forms an adsorption layer of a substance containing at least an impurity element which becomes a semiconductor dorant on a semiconductor inner wall which has been chemically activated, and forms the adsorption layer. It has a principle feature in that an impurity is doped into an inner wall of a semiconductor as an impurity diffusion source. According to the inventor's detailed research, almost no adsorbed layer is formed or at least an order of magnitude less adsorbed impurities remain on an inactive surface covered with an oxide film than on an active surface. It turns out there is no. In particular, when boron is adsorbed on the silicon surface, it is considered important to remove an inert coating such as a natural oxide film in advance.

When implanting a P-type impurity into the inner wall of a silicon semiconductor, a source gas other than diborane, for example, trimethylgallium (TMG), boron trichloride (BCl
₃ ) A compound of a group III element represented by, for example, can be used. Similarly, when an N-type impurity is doped into the inner wall of a silicon semiconductor, arsine (AsH ₃ ), phosphorus trichloride (PCl ₃ ), antimony pentachloride (SbCl ₅ ), and phosphine (PH ₃ ) are used as source gases. Etc. can be used.

In order to carry out the cleaning treatment of the inner wall of the semiconductor substrate, the substrate temperature is preferably set in the range of 800 ° C. to 1200 ° C., including the relationship between the background pressure and the atmosphere gas. In the adsorption layer forming process, it is preferable to set the substrate temperature in the range of 400 ° C. to 950 ° C.

Further, besides forming an impurity adsorption film directly on the inner wall of the activated semiconductor substrate, it is also possible to use a silicon film grown epitaxially as a base treatment. Alternatively, a silicon single crystal film may be formed on the formed impurity adsorption film by the epitaxial growth method. Further, the impurity diffusion layer may be formed by stacking the impurity adsorption film and the silicon single crystal film on each other. As described above, there is a feature that activation of impurities is promoted by interposing a silicon crystal structure film. Further, by laminating the impurity adsorption film and the silicon single crystal film, the thickness of the impurity diffusion layer can be freely controlled as a result. Further, by repeating formation and diffusion of the impurity adsorption film, an impurity diffusion layer having a desired impurity concentration and diffusion depth can be obtained.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 4 is a process chart showing an embodiment in which the impurity implantation method according to the present invention is applied to the manufacture of a so-called trench resistance element. In the step shown in FIG. 4A, a trench 42 is provided on the surface of a semiconductor substrate 41 made of silicon, and an inner wall 43 is formed. The formation of the trench 42 is performed by, for example, reactive ion etching.

In the step shown in FIG. 4B, a trench 42 is formed to mask a region other than the region into which impurities are implanted.
An insulating film 44 is formed along both sides of the substrate. The insulating film 44 is formed by depositing a silicon oxide film or a silicon nitride film by a chemical vapor deposition method.

In the step shown in FIG.
Then, a cleaning process is performed on the exposed surface of the silicon substrate 41 to remove the inactive film and expose the active surface. Subsequently, diborane gas is supplied to this active surface,
An impurity adsorption film 45 containing boron is selectively formed. Since the impurity adsorption film 45 is formed chemically, it is deposited along the inner wall 43 with a uniform thickness.

In the step shown in FIG.
Is subjected to the heat treatment, and the impurity boron forming the adsorption film 45 is uniformly diffused along the inner wall 43, and the impurity diffusion layer 46 is formed.
To form The impurity diffusion layer 46 is of a P + type, and has a desired resistance value by controlling the amount of boron introduced. In addition, since the impurity diffusion layer 46 is formed uniformly and continuously along the inner wall 43, an extremely good resistor film is provided.

Finally, in a step shown in FIG. 4E, a pair of electrode films 47 are formed, and a so-called trench resistance element is manufactured. According to the present embodiment, since a resistive element can be provided in the trench, the semiconductor device can be miniaturized. If the resistive film is formed on the inner wall of the trench by a conventional deposition technique, a problem such as step disconnection or uneven film thickness occurs, which is not preferable in practical use.

FIG. 5 is a schematic view showing another embodiment in which the impurity implantation method according to the present invention is applied to the manufacture of a trench resistance element. As shown, the trench resistance element according to the present embodiment has a concave portion 52 formed on the surface of a silicon semiconductor substrate 51. The lower portion of the concave portion 52 is larger than the upper portion, so that the semiconductor substrate 51 can be more effectively utilized three-dimensionally. A boron impurity diffusion layer 53 is formed along the inner wall of the recess 52. A pair of electrode films 55 is formed on both sides of the concave section 52 via an insulating film 54. Each end of the pair of electrode films 55 is joined to the impurity diffusion layer 53 to constitute a trench resistance element.

FIG. 6 is a process chart showing an embodiment in which the impurity implantation method according to the present invention is applied to the formation of a so-called trench isolation region. In the step shown in FIG. 6A, an insulating film 62 is formed on a surface of a semiconductor substrate 61 made of silicon. The insulating film 62 is made of a silicon oxide film or a silicon nitride film. A resist film 63 is applied on the insulating film 62. The resist film 63 is etched according to a predetermined pattern and is partially removed.
A region for element isolation is formed later in the partially removed portion.

In the step shown in FIG. 6B, reactive ion etching is performed through the resist film 63 to form a trench 64, and then the trench 64 is formed. Is also removed.

Subsequently, in a step shown in FIG. 6C, a boron impurity adsorption film is selectively formed only on the inner wall of the trench. As described above, this adsorption film 65 is formed by introducing diborane gas while heating the substrate 61.

In the step shown in FIG.
Is performed, and the boron contained in the impurity adsorption film 65 is diffused into the semiconductor substrate 61 along the inner wall of the trench and activated. As a result, a high concentration P-type impurity diffusion layer 66 is formed. This impurity diffusion layer 66 is formed so as to completely and uniformly cover the trench.

Finally, in the step shown in FIG. 6E, the inside of the trench 64 is filled with an oxide film 67. As a result, a so-called trench isolation region is formed.
This trench isolation region has a two-layer structure of a filled oxide film 67 and an impurity diffusion layer 66. Since the high-concentration P-type impurity diffusion layer 66 is interposed between the oxide film 67 and the semiconductor substrate 61, the element region is completely separated. That is, the impurity diffusion layer 66 has a function of preventing inversion of the semiconductor layer near the interface, and significantly increases the open voltage of the trench isolation region.

FIG. 7 is a sectional view showing an embodiment in which the impurity implantation method according to the present invention is applied to the manufacture of a so-called trench capacitor. As shown, the trench capacitance element is formed on an N-type silicon semiconductor substrate 71.
A trench is provided on the surface of the substrate 71, and a P + type electrode layer 72 is formed along the inner wall of the trench. The electrode layer 72 is formed by the impurity implantation method according to the present invention, and is a P + type impurity diffusion layer containing boron. The dielectric layer 7 extends along the electrode layer 72.
3 are formed. The dielectric layer 73 is deposited, for example, by chemical vapor deposition of silicon dioxide. The other electrode layer 74 is formed along the dielectric layer 73.

The electrode skin 74 is formed, for example, by depositing a polycrystalline silicon film and injecting impurities at a high concentration. According to this embodiment, the trench capacitance element can be easily formed inside the surface of the semiconductor substrate, and the degree of integration of the semiconductor device can be improved.

[0036]

As described above, according to the present invention, impurity diffusion along the inner wall is performed by a series of steps of cleaning, impurity adsorption, and diffusion of the inner wall formed inside the surface of the semiconductor substrate. The effect is that the layers can be formed uniformly and continuously. Further, it is possible to easily control the concentration and the diffusion depth of the impurity implanted into the impurity diffusion layer, and there is an effect that the impurity diffusion layer thus obtained can be used for various purposes.

[Brief description of the drawings]

FIG. 1 is a process chart of an impurity implantation method.

FIG. 2 is a block diagram of an apparatus used for impurity implantation.

FIG. 3 is a graph of the peak boron concentration injected.

FIG. 4 is a manufacturing process diagram of the trench resistance element.

FIG. 5 is a sectional view of a trench resistance element.

FIG. 6 is a process chart of forming a trench isolation region.

FIG. 7 is a sectional view of a trench capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Concave part 3 ... Inner wall 4 ... Inactive coating 5 ... Impurity adsorption film 6 ... Impurity diffusion layer

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-53920 (JP, A) JP-A-64-74719 (JP, A) JP-A-62-283624 (JP, A) JP-A-63-283624 249332 (JP, A) JP-A-63-164358 (JP, A) "Latest LSI process technology" Kazuo Maeda, 1988, 4th edition, Industrial Research Committee, pp. 197 (58) Fields investigated (Int. Cl. ⁷ , DB (Name) H01L 21/225 H01L 21/22 H01L 21/822 H01L 27/04

Claims (7)

(57) [Claims] 1. A recess formed in a surface of the semiconductor substrate, a first step of forming an inner wall, and a second step of exposing the removed active surface with an inert coating on the surface of the inner wall, of the semiconductor substrate A third step of supplying diborane to the active surface and adsorbing boron or a compound containing a boron element to form an impurity film on the active surface at a temperature of 400 ° C. or higher and 950 ° C. or lower; And a fourth step of diffusing boron in the impurity film into the inner wall. Wherein said the second step, injection method of impurities according to claim 1, said third step is carried out continuously in a vacuum chamber. 3. The method according to claim 1, wherein the second step is performed at a background pressure of 1
× 10 −4 Pa or less, and a substrate temperature of 800 ° C. or more and 12
3. The method according to claim 2 , wherein the temperature is not higher than 00.degree. 4. The semiconductor device according to claim 1 , wherein the concave portion of the semiconductor substrate is provided with the semiconductor.
The width of the bottom is larger than the width of the opening on the surface of the substrate.
2. The method according to claim 1, wherein the impurity is implanted. 5. A layer in which boron is diffused into the inner wall,
2. The method according to claim 1, wherein the impurity is an antibody layer. 6. A method for filling the inner wall of the recess with an oxide film.
2. The method according to claim 1, further comprising five steps. 7. The resistor layer forms a first electrode layer.
And forming a dielectric layer on the first electrode layer.
5 steps, and furthermore, forming a second electrode on the dielectric layer
6. The impurity implantation according to claim 5, comprising a sixth step of forming.
Method.