JP3260573B2 - YC separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a YC separation circuit, and more particularly to a YC separation circuit for separating a luminance signal and a color signal of a color video signal using a comb filter.

[0002]

2. Description of the Related Art Conventionally, this type of YC separation circuit uses a comb-type filter configuration which takes a correlation with a delay (1H delay) corresponding to one horizontal scanning period. At least three adjustments of the input level and the delay time of the color signal separation are required.

Referring to FIG. 2, which shows a block diagram of a conventional YC separation circuit used in a general television receiver or VTR, the conventional YC separation circuit removes unnecessary high frequency components of an input video signal I. A low-pass filter (LPF) 4 that removes and outputs a signal IF, a 1H delay element 6 that delays the signal IF by one horizontal scanning period to generate a 1H delay signal H, and adjusts an output level of the 1H delay signal to generate a signal VH. A variable resistor 20 for generating a signal LH; an LPF 7 for removing an unnecessary clock component from the signal VH to generate a signal LH;
An amplifier 21 for amplifying the signal AH and outputting a signal AH; a variable resistor 22 for adjusting the level of the signal AH and outputting a signal HF;
An adder 15 that adds the signal IF and the signal HF to generate a luminance signal Y and an adder 16 that subtracts the signal IF and the signal HF from each other to generate a color signal C are provided.

Next, the operation of a conventional YC separation circuit will be described with reference to FIG. 2. This circuit is a two-line YC separation circuit utilizing the well-known fact that there is a line correlation between adjacent scanning lines. First, the video signal I input from the input terminal T1 is supplied to the LPF 4, and the LPF 4 removes unnecessary high frequency components of the video signal I and outputs the signal IF. The signal IF is supplied to the 1H delay element 6 and the adders 15 and 16, respectively. The 1H delay element 6 is composed of a known clock signal driven CCD or the like, delays the signal IF by 1H, and supplies the output signal H to the variable resistor 20. The variable resistor 20 adjusts the signal H to an appropriate level, and the output signal VH
Is supplied to the LPF 7. The LPF 7 has a cutoff frequency of about 5.5 MHZ, removes the clock signal component included in the signal VH delayed by 1 H, and supplies the output signal LH to the amplifier 21. Amplifier 2 1 amplifies the supplied signal LH, and supplies an output signal AH to the variable resistor 22. The variable resistor 22 adjusts the level of the signal AH and supplies an output correlation signal HF to each of the adders 15 and 16. Adder 1
Reference numerals 5 and 16 perform the inversion of the phase of the color signal before and after the 1H period, which is a feature of the signal of the NTSC system, and the correlation operation of the signals IF and HF using the similarity of the color signals. The adder 15 extracts the luminance signal Y by attenuating the color signal C as a result of the addition of the signals IF and HF, and outputs the luminance signal Y to the output terminal TY. The adder 16 extracts the chrominance signal C by attenuating the luminance signal Y as a result of the mutual subtraction of the signals IF and HF, and outputs it from the output terminal TC.

Next, a further description will be given of the conventional method of adjusting the YC separation circuit. The output signal H of the 1H delay element 6 is input to the variable resistor 20. This variable resistor 20
The purpose of the adjustment is to set the level of the signal VH to be supplied to the LPF 7 by absorbing the variation in the gain of the 1H delay element. Next, the variable resistor 22 absorbs a variation in gain between the LPF 7 and the amplifier 21 and supplies the level of the correlation signal HF to be supplied to the adders 15 and 16 to the other input signal I.
The level is adjusted to match the level of F.

Finally, the time error between the signals IF and HF supplied to the adders 15 and 16 is adjusted by increasing or decreasing the delay time of the LPF 7. As a result of this delay time adjustment,
The adders 15 and 16 provide a signal IF to be subjected to a correlation operation and a correlation signal HF obtained by delaying the signal IF by exactly 1H, that is, 1H.
The previous signal IF is input.

As described above, this conventional YC separation circuit adjusts the level of the output signal VH of the 1H delay element 6, adjusts the level of the correlation signal HF supplied to the adders 15 and 16, and adjusts the 1H of the correlation signal HF. Adjustment of delay time and total 3
It needs to be adjusted in several places.

[0008] If the above adjustment is incomplete, a clear image can be obtained due to the occurrence of problems such as cross color caused by leakage of the luminance signal to the color signal and dot interference caused by leakage of the color signal to the luminance signal. These adjustments were considered essential.

[0009]

The conventional YC separation circuit described above adjusts the level of the output signal of the 1H delay element, and adjusts the level of the correlation signal supplied to each adder for separating the luminance signal and the chrominance signal. And adjustment of the 1H delay time of the correlation signal.
There is a drawback in that it requires adjustment of the locations, and in the manufacturing process of a television receiver or the like using the same, it causes an increase in man-hours and costs.

Further, there has been a drawback that the above-described adjustment deviation occurs due to a change over time of an adjustment element such as a variable resistor, and stable operation for a long period of time is difficult.

[0011]

The YC separation circuit of the present invention delays an input color video signal by one horizontal scanning period.
A 1H delay element that generates an H delay signal, a low-pass filter that removes unnecessary high frequency components of the 1H delay signal and generates a filtered 1H delay signal,
A YC having a comb filter characteristic comprising first and second adders for correlating a correlation signal corresponding to a delayed signal and the input color video signal by mutual addition and subtraction to generate a luminance signal and a color signal, respectively; In the separation circuit, the low-pass filter includes frequency adjustment means for varying a cutoff frequency in response to supply of a frequency control signal, a vertical synchronization signal separation circuit for extracting a vertical synchronization signal from the input color video signal, A quadrature subcarrier generating circuit for generating a quadrature subcarrier signal obtained by shifting the subcarrier signal by 90 degrees; and supplying the input color video signal to the vertical synchronizing signal during a vertical synchronizing signal period in response to the supply of the vertical synchronizing signal. A first switch circuit for passing the quadrature subcarrier signal during a period other than a period, and a gain controlled in response to a gain control signal. A variable gain amplifier circuit for amplifying the 1H delay signal passing through the filter to generate the correlation signal, and a frequency control signal generating circuit for generating the frequency control signal in response to the supply of the quadrature subcarrier signal and the correlation signal And a gain control signal generating circuit for generating the gain control signal in response to the supply of the quadrature subcarrier signal and the luminance signal.

[0012]

FIG. 1 is a block diagram showing an embodiment of the present invention, in which components common to those in FIG. 2 are denoted by common reference characters / numerals, and FIG. The YC separation circuit of FIG.
And the control signal IM in addition to the same function as the conventional LPF 7
L whose cutoff frequency fc is controlled in response to the supply of
In addition to the PF 7A and the adders 15 and 16, a synchronization signal separation circuit 1 for separating the horizontal / vertical synchronization signal S from the input video signal I, and a vertical separation circuit 2 for extracting only the vertical synchronization signal V from the synchronization signal S A switch 5 for selectively switching between the signals IF and f in response to the supply of the vertical synchronizing signal V, and a voltage-controlled amplification (VCA) circuit 8 for gain-controlled by the signal G to amplify the signal LH and output the signal VHF. And the subcarrier signal fs
The phase shifter 9 outputs the signals f and fA by shifting the phase of c by 90 °, and the control signal I from the supplied signals VHF and fA.
A frequency control circuit 10 for generating M, a multiplier 17 for multiplying the signal f by the signal Y to generate a signal G, a switch 18 in response to the supply of the vertical synchronization signal V, and a data holding capacitor 19 Is provided.

The frequency control circuit 10 multiplies the supplied signal VHF by the signal fA to generate a signal M, and converts the voltage signal M into a control signal IM which is a current signal. A frequency control circuit 10 including a voltage-current (VI) converter 12, a switch 13 for performing a phase comparison operation of a multiplier 11 for a vertical synchronization signal period in response to supply of a vertical synchronization signal V, and a data holding capacitor 14. Is provided.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, a video signal I inputted from an input terminal T1 is supplied to an LPF 4 and a sync separation circuit 1,
As in the conventional case, the LPF 4 removes unnecessary high frequency components of the video signal I, outputs a signal IF, and supplies the signal IF to the switch 5. The sync separation circuit 1 extracts a horizontal / vertical sync signal S from the video signal I. The vertical separation circuit 2 extracts a vertical synchronization signal V from the synchronization signal S. This vertical synchronization signal V controls the switch 5.

On the other hand, the phase shifter 9 multiplies the quadrature subcarrier signal f obtained by shifting the phase of the subcarrier signal fsc supplied via the terminal Tf by 90 ° with the switch 5 by the quadrature subcarrier signal fA. To the vessel 11 respectively. Each of the two contacts of the switch 5 is supplied with the signal IF and the signal f as described above. In response to the control of the vertical synchronizing signal V, the signal IF and the vertical synchronizing signal are output except during the vertical synchronizing signal period. During the period, the signal SF that selectively passes the signal f is output.

The signal SF is supplied to the 1H delay element 6 as in the prior art. The output H of the signal SF is removed from the clock component by the LPF 7A, and the output signal LH is supplied to the VCA circuit 8. The VCA circuit 8 supplies an output signal VHF corresponding to the signal LH to each of the multiplier 11 and the adders 15 and 16.

The multiplier 11 of the frequency control circuit 10 multiplies the supplied signals VHF and fA to generate a signal M.
Here, when the cutoff frequency fc of the LPF 7A, that is, the frequency fc of the signal VHF does not deviate from a predetermined value, the phase difference between the signals VFA and fA is exactly 90 °, that is, the quadrature phase, and therefore the signal M becomes zero. This signal M
The VI converter 12 responds to the supply of
control signal IM0 having a predetermined median value which does not change c
Supply to F7A. Therefore, the LPF 7A holds the cutoff frequency fc in this state as it is. LPF7
When the cutoff frequency fc of A is lower than a predetermined value, the phase of the signal VHF is delayed by more than 90 ° from the signal fA, and the signal M has a positive polarity. In response to the supply of the positive polarity signal M, V
The I converter 12 supplies a control signal IMl for increasing the cutoff frequency fc to the LPF 7A. As a result, LPF
7A increases the cutoff frequency fc. Also, LP
If the cut-off frequency fc of F7A is higher than a predetermined value, the phase of the signal VHF is more advanced than the signal fA by 90 °,
The signal M has a negative polarity. In response to the supply of the signal M having the negative polarity, the VI converter 12 supplies a control signal IMh for lowering the cutoff frequency fc to the LPF 7A. As a result, the LPF 7A lowers the cutoff frequency fc.

When there is no correlation between adjacent scanning lines or when a video signal does not include a color signal, the switch 13
In order to avoid a malfunction of the I-converter 12, the multiplier 11 performs a phase comparison only during the vertical synchronizing signal period, and controls so as to hold the value at that time during periods other than the vertical synchronizing signal period. Thus, the multiplier 11, the VI converter 12, the switch 13
, The delay time adjustment for the 1H period can be automated.

Next, the multiplier 17 outputs a signal G in response to the supply of the signal f and the output signal Y of the adder 15. Signal S F and the signal VHF supplied to each of the adders 15 and 16
Are equal, the signal Y does not include a residual color signal component, so only the signal f is input to the multiplier 17, the voltage of the output signal G becomes 0, and the gain of the VCA circuit 8 does not change. The level of the signal VHF is kept as it is.

Next, when the level of the signal VHF signal S F smaller than, since the signal Y contains residual color signal components, the multiplier 17 and the signal Y and the signal f to the phase comparator, the output signal G gain signal increase VHF the VCA circuit 8 by a voltage of the level of S F both increase the level of the signal VHF until the same. Conversely, when the level of the signal VHF is higher than the signal S, the signal Y includes a residual color signal component of the opposite polarity, and the multiplier 17 outputs the signal Y.
The gain of the VCA circuit 8 is reduced by the voltage of the output signal G having the opposite polarity as a result of the phase comparison between the signals VHF and S.
F. The level of the signal VHF is reduced until both levels become the same.

The switch 18 performs the phase comparison operation of the multiplier 17 only during the period of the vertical synchronizing signal, similarly to the case of the multiplier 11 and the switch 13 described above. Hold the voltage.

The above operation by the adder 15 and 16 of the signal S F just the same level as 1H period delayed signal VHF
Is supplied.

[0023]

As described above, the YC separation circuit according to the present invention comprises a vertical synchronization signal separation circuit, a quadrature subcarrier generation circuit, and an input color video signal during a vertical synchronization signal period. A switch circuit that passes the quadrature subcarrier signal during the period, a variable gain amplifier circuit, and a frequency control signal generation circuit that generates a frequency control signal in response to the supply of the quadrature subcarrier signal and the correlation signal. And a gain control signal generating circuit for generating a gain control signal in response to the supply of the quadrature subcarrier signal and the luminance signal, so that the shift of the cutoff frequency of the LPF, that is, the delay of the 1H delay signal (correlation signal). By automatically correcting the time and level, these adjustments in the manufacturing process are not required, which has the effect of reducing man-hours and manufacturing costs. That.

In addition, there is an effect that an adjustment element such as a variable resistor which causes a change with time is not required, and that a characteristic deterioration due to a change with time can be prevented by forming a closed loop system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a YC separation circuit of the present invention.

FIG. 2 is a block diagram illustrating an example of a conventional YC separation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization separation circuit 2 Vertical separation circuit 4,7,7A LPF 5,13,18 Switch 6 1H delay element 8 VCA circuit 9 Phase shifter 10 Frequency control circuit 11,17 Multiplier 12 VI converter 14,19 Capacitor 15,16 Adder 20,22 Variable resistor 21 Amplifier

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-67989 (JP, A) JP-A-6-335020 (JP, A) JP-A-6-276545 (JP, A) JP-A-1- 181212 (JP, A) JP-A-61-228705 (JP, A) JP-A-61-73412 (JP, A)

Claims (2)

(57) [Claims] 1. A 1H delay element for delaying an input color video signal by one horizontal scanning period to generate a 1H delay signal, a correlation signal corresponding to a delayed video signal from which unnecessary high frequency components of the 1H delay signal have been removed, and the input color A YC separation circuit having a comb filter characteristic comprising first and second adders for generating a luminance signal and a chrominance signal by correlating by mutual addition and mutual subtraction with a video signal; A low-pass filter that removes unnecessary high-frequency components of the 1H delay signal and generates the delayed video signal; and a vertical filter that extracts a vertical synchronization signal from the input color video signal. A synchronization signal separation circuit; a quadrature subcarrier generation circuit that generates a quadrature subcarrier signal obtained by shifting the subcarrier signal by 90 degrees; A first switch circuit that allows the input color video signal to pass during periods other than the vertical synchronization signal period in response to the supply of the vertical synchronization signal, and passes the quadrature subcarrier signal during the vertical synchronization signal period; A gain variable amplifier circuit whose gain is controlled to amplify the delayed video signal to generate the correlation signal; and a first multiplication circuit that multiplies the quadrature subcarrier signal by the correlation signal to generate a first multiplied signal. A multiplier, a voltage-current conversion circuit for converting the voltage value of the first multiplication signal into a current value to generate the frequency control signal, and the voltage-current conversion circuit responding to the supply of the vertical synchronization signal during the vertical synchronization signal period. A second switch circuit for operating a first multiplier, and a frequency control signal generation circuit for generating the frequency control signal in response to the supply of the quadrature subcarrier signal and the correlation signal; A quadrature subcarrier signal and an output signal of the first adder.
YC separation circuit comprising: a gain control signal generating circuit in response to the supply of the No. generates the gain control signal. And a second multiplier for multiplying the quadrature subcarrier signal by the luminance signal to generate the gain control signal, and responsive to the supply of the vertical synchronization signal. 2. The YC separation circuit according to claim 1, further comprising: a third switch circuit for operating the second multiplier during the vertical synchronization signal period.