JP3256989B2 - Packet processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet processing apparatus for performing packet division processing.

[0002]

2. Description of the Related Art Conventional CCITTX. FIG. 3 shows a packet processing apparatus using the 25 protocol. When a packet longer than the allowable packet length of the terminal accommodated in this packet processing apparatus is sent, the layer 3 processor 24 copies the long packet in the packet data storage memory 26 into a memory so that the packet header becomes shorter. (PK
THD), a complete packet form is generated, and a packet transfer instruction including the number of bytes (BC) of the packet data and the head address (ADR) of the packet data is written on the interface memory 23. The layer 2 processor 22 writes the address field and the control field of the layer 2 directly into the transmission FIFO 21 and then sets the byte number (BC) and the start address (ADR) of the packet data in the DMA controller 25 and starts up. multiply. Activated DAM controller 2
5 sequentially writes the packet data from the packet data storage memory 26 to the transmission FIFO 21. This is transferred by the number of short packets divided and copied to perform packet division processing.

[0003]

In this conventional packet processing apparatus, a layer 3 processor expands a long packet into a short packet on a memory and attaches a packet header to each packet to perform a packet length conversion process. There is a drawback in that the processing capacity of conversion depends on the packet length, and that extra processing time is required only for the memory copy processing, which leads to a significant reduction in processing capacity.

[0004]

According to the present invention, there is provided a packet processing apparatus comprising: A packet data storage memory for storing packet data from a network; a packet data storage memory for storing packet data from a network; A layer 3 processor that performs processing of layer 3 and creates a plurality of transfer instructions corresponding to each of a plurality of data blocks divided into a predetermined number of bytes or less of the packet data stored in the packet data storage memory; . A layer 2 processor that performs processing of layer 2 and reads data from the packet data storage memory in response to the transfer command to create an output packet, wherein the layer 3 processor adds a packet header as the transfer command A packet header addition identifier designating whether or not to perform the setting, including the packet header, the number of transfer bytes, and the address of the packet data storage memory when the packet header is added; Determines the packet header addition identifier in the transfer command, and if the packet header addition is specified, the packet header in the transfer command is used as the packet header of the output packet. Data read from the packet data storage memory accordingly. It is configured to the data of the output packet.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a hardware configuration of a packet processing apparatus according to an embodiment of the present invention and a data format on a memory. The hardware block configuration is the same as that of the conventional example shown in FIG. FIG. FIG. 3 is a diagram showing a data format of 25 protocol, where (a) is a layer 2
(B) shows a layer 3 data packet format.

When the accommodated terminal can receive only 128 bytes of data, when the 512-byte data sent from the communication partner terminal via the network is in the packet data storage memory 16, the layer 3 processor 14 First, a packet transfer instruction that does not require the addition of a packet header (PKTHD) is written with the transfer byte counter (BC) set to 128 on the interface memory 13 with the packet header addition identifier (ID) = 0. Further, the layer 3 processor 14
For the 84-byte data, ID = 1, that is, a packet header needs to be added, the transfer byte counter (BC) is set to "128", and the DMA transfer start address (ADR) on the storage memory 16 is increased by 128 bytes. As a result, the packet is divided into three packet transfer instructions and written into the interface memory 13. The layer 2 processor 12 reads the packet transfer instruction on the interface memory 13, writes the address field (A) and the control field (C) in the transmission FIFO 11,
When D = 0, the DMA transfer start address (ADR) and the number of transfer bytes (BC) are set in the DMA controller 15, and when ID = 1, the packet header (PKTHD) is directly written into the FIFO 11 for transmission, The DMA transfer start address (ADR) and the number of transfer bytes (BC) are set in the controller 15, and the DMA controller 15 is started. The started DMA controller 15 transfers the packet data from the packet data storage memory 16 to the transmission FIFO 11 and stores 512-byte data in the transmission FIFO 11.
The packet is transmitted to the terminal side as four packets having 8-byte data.

[0008]

As described above, according to the present invention, since the packet division processing is performed without copying data, the packet division processing can be performed without lowering the packet processing capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. It is a figure showing the data format of 25 protocols.

FIG. 3 is a block diagram of a conventional packet processing device.

[Explanation of symbols]

11, 21 Transmission FIFO 12, 22 Layer 2 processor (X.25 Layer 2
Processing Processor) 13,23 Interface Memory 14,24 Layer 3 Processor (X.25 Layer 3)
Processing processor) 15, 25 DMA controller 16, 26 Packet data storage memory

Claims (1)

(57) [Claims] [Claim 1] CCITT Recommendation X. 25. A packet processing apparatus which processes packet data according to 25 protocols, divides the data into a plurality of packets having a predetermined length or less, and outputs the plurality of packets.
A packet data storage memory for storing packet data from the network; A layer 3 processor that performs processing of layer 3 and creates a plurality of transfer instructions corresponding to each of a plurality of data blocks divided into a predetermined number of bytes or less of the packet data stored in the packet data storage memory; . A layer 2 processor that performs processing of layer 2 and reads data from the packet data storage memory in response to the transfer command to create an output packet, wherein the layer 3 processor adds a packet header as the transfer command A packet header addition identifier designating whether or not to perform the setting, including the packet header, the number of transfer bytes, and the address of the packet data storage memory when the packet header is added; Determines the packet header addition identifier in the transfer command, and if the packet header addition is specified, the packet header in the transfer command is used as the packet header of the output packet. Data read from the packet data storage memory accordingly. Packet processing device, characterized in that the data of the output packet.