JP3253014B2 - Video encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture coding apparatus and, more particularly, to a moving picture coding apparatus for compressing a moving picture by high-efficiency coding.

[0002]

2. Description of the Related Art In recent years, a moving picture encoding apparatus has been used as a device for converting moving picture information into digital data having a smaller required band, such as a communication medium, a storage medium, or a combination thereof, for multimedia. It is being actively studied. Hereinafter, the configuration of the conventional moving picture coding apparatus will be described.

FIG. 14 is a block diagram showing a configuration of a conventional moving picture coding apparatus, and particularly shows a configuration of an input processing unit in detail. In FIG. 14, the moving picture coding apparatus includes a synchronization detector 42, a field memory 43,
It includes a difference detector 44, a frame memory 45, a PLL circuit 46, and a read circuit 47.

The sync detector 42 extracts a field sync signal from a 2-3 pull-down moving picture signal. The field memory 43 stores the moving image data at a timing synchronized with the field synchronization signal from the synchronization detector 42.
Save for the field. The difference detector 44 detects a difference between the field data output from the field memory 43 and delayed by one field time and the input moving image data. The frame memory 45 stores moving image data for one frame at a timing synchronized with the difference detection signal from the difference detector 44. The PLL circuit 46 outputs a frame synchronization signal synchronized with the difference detection signal. The read circuit 47 reads frame data from the frame memory 45 at a timing synchronized with the frame synchronization signal from the PLL circuit 46.

Before explaining the operation of the conventional moving picture coding apparatus, the principle of 2-3 pull down will be described with reference to FIG. Video sources are roughly classified into video rate materials (30 frames / sec) and film rate materials such as movies (24 frames / sec). In order to broadcast a film rate material on a television or a video, generally, the rate is converted by a telecine apparatus and the video is recorded. In the conversion, an overlapping field for adjusting the rate is generated. Specifically, as shown in FIG. 15, two frames of a movie are derived into two fields of video and three fields, respectively. This conversion process is called 2-3 pulldown. Since one of the fields derived from the three fields is a duplicated field, it becomes a redundant screen in video encoding. Therefore, if the redundant picture is removed by the preprocessing and the MPEG video encoding is performed at a source rate of 24 pictures per second, the film rate material can be encoded with high compression efficiency. However, if the duplicated field is simply removed, two even-odd reverse frames are generated successively for every ten fields. Therefore, an order conversion process for restoring the reverse is added.

FIG. 16 is a frame processing sequence diagram for explaining the operation of the moving picture coding apparatus shown in FIG. Hereinafter, the operation of the conventional moving picture coding apparatus will be described with reference to FIG. In FIG. 16, (a) shows the moving image 51 of 24 frames per second, and (b) shows the moving image 51 of 2 frames.
-3 30 frames per second pulled down TV video 5
2C, (c) TV video data 52b obtained by quantizing a TV video 52a of 30 frames per second, which is 2-3 pulled down, and (d) TV video delayed by one field output from the field memory 43. Data 53
(E) shows the field synchronization signal (FS) 54 output from the synchronization detector 42, (f) shows the difference detection signal (DS) 55 output from the difference detector 44, and (g) shows the PL
Frame synchronization signal (FRS) output from L circuit 46
(H) shows the rate-converted frame data 57 output from the readout circuit 47, respectively.

First, the synchronization detector 42 outputs a field synchronization signal (FS) 54 by extracting a vertical synchronization signal from the input television video data 52b. The input television moving image data 52b is synchronized with the field synchronization signal (FS) 54 at the timing.
The data is taken into the field memory 43. Further, at a timing synchronized with the field synchronization signal (FS) 54, the television moving image data 53 delayed by one field is read from the field memory 43 and input to the difference detector 44 together with the real-time television moving image data 52b. . The difference detector 44 compares the input two pieces of television video data on a field-by-field basis. If the error amount of the entire field is equal to or less than a preset threshold value, the difference detector 44 determines that the fields match, and the difference detection signal 55 And outputs a signal of a logic level “0” (for example, a low level signal). If the error amount is equal to or larger than the threshold value, it is determined that the fields do not match, and a signal of a logical level “1” (for example, a high level signal) is output as the difference detection signal (DS) 55. That is, the first field and the second field in the same frame
When the correlation with the field becomes low, the logical level of the difference detection signal (DS) 55 becomes “1”.

On the other hand, the television moving image data 52b is taken into the frame memory 45 in frame units at a timing synchronized with each rising of the difference detection signal (DS) 55 from "0" to "1". Here, focusing on the timing relationship between the real-time television moving image data 52b and the difference detection signal (DS) 55, each rising of the difference detection signal (DS) 55 from “0” to “1” is used as a trigger. Two fields of data following the trigger point (ie,
One frame of data) is a dynamic image 5 of 24 frames per second.
One frame corresponds to one frame of data. That is, the frame taken into the frame memory 45 is a frame from which the duplicate field generated by the 2-3 pull-down has been removed, that is, a frame corresponding to the original moving image 51. PLL
The circuit 46 generates a frame synchronization signal (FRS) 56 having a constant pulse interval (24H) synchronized with the rising edge of every other pulse among the pulses included in the difference detection signal (DS) 55. At the timing synchronized with the frame synchronization signal (FRS) 56, the readout circuit 47
The rate-converted frame data 57 is read from the frame memory 45. Rate-converted frame data 5
7 is input to the high-efficiency encoder 48 together with a frame synchronization signal (FRS) 56, and after being subjected to intra-frame encoding and inter-frame encoding, is output or transmitted.

[0009]

However, in the configuration of the above-mentioned conventional device, the structure between adjacent fields (that is, between the first field and the second field in the same frame) is used.
Since the 2-3 pull-down cycle is obtained based on the difference between the two, the difference value varies depending on the type of the image, and in some cases, an error occurs in the determination result of the difference detector 44,
There was a possibility that an accurate 2-3 pull-down cycle could not be detected.

Also, a television moving image 52a of 30 frames per second, which has been 2-3 pulled down, is edited by a video editing device or the like without considering the 2-3 pull down cycle.
If the pull-down cycle is broken, the difference detection signal 5
5 indicates unexpected behavior and the PLL circuit 46 loses lock. In such a case, during the period until the PLL circuit 46 re-locks, incorrect frame data is output and the frame synchronization signal 56 becomes discontinuous.
The operation timing of the high efficiency encoder 48 becomes unstable,
There is a problem that the operation of the high efficiency encoder 48 is broken.

When a scene such as a still image, in which a difference is unlikely to occur, continues in the 2-3 moving-down television moving image 52a at 30 frames per second, the PLL circuit 46 loses synchronization and the frame synchronization signal 56 becomes inconsistent. Since the operation becomes accurate, the operation timing of the high-efficiency encoder 48 becomes unstable, and the operation of the high-efficiency encoder 48 is broken.

In the case where a material in which subtitles and the like are superimposed by a telop device or the like is used for a television moving image 52a of 30 frames per second which has been 2-3 pulled down,
The difference detection signal 55 indicates an unexpected behavior, and the PLL circuit 46 loses lock. In such a case, while the subtitles and the like on the material disappear and the PLL circuit redraws, incorrect frame data is output and the frame synchronization signal 56 becomes discontinuous. There is a problem that the operation timing becomes unstable and the operation of the high-efficiency encoder 48 breaks down.

[0013] Further, 30 per second, which is 2-3 pulled down
When the television moving image 52a of the frame has many random noises and high frequency components, there is a problem that erroneous determination of field correlation due to random noise and erroneous determination of field correlation due to aliasing generated by high frequency components are caused.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a moving picture coding apparatus capable of always accurately detecting the position of a duplicated field without a difference value depending on the type of picture. Another object of the present invention is to provide a moving picture coding system which can always perform a stable coding process without causing a break in a processing sequence in a part where the periodicity of the input material is broken due to editing or the like. It is to provide a device. Still another object of the present invention is to cause a failure in a processing sequence even when a still image is included in an input material, a subtitle is superimposed, or a random noise or a high frequency component is included. Instead, it is an object of the present invention to provide a moving picture coding apparatus capable of always performing stable coding processing.

[0015]

According to a first aspect of the present invention, a relatively high-rate first moving image data obtained by performing a rate conversion process on a relatively low-rate first moving image data. An apparatus for re-converting the second moving image data into moving image data having the same rate as that of the first moving image data and encoding the same, and a synchronization detecting means for extracting a field synchronization signal from the second moving image data A field memory that stores the second moving image data for two fields at a timing synchronized with a field synchronization signal from the synchronization detecting means;
By detecting the difference between the field data output from the field memory and delayed by two fields and the real-time second moving image data, it is determined whether or not a correlation exceeding a predetermined reference is recognized between the compared fields. Difference detection means for outputting a difference detection signal, a PLL means for synchronizing with the difference detection signal and outputting a frame synchronization signal having the same period as the first moving image data rate, a field synchronization signal and a frame synchronization signal A frame memory that stores moving image data for one frame at a timing synchronized with the above, a frequency divider that divides a field synchronization signal and outputs a compensation frame synchronization signal, and monitors a locked state of the PLL unit. Lock detecting means for outputting a lock state signal indicating whether the apparatus is locked or unlocked; When the lock state signal indicates the lock state, the moving image data of the frame memory is selectively output, and when the lock state signal indicates the unlock state, the moving image data of the first field of the field memory is compensated. Selecting means for repeatedly outputting as the obtained moving image data, and selectively outputting a frame synchronization signal from the PLL means when the lock state signal indicates the locked state,
When the locked state signal indicates the unlocked state, the switching means for selectively outputting the compensated frame synchronization signal from the frequency dividing means, and one frame from the selecting means at the timing synchronized with the synchronization signal from the switching means. A reading unit for reading the moving image data and an encoding unit for encoding the moving image data read by the reading unit are provided.

As described above, according to the first aspect, the difference detecting means detects the difference between the field data delayed by two fields and the real-time second moving image data. The difference between the first fields or between the second fields is detected. As a result, the difference value does not vary depending on the type of the image,
The position of the duplicated field can always be detected accurately. If the PLL means is unlocked for any reason, the moving image data of the first field stored in the field memory is repeatedly output as compensated moving image data, and the frequency of the field synchronization signal is divided. Since the compensated frame synchronization signal obtained in this way is output in place of the frame synchronization signal from the PLL means, P
The stable operation of the encoding means can be ensured even during the period in which the LL is out of synchronization.

In a second aspect based on the first aspect, the difference detecting means is a self-propelled function for generating a predicted output by self-propelling when the result of the difference detection is discontinuously fragmented on a time axis. It is characterized by having.

As described above, according to the second aspect, when the difference detection result is fragmentally discontinuous on the time axis, the difference detection means runs on its own and generates a prediction output. Even if the input moving image data has slight irregularities in the period or noise, the disturbance can be overcome, stable difference detection can always be performed, and the processing sequence can be continued without failure.

In a third aspect based on the second aspect, the difference detecting means generates a prediction output based on a field synchronization signal from the synchronization detecting means.

In a fourth aspect based on the third aspect, when the difference detection result does not indicate the field correlation during the period in which the predicted output indicates the field correlation, the difference detection means sets the difference detection result on the time axis. It is characterized in that it is determined above that it is fragmentally discontinuous.

According to a fifth aspect based on the first aspect, the difference detection means is configured to perform self-running when the state in which the difference value between the compared fields is equal to or less than a predetermined value has continued for a certain period or more. It has a still image detecting function of generating an output.

As described above, according to the fifth aspect, when the state in which the difference value is equal to or smaller than the predetermined value continues for a certain period or more, the difference detection means forcibly runs to output the predicted output. Therefore, a stable difference detection signal can be always generated even when a still image or the like in which a difference component hardly occurs in the input moving image data continues.

According to a sixth aspect based on the fifth aspect, the difference detecting means generates a prediction output based on a field synchronization signal from the synchronization detecting means.

In a seventh aspect based on the first aspect, the difference detection means has an area selection function for selectively removing a specific area of the moving image data from the difference detection range.

As described above, according to the seventh aspect, the difference detection means can selectively remove a specific area of the input moving image data from the difference detection range, so that subtitles and the like are superimposed, Even when the screen partially breaks the periodicity, it is possible to always perform stable difference detection by selectively removing the part from the difference detection area.

According to an eighth aspect, in the first aspect, the second aspect is provided.
Further provided with an image filter means provided at the first stage of the input of the moving image data for removing the noise component and the high frequency component contained in the second moving image data.

As described above, according to the eighth aspect, the noise component and the high frequency component of the moving image data are removed at the first stage of the input of the moving image data.
It is possible to prevent a difference detection error due to aliasing caused by random noise and excess high frequency components.

In a ninth aspect based on any of the first to eighth aspects, the first moving image data is movie moving image data of 24 frames per second, and the second moving image data is This is moving image data for television of 30 frames, and the rate conversion process is a 2-3 pull-down process.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing a configuration of an image coding apparatus according to a first embodiment of the present invention. In FIG. 1, an image encoding apparatus according to the present embodiment includes a synchronization detector 102, a field memory 1
03, a difference detector 104, and a frame memory 105.
, A PLL circuit 106, a lock detector 107, a selection circuit 108, a frequency divider 109, a switching circuit 110, a readout circuit 111, and a high-efficiency encoder 112. The selection circuit 108 includes a field memory 108a and a switch 108b.

The sync detector 102 extracts a field sync signal from the video data that has been 2-3 pulled down.
The field memory 103 stores moving image data for two fields at a timing synchronized with the field synchronization signal (FS) from the synchronization detector 102. Difference detector 104
Detects a difference between field data output from the field memory 103 and delayed by two fields and real-time moving image data, and outputs a difference detection signal (DS). The frame memory 105 stores moving image data for one frame at a timing synchronized with a frame synchronization signal (FRS) from the PLL circuit 106. PLL circuit 106
Outputs a frame synchronization signal (FRS) synchronized with the difference detection signal (DS). The lock detector 107
The lock state of the LL circuit 106 is monitored, and a lock state signal (LS) is output. The selection circuit 108 selectively outputs the moving image data of the frame memory 105 and the moving image data of only the first field of the field memory 103 according to the lock state signal (LS). The divider 109 is
The frequency of the field synchronization signal (FS) is divided to output a compensation frame synchronization signal (FRS2). The switching circuit 110 receives the frame synchronization signal (F) in response to the lock state signal (LS).
RS) and the compensated frame synchronization signal (FRS2) are selectively output. The readout circuit 111 includes the switching circuit 11
The frame data is read from the selection circuit 108 at the timing of the output of 0. The high-efficiency encoder 112 performs intra-frame coding and inter-frame coding of image data.

FIGS. 2 and 3 are diagrams showing a frame processing sequence for explaining the operation of the moving picture coding apparatus of FIG. 1. In particular, FIG. 2 shows a frame processing sequence in a normal operation. 3 shows a frame processing sequence at the time of 2-3 pull-down failure. The operation of the moving picture coding apparatus of FIG. 1 will be described below with reference to FIGS. In FIG. 2 and FIG. 3, the logic level “0” of each signal corresponds to the low level, and the logic level “1” corresponds to the high level. However, the relationship may be reversed. That is, the video encoding device of the present embodiment may be configured to operate with negative logic. This is the same for the moving picture coding devices of the other embodiments.

First, with reference to FIG. 2, an operation in the case where the input television moving image data has a normally continuous 2-3 pull-down cycle will be described. In FIG.
(A) is a moving image 21 of 24 frames per second, (b) is a television moving image 22a of 30 frames per second obtained by 2-3 pulldown of the moving image 21, and (c) is a television image of 30 frames per second obtained by performing 2-3 pulldown. TV video data 22b obtained by quantizing the video 22a is shown in FIG.
(E) shows the field synchronization signal (FS) 24 output from the synchronization detector 102, and (f) shows the difference output from the difference detector 104. Detection signal (DS) 25
(G) shows the frame synchronization signal (FRS) 26 output from the PLL circuit 106, (h) shows the compensation frame synchronization signal (FRS2) 27 output from the frequency divider 109,
(I) shows the lock state signal (LS) 28 outputted from the lock detection circuit 107, (j) shows the encoded frame data 29b outputted from the readout circuit 111, and (k) shows the output from the switching circuit 110. The encoded frame synchronization signal 29a is shown.

The synchronization detector 102 outputs a field synchronization signal (FS) 24 by extracting a vertical synchronization signal from a 2-3 moving down television moving image 22a of 30 frames per second. The television moving image data is synchronized with the field synchronization signal (FS) 24 at the timing.
The data is taken into the field memory 103. Further, at a timing synchronized with the field synchronization signal (FS) 24,
The television moving image data 23 delayed by two fields is read from the field memory 103 and input to the difference detector 104 together with the real-time television moving image data 22b.

The difference detector 104 compares the input two pieces of television video data on a field-by-field basis. If the error amount of the entire field is equal to or less than a preset threshold value, it is determined that the two fields match, and the difference detection is performed. A signal of logic level "0" is output as the signal 25. If the error amount is equal to or larger than the threshold value, it is determined that the fields do not match, and a signal of logic level "1" is output as the difference detection signal (DS) 25. . That is, when an overlapping frame having a high correlation between the first fields of the adjacent frames due to the 2-3 pull-down is detected, the logical level of the difference detection signal (DS) 25 becomes “0”.

The PLL circuit 106 outputs a difference detection signal (D
S) Generates a frame synchronization signal (FRS) 26 with a constant pulse interval (24 Hz) synchronized with the falling edge of each pulse included in 25). On the other hand, the television moving image data 22b is taken into the frame memory 105 on a frame basis at a timing synchronized with the field synchronization signal (FS) 24 and the frame synchronization signal (FRS) 26. At this time, the frame memory 105 always fetches the television moving image data 22b from the beginning of all fields at the timing synchronized with the field synchronization signal (FS) 24 regardless of the frame synchronization signal (FRS) 26. If the frame synchronization signal (FRS) 26 does not transition at the time of starting to fetch data into the first field area in its own memory area or during the fetching, the fetched field is discarded and the television moving image is deleted. The next field of the data 22b is taken as the first field. Here, the real-time television moving image data 22b and the frame synchronization signal (FRS) 26
Focusing on the timing relationship with, the rising of the frame synchronization signal (FRS) 26 from “0” to “1” as a trigger, the data for the two fields that follow from the trigger point (that is, the data for one frame) is , 24 per second
This corresponds to the data of one frame of the moving image 21 of the frame. That is, the frame fetched into the frame memory 105 is a frame from which duplicate fields generated by the 2-3 pull-down have been removed, that is, a frame corresponding to the original moving image 21.

The lock detection circuit 107 is a PLL circuit 10
6 is constantly monitored, and if the 2-3 pull-down cycle of the television moving image 22a is normally continued, the logic level of the lock state signal (LS) 28 is set to "1" and the PLL circuit 1
06 is locked. When the logic level of the lock state signal (LS) 28 is “1”, the switch 108 b in the selection circuit 108 allows the frame data from the frame memory 105 to pass, and the readout circuit 111 outputs the frame synchronization signal (FRS) 26. The frame data is read from the selection circuit 108 at the timing synchronized with the frame data and output as the encoded frame data 29b. Switching circuit 110
Indicates that the logic level of the lock state signal (LS) 28 is "1"
, The frame synchronization signal (F
RS) 26 as an encoded frame synchronization signal 29a. The coded frame synchronization signal 29a and the coded frame data 29b are input to the high-efficiency coder 112, and are subjected to intra-frame coding and inter-frame coding.

Next, with reference to FIG. 3, an operation in the case where the 2-3 pull-down period of the input television moving image data has failed will be described. In FIG. 3, (a) is 2 per second.
The dynamic image 31 of 4 frames is shown.
TV movie 32 at 30 frames per second with 3 pull-downs
(c) is TV video data 32b obtained by quantizing a TV video 32a of 30 frames per second, which is 2-3 pulled down, and (d) is TV video data delayed by two fields output from the field memory 103. 33,
(E) shows the field synchronization signal (FS) 34 output from the synchronization detector 102, (f) shows the difference detection signal (DS) 35 output from the difference detector 104, and (g) shows the PL.
The frame synchronization signal (FR
S) 36, (h) a compensated frame synchronization signal (FRS2) 37 output from the frequency divider 109, and (i) a lock state signal (LS) output from the lock detection circuit 107.
38, (j) the encoded frame data 39b output from the readout circuit 111, and (k) the switching circuit 110.
Respectively show the encoded frame synchronizing signal 39a output from.

If the 2-3 pull-down cycle of the television video 32a breaks down, the periodicity of the difference detection signal (DS) 35 output from the difference detector 104 breaks down, and the PLL circuit 10
6 is unlocked. The lock detection circuit 107 immediately changes the logic level of the lock state signal (LS) 38 to “0”.
To notify that the PLL circuit 106 has lost synchronization. When the logic level of the lock state signal (LS) becomes “0” (PLL unlock state), the switch 108 b in the selection circuit 108 has finished sending the frame data of the frame memory 105 selected at that time. Thereafter, the field memory 108a is selected from the beginning of the next frame screen, and the first field data is transmitted. That is, at this time, the selection circuit 108 stores the first field data read from the field memory 103 in the field memory 1
By temporarily storing the first field data at 08a, the same first field data is repeatedly output twice. As a result, one compensation frame data is constituted by the same first field data.

The frequency divider 109 always divides the frequency of the field synchronization signal (FS) 34 output from the synchronization detector 102, thereby providing a compensating frame synchronization signal (of the same phase and the same rate as the original image 31 of 24 frames per second). FRS2) 37 is output. When the logic level of the lock state signal (LS) becomes “0” (PLL unlock state), the switching circuit 110
The output of the PLL circuit 106 is immediately switched to the output of the frequency divider 109, and the high-efficiency encoder 1 is used as the encoded frame synchronization signal 39a using the compensated frame synchronization signal (FRS2) 37.
12 is output. The read circuit 111 includes the selection circuit 10
8 is read twice at a timing synchronized with the encoded frame synchronization signal 39a by repeating the first field data twice to compose one frame by repeating the first field data twice.
High-efficiency encoder 11 as encoded frame data 39b
Output to 2.

When the 2-3 pull-down period of the television video 32a is broken, the periodicity of the difference detection signal (DS) 35 output from the difference detector 104 is restored, and the PLL circuit 1
06 completes the re-locking, the lock detection circuit 107
Immediately sets the logic level of the lock state signal (LS) 38 to "1" and notifies that the PLL circuit 106 has recovered synchronization. The switch 108 b in the selection circuit 108 sets the logic level of the lock state signal (LS) 38 to “1” (PLL
When the lock state is reached, the compensation frame data obtained from the currently selected field memory 108a (that is, the compensation frame data obtained by repeating the first field data of the field memory 103 twice) is transmitted. After the end, the frame memory 105 is selected from the top of the next frame screen, and normal frame data starts to be transmitted. When the logic level of the lock state signal (LS) 38 becomes "1" (PLL lock completed state), the switching circuit 110 immediately switches from the output of the frequency divider 109 to the output of the PLL circuit 106, and the frame synchronization signal (FRS) 36 is output to the high-efficiency encoder 112 as an encoded frame synchronization signal 39a. Readout circuit 11
1 reads the frame data from the selection circuit 108 at a timing synchronized with the encoded frame synchronization signal 39a, and outputs the frame data to the high-efficiency encoder 112 as encoded frame data 39b.

As described above, in the moving picture coding apparatus according to the present embodiment, the 2-3 pull-down period is broken and the PLL circuit 1
Until 06 is redrawn, the compensation frame obtained by repeating the first field twice is encoded with high efficiency.

As described above, according to this embodiment, based on the difference between the same fields in adjacent frames,
Since three pull-down periods are obtained, an intermittently generated overlapping field can be compared with the same field preceding it. As a result, the field correlation obtained when a duplicated field occurs is extremely high and does not vary depending on the type of image.
The pull-down cycle can be detected. Further, even if the 2-3 pull-down cycle of the television video 22a is broken due to editing work or the like, compensation frame data and a compensation frame synchronization signal are generated until the PLL circuit 106 completes re-pulling. Thus, the original frame data and the frame synchronization signal are substituted, so that the PLL circuit 46 does not lose the lock, and the high-efficiency encoder 48 can always perform the encoding operation stably. .

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
It is a block diagram showing the composition of the picture coding device concerning an embodiment. In FIG. 4, the image encoding apparatus of the present embodiment is different from the configuration of the first embodiment shown in FIG. 1 in that field data output from the field memory 103 and delayed by two fields and real-time moving image data A difference detector 401 with a self-propelled function that generates a predicted output by self-propelling even if the difference is fragmentally discontinuous on the time axis, instead of the difference detector 104 that detects the difference It is.
Other configurations are the same as those of the first embodiment. Corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

FIG. 5 is a block diagram showing a more detailed configuration of the difference detector 401 with a self-running function shown in FIG. In FIG. 5, the difference detector 401 with a free-running function includes a difference calculation device 401a, a reference value holding circuit 401b, a comparator 401c, a field counter 401d, and a gate logic circuit 401e. Difference detection device 40
1a calculates and outputs a difference value between field data output from the field memory 103 and delayed by two fields and real-time moving image data,
Outputs a difference detection signal. The reference value holding circuit 401b
A reference value serving as a reference for determining whether or not there is a difference is held and output as data. The field counter 401d is
A field synchronization signal (FS) from the synchronization detector 102 is measured, and a prediction signal is output. The comparator 401c receives the prediction signal from the field counter 401d as an enable signal, is activated when the prediction signal is at a high level, and outputs difference value data output from the difference calculation device 401a and a reference value holding circuit 401b. Is compared with the reference value data output from. If the difference value is larger than the reference value, the judgment signal is output at a low level, and if it is smaller, the judgment signal is output at a high level. When the prediction signal from the field counter 401d is at a low level, the comparator 401c is inactivated and its output is at a high level. Gate logic circuit 401e
When the determination signal from the comparator 401c is at a high level, the differential detection signal (DS) from the difference calculation device 401a is passed and output as a self-running difference detection signal (DS2). Counter 401d
The self-running difference detection signal (DS
Output as 2).

FIG. 6 is a diagram showing a frame processing sequence for explaining the operation of the moving picture coding apparatus of FIG. Hereinafter, the operation of the video encoding device shown in FIG. 4 will be described with reference to FIG. In FIG. 6, (e) shows a free-running difference detection signal (DS2) 55 output from the difference detector 401 with a free-running function. The difference detector 401 with the self-running function includes the field counter 4 inside as described above.
01d, and has a function of predicting a place where the next difference detection becomes minimum. Then, even if the difference calculation result does not become minimal contrary to the prediction, the self-running difference detection signal (DS
2) Output 55. Other operations are the same as those of the first embodiment (see FIGS. 1 to 3).

As described above, according to the second embodiment,
A PLL circuit 10 is added to the input television moving image data 22b.
Even if there is a slight 2-3 pull-down anomaly point, noise, or the like that does not cause loss of lock, the prediction difference detection is performed based on the own prediction result even if the difference calculation result does not become minimal contrary to the prediction. Self-running difference detection signal (DS2)
Since 55 is output, the processing sequence can be continued without failure.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
It is a block diagram showing the composition of the picture coding device concerning an embodiment. In FIG. 7, the configuration of the image encoding apparatus of the present embodiment differs from that of the first embodiment shown in FIG. 1 in that field data output from the field memory 103 and delayed by two fields and real-time moving image data A difference calculation result is also output as a difference value instead of the difference detector 104 that detects a difference between the static detection signal and a static value that forcibly runs to generate a prediction output if the difference value is equal to or less than a prescribed value for a predetermined period. The difference is that a difference detector 601 with an image detection function is provided.
Other configurations are the same as those of the first embodiment. Corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

FIG. 8 is a block diagram showing a more detailed configuration of the difference detector 601 with the still image detection function shown in FIG. 7, a difference detector 601 with a still image detection function includes a difference calculation device 601a, a still image determination reference value holding circuit 601b, a comparator 601c, and a measurement timer 6
01f, a field counter 601d, and a gate logic circuit 601e. Difference detection device 601
“a” calculates a difference value between the field data output from the field memory 103 and delayed by two fields and the real-time moving image data, outputs the data, and outputs a difference detection signal at the same time. Still image determination reference value holding circuit 60
Reference numeral 1b holds a reference value serving as a reference when determining a still image / moving image and outputs the data. The comparator 601c compares the difference value data output from the difference calculation device 601a with the reference value data output from the still image determination reference value holding circuit 601b, and if the difference value is larger than the reference value, the moving image And the comparison signal is output at a high level. If the comparison signal is smaller, the image is determined as a still image and the comparison signal is output at a low level. The measurement timer 601f measures a period during which the comparison signal is at a low level, and outputs a determination signal at a low level when the low level period of the comparison signal continues for a specified time or more. The field counter 601d measures a field synchronization signal (FS) from the synchronization detector 102 and outputs a prediction signal. The gate logic circuit 601e includes a measurement timer 601
f when the determination signal from f is at a high level
1a is passed and output as a self-running difference detection signal (DS2). When the determination signal is at a low level, a prediction signal from the field counter 601d is passed and output as a stationary part difference detection signal (DS3). I do.

FIG. 9 is a diagram showing a frame processing sequence for explaining the operation of the moving picture coding apparatus of FIG. Hereinafter, the operation of the video encoding device shown in FIG. 7 will be described with reference to FIG. FIG. 9E shows a still part difference detection signal (DS3) 75 output by the difference detector 601 with a still image detection function. As described above, the difference detector 601 with a still image detection function also outputs the difference calculation result as a difference value. A stationary part difference detection signal (DS3) 75, which is a detection signal, is output. Other operations are the same as those of the first embodiment (see FIGS. 1 to 3).

As described above, according to the third embodiment,
Even if there is a continuous still image scene in the input TV moving image data 22b, if the difference calculation result is contrary to the prediction and is equal to or less than a specified value for a certain period, the self-running is forcibly performed to the own prediction result. Since the stationary part difference detection signal (DS3) 75, which is a prediction difference detection signal, is output based on this, the processing sequence can be continued without failure.

(Fourth Embodiment) FIG. 10 is a block diagram showing a configuration of an image coding apparatus according to a fourth embodiment of the present invention. In FIG. 10, the difference between the image encoding device of the present embodiment and the configuration of the first embodiment shown in FIG.
Instead of the difference detector 104 for detecting the difference between the field data output from the field memory 103 and the field data delayed by two fields and the real-time moving image data, a specific area of the moving image data is selectively selected from the difference detection range. The difference is that a difference detector 801 with an area selection function to remove is provided.
Other configurations are the same as those of the first embodiment. Corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

FIG. 11 is a block diagram showing a more detailed configuration of the difference detector 801 with the area selection function shown in FIG. In FIG. 11, a difference detector 801 with an area selection function includes first and second line counters 801a and 801d and first and second pixel counters 801a and 801d.
1b and 801e, and first and second gate circuits 80
1c and 801f, and a difference detector 801g. The first line counter 801a counts horizontal synchronization signal pulses of moving image data delayed by two fields output from the field memory 103, and after counting a predetermined number of skip lines, sets the first line start signal to high level, When the predetermined number of valid lines has been counted, the first line start signal is set to a low level, and the low level is maintained until the last line of one screen. First pixel counter 801
b counts the number of pixels in one line of moving image data delayed by two fields output from the field memory 103, and after counting a predetermined number of skipped pixels, sets the first pixel start signal to a high level and sets a predetermined validity After the number of pixels is counted, the first pixel start signal is set to a low level, and the low level is maintained until the end of one line.
When the first line start signal and the first pixel start signal are each at a high level, the first gate circuit 801c opens the gate to pass the moving image data and output the first area selection video data. On the other hand, the second line counter 801d counts a horizontal synchronization signal pulse of real-time moving image data, sets a second line start signal to a high level after counting a predetermined number of skip lines, and counts a predetermined number of valid lines. Then, the second line start signal is set to the low level, and the low level is maintained until the last line of one screen. The second pixel counter 801e counts the number of pixels in one line of real-time moving image data, sets the second pixel start signal to a high level after counting a predetermined number of skipped pixels, and counts a predetermined number of valid pixels. The second pixel start signal is set to a low level, and the low level is maintained until the end of one line. When the second line start signal and the second pixel start signal are each at a high level, the second gate circuit 801f opens the gate and passes the moving image data to output the second area selection video data. The difference detector 801g compares the first area selection video data with the second area selection video data.
The difference from the area selection video data is calculated, and an area difference detection signal (DS4) is output.

FIG. 12 is a diagram showing the structure of an input field image for explaining the operation of the moving picture coding apparatus of FIG. Hereinafter, the operation of the video encoding device shown in FIG. 10 will be described with reference to FIG. In FIG. 12, the field image 9 of the input television moving image data 22b is shown.
01 includes a subtitle area 902 and a selection area 903. In the subtitle area 902, subtitles and the like are superimposed at a video rate of 30 frames per second, and the screen partially breaks down by 2-3 pull-down. The selection area 903 is, in the input field image 901,
This is the part where the subtitle area 902 escaped. The difference detector 801g in the difference detector 801 with the area selection function is
By the operation of the above-described first and second line counters 801a and 801d, first and second pixel counters 801b and 801e, and first and second gate circuits 801c and 801f, a predetermined selection area 9 is determined.
03, the difference detection is performed, and the subtitle area 902 is excluded from the difference detection targets. Other operations are the same as those of the first embodiment (see FIGS. 1 to 3).

As described above, according to the fourth embodiment,
Since a specific area of the input television video is selectively excluded from the difference detection range, even when the subtitles are superimposed and the screen partially breaks down by 2-3 pull-down. By selectively removing the portion from the difference detection area, stable difference detection can be performed, and the processing sequence can be continued without failure.

(Fifth Embodiment) FIG. 13 is a block diagram showing a configuration of an image coding apparatus according to a fifth embodiment of the present invention. The difference between the image encoding device of the present embodiment and the configuration of the first embodiment shown in FIG.
01 is provided at the first stage of moving image data input. Other configurations are the same as those of the first embodiment. Corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

In the moving picture converter shown in FIG. 13, an image filter 1001 includes a filter (for example, a two-dimensional median filter or a three-dimensional recursive filter) for removing a noise component of an input moving picture, and a high-frequency component for removing the input moving picture. (E.g., a one-dimensional horizontal filter or a two-dimensional spatial filter), and removes noise components and high-frequency components included in moving image data. Other operations are the same as those of the first embodiment (see FIGS. 1 to 3).

As described above, according to the fifth embodiment,
By newly providing the image filter 1001, the noise component and the high frequency component of the input television moving image can be removed in advance, so that it is possible to prevent the occurrence of the difference detection error due to the aliasing caused by the random noise and the excess high frequency component. Since a stable difference detection can always be performed, the processing sequence can be continued without failure.

According to each embodiment described above,
Although the frame memory 105 that stores moving image data in units of frames is used, the frame data may be configured by outputting the same data twice using a field memory that stores moving image data in units of fields. .
The self-running function of the difference detector 401 with a self-running function and the difference detector 601 with a still image detection function can also be realized by outputting a prediction signal using a feedback synchronous circuit such as a PLL.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image encoding device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a frame processing sequence for explaining the operation of the moving picture coding apparatus of FIG. 1, and particularly shows a frame processing sequence in a normal operation.

FIG. 3 is a diagram showing a frame processing sequence for explaining the operation of the moving picture coding apparatus in FIG. 1;
3 shows a frame processing sequence at the time of 3 pull-down failure.

FIG. 4 is a block diagram illustrating a configuration of an image encoding device according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a more detailed configuration of a difference detector with a self-running function shown in FIG. 4;

FIG. 6 is a diagram showing a frame processing sequence for explaining the operation of the moving picture coding apparatus in FIG. 4;

FIG. 7 is a block diagram illustrating a configuration of an image encoding device according to a third embodiment of the present invention.

8 is a difference detector 6 with a still image detection function shown in FIG.
It is a block diagram which shows the more detailed structure of No. 01.

9 is a diagram showing a frame processing sequence for explaining the operation of the moving picture coding device in FIG. 7;

FIG. 10 is a block diagram illustrating a configuration of an image encoding device according to a fourth embodiment of the present invention.

11 is a block diagram showing a more detailed configuration of a difference detector with area selection function 801 shown in FIG.

12 is a diagram illustrating a configuration of an input field image for explaining an operation of the video encoding device in FIG. 10;

FIG. 13 is a block diagram illustrating a configuration of an image encoding device according to a fifth embodiment of the present invention.

FIG. 14 is a block diagram illustrating a configuration of a conventional video encoding device.

FIG. 15 is a diagram for explaining the principle of 2-3 pull-down.

FIG. 16 is a frame processing sequence diagram for explaining the operation of the video encoding device shown in FIG. 14;

[Explanation of symbols]

 Reference Signs List 102 synchronization detector 103 field memory 104 difference detector 105 frame memory 106 PLL circuit 107 lock detection circuit 108 selection circuit 109 frequency divider 110 switching circuit 111 readout circuit 112 high efficiency coding Detector 401: Difference detector with self-running function 601: Difference detector with still image detection function 801: Difference detector with area selection function 1001: Image filter

Claims (9)

(57) [Claims] 1. A relatively high-rate second moving image data obtained by performing a rate conversion process on a relatively low-rate first moving image data is referred to as a first moving image data. An apparatus for encoding after re-converting to moving image data of the same rate, comprising: a synchronization detecting unit that extracts a field synchronization signal from the second moving image data; and a synchronization unit that synchronizes with a field synchronization signal from the synchronization detection unit. A field memory for storing two fields of the second moving image data at a timing of detecting the difference, and detecting a difference between the field data output from the field memory delayed by two fields and the real time second moving image data. A difference detection means for outputting a difference detection signal indicating whether or not a correlation equal to or greater than a predetermined reference is recognized between the fields to be compared; PLL means for synchronizing with the difference detection signal and outputting a frame synchronizing signal having the same period as the rate of the first moving image data, and the moving image data at a timing synchronizing with the field synchronizing signal and the frame synchronizing signal Memory for storing one frame, frequency dividing means for dividing the field synchronization signal and outputting a compensation frame synchronization signal, monitoring the lock state of the PLL means, and checking whether the PLL means is in the locked state. Lock detecting means for outputting a lock state signal indicating whether the apparatus is in a lock state, and when the lock state signal indicates a lock state, selectively outputs moving image data of the frame memory; When the unlocked state is indicated, the moving image data of the first field of the field memory is compensated. Selecting means for repeatedly outputting as the moving image data; and selectively outputting a frame synchronization signal from the PLL means when the lock state signal indicates a lock state, wherein the lock state signal indicates an unlock state. Switching means for selectively outputting a compensated frame synchronizing signal from the frequency dividing means, and reading means for reading one frame of moving image data from the selecting means at a timing synchronized with the synchronizing signal from the switching means. And a coding unit for coding the moving image data read by the reading unit. 2. The method according to claim 1, wherein the difference detecting means has a self-running function of generating a predicted output by self-running when the difference detection result is fragmented discontinuously on a time axis. Do
The video encoding device according to claim 1. 3. The moving picture coding apparatus according to claim 2, wherein said difference detection means generates said prediction output based on a field synchronization signal from said synchronization detection means. 4. If the difference detection result does not indicate a field correlation during a period in which the prediction output indicates a field correlation, the difference detection means may make the difference detection result fragmentally discontinuous on a time axis. The moving picture coding apparatus according to claim 3, wherein the moving picture coding apparatus determines that the moving picture has been read. 5. A still image detecting function for generating a predicted output by self-running when a state in which a difference value between fields to be compared is equal to or less than a predetermined value continues for a predetermined period or more. The moving picture coding apparatus according to claim 1, wherein the moving picture coding apparatus is provided. 6. The moving picture coding apparatus according to claim 5, wherein said difference detecting means generates said prediction output based on a field synchronization signal from said synchronization detecting means. 7. The moving picture code according to claim 1, wherein said difference detecting means has an area selecting function for selectively removing a specific area of moving picture data from a difference detection range. Device. 8. The image processing apparatus according to claim 1, further comprising: an image filter provided at an initial stage of the input of the second moving image data, for removing a noise component and a high frequency component included in the second moving image data. 5. The video encoding device according to item 1. 9. The first moving image data is movie moving image data of 24 frames per second, the second moving image data is television moving image data of 30 frames per second, and the rate conversion is performed. The process is a 2-3 pull-down process.
A moving picture encoding device according to claim 1.