JP3249998B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which performs high-speed and multifunctional operations.

[0002]

2. Description of the Related Art Conventionally, a discrete-time cellular neural network (Discrete-Time Cellular Neutral) has been used as an architecture capable of processing information at a very high speed by parallel computation.
ral Networks) is known (literature: H. Harrer et al., IEEE Trans. Neural Networks,
vol.3, 466, 1992.). It arranges information processing elements called cells on a plane and operates them in parallel, and is suitable for high-speed processing of two-dimensional information such as image information. Each cell evolves in time with an algorithm as shown in Equation 1 below.

[0003]

(Equation 1)

[0004] Here, x ^c (k) is what the state at time k of the cell c, y ^c (k) is the output, the parameters for the i ^c is the threshold adjustment, the external input value with u ^d the cell d Yes,
a ^c _d, b ^c _d are parameters of the weighting. Also, N _r
(C) shows the vicinity of the cell c. For example, in the case of a hexagonal lattice, the smallest neighborhood is indicated by a hatched portion in FIG . Here, the weighting coefficients and inputs are analog values, but the outputs are binary. The weighting coefficient has translation symmetry. That is, all cells have the same coefficient. Coefficients a ^c _d weighting, by choosing b ^c _d appropriate, edge Detection, noise removal, various functions such as discrete convolution can be realized.

[0005]

Although such a semiconductor device can be manufactured by using a known technique,
A large number of transistors are required just to realize the function of one cell, and sufficient integration is difficult. For example, in the example of the above-mentioned reference document, this is formed using CMOS. However, one cell requires 290 μm × 275 μm, and a chip of 1 cm × 1 cm only integrates about 30 × 30 cells. Can not. Therefore, a practical treatment with sufficient decomposition ability was impossible.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device capable of obtaining a high-speed and sufficient decomposition capability.

[0007]

In order to achieve the above object, the present invention provides a logic gate using a monostable-bistable transition of a circuit in which elements exhibiting N-type negative resistance characteristics are connected in series. It constitutes a cell.

[0008]

In the present invention, a cell having an extremely small area can be realized by forming a cell by a logic gate using a monostable-bistable transition, and a sufficiently large number of cells can be integrated.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a view for explaining a basic structure of an embodiment of a semiconductor device according to the present invention. In this embodiment, a current variable negative resistance element exhibiting an N-type negative resistance characteristic is formed by two. A monostable-bistable logic gate connected in series is used. The logic gate includes a first current variable negative resistance element D ₁ having an input terminal I ₁ ~I ₅ example of performing current control as shown in FIG. 1, as well as for example the input terminal I ₆ ~I ₉ A second current variable negative resistance element D ₂ is connected in series;
The connection point is an output terminal O, and the drive voltage V _bias is applied to this series circuit.

[0010] The logic gate thus configured has a first
Compares the current variable negative resistance device D ₁ of the current amount of the second current variable negative resistance element D _2, when the first current variable negative resistance element D ₁ side is larger, outputs a high voltage V _H And the second
When the current amount of the current variable negative resistance element D ₂ is larger, it outputs a low voltage V _L. Here, the voltage V _H is set to the logical value “1”.
And the voltage V _L is mapped to the logical value “−1”. At this time, the input to the _first current variable negative resistance element D _{1 corresponds} to the case where the weight is positive, and the input to the second current variable negative resistance element D ₂ corresponds to the case where the weight is negative. Can be.

Since the magnitude of the weighting is proportional to the gate width, an analog weighting can be realized by changing this for each input. However, since the first current variable negative resistance element D ₁ in the emitter at the time of switching (source) potential is high, the proportionality constant of the weighting must be changed between positive and negative. In short, it suffices to determine the amount of change in the peak current so as to be proportional to the weight.

One cell is constituted by the logic gate having such a structure. Here, since the time evolution of the cell it is necessary to feed back the output to itself, constituted by one cell C as shown in FIG. 2 and two logic gates G _A logic gate G _B. Connect the output of the logic gate G _B of the logic gate G _A same cell and its neighboring cell to the input of, to the input of the logic gate G _B connects the output of the logic gate G _A of the same cell. At this time, FIG.
(A), by applying a driving voltage V _bias as shown in (b) to each of the logic gates G _A and logic gates G _B,
The flow of information is as shown in FIGS. 2A and 2B, and the above-described algorithm can be expressed by two phases. In this case, the logic gate G _A and logic gates G _B, of course, the input u ^d and the threshold adjustment parameter i ^c from the outside
To be given constantly.

According to such a configuration, since one cell can be realized with a very small number of current variable negative resistance elements, the cell area can be extremely reduced to 1/100 or less of the conventional one.
Therefore, many cells can be integrated, and large-scale data, which has been difficult in the past, can be processed at high speed. Further, in this embodiment, since a logic gate utilizing a monostable-bistable transition is used, a feature that the speed is not deteriorated even if the fanout is large can be obtained. Therefore, in an application with many fan-outs, an extremely high-speed operation can be performed as compared with the related art. In this embodiment, the hexagonal lattice arrangement has been described as an example, but it goes without saying that this arrangement may be another arrangement, for example, a rectangular lattice.

FIG. 4 is a diagram for explaining an example of the configuration of the monostable-bistable logic gate described in FIG. 1. In FIG. 4, two monostable-bistable logic gates are connected in series to form a monostable-bistable logic gate. 1 shows an element in which a junction gate is provided in a resonant tunnel diode as one of the variable current negative resistance elements. Hereinafter, the configuration of this element will be described with reference to cross-sectional views. In FIG. 4, reference numeral 11 denotes a semi-insulating GaAs substrate,
2 has a thickness of 6 doped with, for example, 2 × 10 ¹⁸ cm ⁻³ of Si.
000 ° n ⁺ -GaAs buffer layer, 13 is, for example, 5
× 10 ¹⁷ cm ⁻³ Si-doped 500 ° thick n ⁻
An emitter layer 14 made of GaAs;
A first barrier layer made of 0 ° undoped AlAs, 1
Reference numeral 5 denotes a well layer made of undoped GaAs having a thickness of 50 °, for example, and reference numeral 16 denotes a second barrier layer made of undoped AlAs also having a thickness of 50 °.

Further, 17 is, for example, 5 × 10 ¹⁷ cm ^-3 S
call i made from n-GaAs with a thickness of 500Å doped
The collector layer 18 is a collector contact layer made of, for example, 3000 nm thick n ⁺ -GaAs doped with 2 × 10 ¹⁸ cm ⁻³ of Si. The crystal is grown by, for example, a molecular beam epitaxy method, and after the growth, mesa etching is performed to form a resonant tunnel diode as shown in FIG.

[0016] 19 collector electrode, Emi 20 formed by deposition and alloying of for example AuGe / Ni
The electrode 21 is, for example, Ni / Zn / Au / Ti / Au
(50 そ れ ぞ れ / 160Å / 1000Å / 10 respectively)
00 ° / 1000 °) and a control electrode 22 alloyed at 400 ° C., 22 is a p ⁺ region formed by Zn diffused from the control electrode 21, and 23 is a high resistance formed by ion implantation of, for example, H ^+. Layer. In addition, not only one control electrode 21 but a plurality of control electrodes 21 can be provided.
Further, the size of the contact portion with the diode can be changed for each electrode.

Since the area of the resonant tunnel diode thus configured is determined by the extension of the depletion layer of the pn junction, the current flowing between the emitter and the collector can be controlled by the voltage applied to the control electrode 21. is there. Two such resonant tunneling diodes are connected in series, and the connection point is used as an output terminal.
_{When a bias} is applied and applied to the control electrode 21, the peak current can be changed by the voltage applied to the control electrode 21 because the flowing current is the sum of the two. Therefore, a logic operation using the monostable-bistable transition can be performed.

In the structure shown in FIG. 4, the emitter layer 1 is provided as a device having a junction gate provided in a resonant tunneling diode.
The same effect can be obtained by using an element in which the control electrode 21 is formed by Schottky bonding the control electrode 21 to each side surface from 3 to the collector layer 17.

FIG. 5 is a diagram for explaining another example of the configuration of the monostable-bistable logic gate described with reference to FIG.
Uses a semiconductor logic circuit in which a resonant tunneling diode and a field effect transistor are combined as one of the current variable negative resistance elements constituting two monostable-bistable logic gates connected in series. As shown in FIG. 5, the semiconductor logic circuit includes input terminals I ₁ ,
_{I 2, ··· I n-1} , a plurality of field effect with I _n transistors _{T 1, T 2, ··· T} n-1, T n is configured by parallel connection.

In such a configuration, a threshold logic operation can be performed on a weighted sum of a plurality of inputs including positive and negative. This weight changes in proportion to the gate width of the field effect transistors T ₁ , T ₂ ,..., T _n−1 , T _n . Therefore, multi-functional operation can be realized.

(Embodiment 2) FIG. 6 is a diagram for explaining another embodiment of the semiconductor device according to the present invention. In this embodiment, one of the logic gates constituting a cell is shown. In this figure, for simplicity, only one input (input from a neighboring cell) is shown. As the logic gate, as shown in FIG. 6, a monostable-bistable logic gate in which two current-variable negative resistance elements for varying current are connected in series and a first current-variable negative resistance element D ₁ , second current variable negative resistance element respectively in D ₂ switching circuit T _a, T _b is configured by connecting.

In such a configuration, the weighting can be changed from the fixed weighting of the first embodiment, and can be used for many purposes. In this example,
Unlike the first embodiment, the gate widths are all the same. Therefore, the weighting is based not on the difference in transconductance due to the gate width but on the difference in voltage applied to the logic gate. This voltage is applied from the outside, the switching circuit T _a, are respectively input to the input terminal I _1, I ₆ through T _b. Here, variable weighting is realized by turning on / off the switching circuits T _a and T _b by an input from another logic gate.

In such a configuration, unlike the first embodiment, the voltage _{VH corresponds} to the logical value "0" and the voltage _VL corresponds to the logical value "1". Here, the logical value is “0, 1” for simplicity, but the logical value “−1, 1” is obtained by converting the weight coefficient and the threshold parameter.
The operation can be performed in the same manner as in the case of. The sign of the weight coefficient can be realized as follows.

Here, when the weighting is positive, the voltage V _W− =
The voltage is set to 0 V, a voltage corresponding to the weight is added to the voltage V _{W +} , and the reverse is performed when the weight is negative. In this case, when the input is at the logical value “1”, the voltage V _W− or V _{W +} is input to the logical gate, and when the input is at the logical value “0”, the input voltage applied to the logical gate is 0V. Become. Further, since the voltage V _W− and the voltage V _{W +} are connected to the ground side and the drive voltage side, respectively, they have logically positive and negative meanings. Therefore, positive and negative weighting can be performed. It should be noted here that the weight of the semiconductor device is the same for all cells, so that the voltage supplied from outside need only be the number of neighboring cells, regardless of the number of cells. Therefore, seven external voltages may be used for the hexagonal lattice and nine external voltages may be used for the rectangular lattice.

The driving voltage V _bias for driving the semiconductor device is the same as in the first embodiment. Also, the external input u ^d and the threshold adjustment parameter i ^c, because no time-dependent, the gate of each cell, for example, the input terminal I
You can give it directly to ₄ .

Even in such a configuration, one cell can be composed of two monostable-bistable logic gates and transistors and resistors twice as many as the number of neighboring cells. A sufficiently small cell as follows can be realized, and high integration can be achieved.

In the above-described embodiment, the switching circuit is constituted by an inverter having an E / R configuration, and the voltage V
_{Although H corresponds} to the logical value “0” and the voltage _{VL corresponds} to the logical value “1”, the present invention is not limited to this, and other correspondences or switching circuits may be used. In short, it is only necessary that the external voltage according to the weight coefficient can be turned on / off by the output of another monostable-bistable logic gate. For example, p
If the FET of the type and the n-type FET are used, it is possible to make the voltage _VH and the voltage _VL correspond to the logical values "1, -1", respectively.

[0028]

As described above, according to the present invention,
A cell having an extremely small area can be realized by forming a cell by a logic gate using a monostable-bistable transition of a circuit in which elements exhibiting N-type negative resistance characteristics are connected in series, and a sufficiently large number of cells can be integrated. As a result, the present invention has an extremely excellent effect that a semiconductor device having a sufficient number of cells at a high speed can be easily obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a monostable-bistable logic element as a logic gate constituting a cell for explaining an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a flow of information in a semiconductor device according to the present invention.

FIG. 3 is a diagram showing a driving voltage for driving a logic gate according to the semiconductor device according to the present invention.

FIG. 4 is a sectional view showing a current variable negative resistance element constituting a logic gate according to the semiconductor device according to the present invention;

FIG. 5 is a current variable negative resistance circuit diagram showing another embodiment of the logic gate according to the semiconductor device according to the present invention.

FIG. 6 is a circuit diagram showing a logic gate forming a cell for explaining another embodiment of the semiconductor device according to the present invention.

FIG. 7 is a diagram showing a cell arrangement and a neighborhood (hexagonal lattice) of a discrete-time cellular neural network.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 negative resistance element 11 semi-insulating GaAs substrate 12 n ⁺ -GaAs buffer layer 13 n ⁻ -GaAs emitter layer 14 i-AlAs barrier layer 15 i-GaAs well layer 16 i-AlAs barrier layer 17 n −GaAs collector layer 18 n ⁺ −GaAs collector contact layer 19 collector electrode 20 emitter electrode 21 control electrode 22 p ⁺ layer 23 high resistance layer I input terminal I _{1 to} I ₉ input terminal O output terminal T _{1 to} T _n electric field effect transistor D ₁ to D ₂ first current variable negative resistance element T _a through T _b switching circuit R ₁ to R ₂ resistor

Claims (6)

(57) [Claims] An element or a circuit having an N-type negative resistance characteristic and having at least one input terminal for modulating its peak current is connected in series to form a series body. It has a plurality of logic gates that are driven up and down with a voltage value obtained by adding a peak voltage to both ends, and each logic gate has one of the outputs of an adjacent logic gate as an input,
A semiconductor device having a configuration for outputting to an adjacent logic gate. 2. The cell according to claim 1, wherein the logic gate comprises a first logic gate and a second logic gate to form one cell, and the input terminal of the first logic gate includes the cell and its neighboring cells. The output of the second logic gate of
The input terminal is connected to the input terminal of the second logic gate and the output of the first logic gate in the vicinity of the cell, and the first logic gate and the second logic gate are connected in a network. A semiconductor device, wherein a logic gate and a second logic gate are alternately driven. 3. The resonance according to claim 1, wherein the element having N-type negative resistance characteristics and having at least one input terminal for modulating its peak current uses resonance to a quasi-bound state. A semiconductor device using an element provided with a junction-type or Schottky-type gate in a tunnel diode. 4. A resonance circuit according to claim 1, wherein said circuit having N-type negative resistance characteristics and having at least one input terminal for modulating its peak current uses resonance to a quasi-bound state. A semiconductor device using a circuit in which a field effect transistor is connected in parallel with a tunnel diode. 5. The semiconductor device according to claim 1, wherein an input value is weighted by changing a gate width. 6. An element or circuit according to claim 1, wherein said element or circuit has an N-type negative resistance characteristic and has at least one input terminal for modulating its peak current. A semiconductor device, wherein a switching circuit is connected to a gate, and the switching circuit is switched by an output from a third logic gate.