JP3249938B2 - Method for manufacturing low power SRAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static random access memory (SRAM) capable of reducing standby power consumption of a memory.

[0002]

2. Description of the Related Art Reduced-shape integrated circuit designs have been used to increase the density of devices within an integrated circuit with the hope of increasing performance and lowering the cost of the integrated circuit. DRA
Modern integrated circuit memories, including M, SRAM, ROM, EEPROM, etc., are prominent examples of the application of this policy. As the density of memory cells in integrated circuit memories continues to increase, the cost per storage bit in such devices has correspondingly decreased. Increased density means smaller structures in the device,
And by reducing the spacing between the devices or the structures that make up the devices. Often these detailed design rules are layout,
Achieved by design and architectural changes, which can be achieved by reducing device size, or do they need to maintain performance when implementing such detailed design rules? Is one of For example, the low operating voltages used in many conventional integrated circuits are made possible by design improvements such as reducing gate oxide thickness and improving tolerance management in lithographic processes. On the other hand, finer design rules require lower operating voltages to limit the effects of heat carriers generated in smaller devices that operate at higher operating voltages, which are now commonplace .

Another operating parameter affected by changing the design rules used in the manufacture of integrated circuit memory devices is power consumption in static random access memory (SRAM). SRAM is S
It is often used for applications that require low power consumption when the RAM goes into a standby state. For example,
Portable computing devices require low power consumption to prolong battery life. Other computing applications, such as desktop computers, which have a low power consumption "sleep" state when the computer is not in operation for a long period of time, require low power consumption in some operating conditions . In such a computer, or at least for certain components of such a computer, such as a modem, as many computer operating states as practical in integrated circuit memory (as opposed to hard disk or mass storage memory) It is desirable that the computer be able to quickly resume normal operation when recovering from sleep. In order to maintain low power consumption, it is necessary to store S
It is important to use RAM. Other types of memory may consume too much power (DRAM) or may not be suitable for this purpose (EEPROM, flash). As the density of SRAMs increases by applying finer design rules, it becomes increasingly difficult to maintain an acceptable low level of power consumption. With finer design rules, the devices in SRAMs are becoming smaller and smaller, and the leakage levels of smaller devices tend to increase, which tends to increase the leakage of each cell. This problem is exacerbated in high-density SRAMs because the number of cells in the SRAM increases with advanced design rules, and large cell leakage is compounded by the large number of cells. Therefore,
Reducing the level of charge leakage in the SRAM cell
It is important to make increasingly dense SRAMs useful in low power consumption applications.

A typical SRAM design includes two or four MOS transistors coupled together in a latch configuration having two charge storage nodes for storing charge states corresponding to data stored in cells. . SRAM
The cell includes two pull-down transistors and two load devices, which may be polysilicon load resistors, but are more typically thin film transistors in modern SRAMs. Each of the charge storage nodes includes a contact between a corresponding pull-down transistor and a corresponding one of the load devices, and each of the charge storage nodes is coupled to a gate electrode of another pull-down transistor in a conventional latch configuration. By selectively coupling each charge storage node to a corresponding one of the complementary bit line pairs,
Data is read from a conventional SRAM cell in a non-destructive manner. Selective coupling is achieved by a pair of pass transistors each connected between one of the charge storage nodes and a corresponding one of the complementary bit lines. A word line signal is applied to the gate of the pass transistor to switch the pass transistor on during a data read operation. Charge flows through the ON pass transistor to and from the charge storage node, discharging one of the bit lines and charging the other of the bit lines. The voltage change on the bit line is sensed by the differential amplifier. In order to keep the latch of the SRAM cell stable during such a data read operation, at least one of the charge storage nodes in the SRAM charges and discharges faster than the flow of charge to and from the corresponding bit line. Must. This control typically involves, in part, the channel of a pass transistor connected to a particular charge storage node to at least one channel of an SRAM pull-down transistor having a drain connected to the particular charge storage node. It is maintained by making it narrower and / or longer.
This geometry allows more current to flow through the at least one SRAM pull-down transistor than through the corresponding pass transistor, and thus causes the charge storage node to charge more quickly than charging or discharging the corresponding bit line. Discharge will be performed.

[0005]

During a standby operation in which the SRAM is not performing a read or write operation, data may be eventually lost from the cells of the SRAM, or the data inside some of the cells may be lost. In a deterministic manner, charge tends to leak out of the charge storage node. To address this problem, SRAMs provide the potential at the charge storage node by providing the charge to the charge storage node, preferably at a very low average rate well matched to the level of charge leakage from the charge storage node. Designed to maintain. An SRAM cell has two load devices each connected between a charge storage node and a high reference potential. Charges flow from the high reference potential through the load device to the respective charge storage nodes, either steadily or intermittently, replacing charges that leak from the charge storage nodes. Regardless of whether the operation of the load device is an active operation or a passive operation, data is stored in the SRAM.
Power is used for as long as it is stored in
Reduction of power consumption by load devices has been
M has been studied as an attempt to reduce power consumption. For example, "Field Effect Thin-Film Transistor
US Patent No. 55148 to Nishimura et al., entitled "for an SRAM with Reduced Standby Current".
No. 80 describes a variety of different designs aimed at controlling leakage from thin film transistors used as load devices for SRAMs.

[0006] As the need to reduce the power consumption of SRAMs and increase the integration density continues, there is a further need to reduce the power consumption of individual SRAM cells and completed SRAM circuits.

[0007]

According to one aspect of the present invention, a static random access memory (SRA) is provided.
M) is created by providing a high reference potential contact, a low reference potential contact, and a charge storage node for the SRAM cell. The pull-down transistor connected between the charge storage node and the low reference potential contact has a source connected to the low reference potential and a drain connected to the charge storage node, and the drain of the pull-down transistor is Does not contain arsenic as a dopant. The pass transistor is connected between the charge storage node and the bit line. The load device is connected between the charge storage node and the high reference potential contact.

Another aspect of the present invention is a static random access memory (SR) having a plurality of SRAM cells having a pull-down transistor and a pass transistor.
AM). The pull-down transistor is provided with a gate electrode on the gate oxide layer, the source and drain regions are subjected to a first phosphorus implant that is automatically aligned with the gate electrode, and an insulating spacer is provided along the gate electrode; Is provided by providing a phosphorus LDD structure for the source and drain of the pull-down transistor. The source region is connected to a low reference potential and the drain region is connected to a charge storage node. In the pull-down transistor, a portion of the pull-down transistor that is a part of the source region of the pull-down transistor is exposed,
An implantation mask for covering arsenic ions in a source region of the pull-down transistor is provided so as to cover at least another portion of the pull-down transistor which becomes a part of a drain region of the pull-down transistor. A pass transistor is connected between the charge storage node and the bit line, and a load device is connected between the charge storage node and the high reference potential contact.

Another aspect of the present invention comprises a pull-down transistor and a pass transistor having a source and a drain, the drain being provided by a dopant consisting essentially of phosphorus. A static random access memory (SRAM) having a plurality of SRAM cells. The source of the pull-down transistor has a higher dopant concentration than the drain of the pull-down transistor. The pass transistor is connected between the charge storage node and the bit line, and the load device is connected between the charge storage node and the reference potential contact.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A particularly preferred embodiment of the present invention provides a method of fabricating an SRAM cell having reduced power consumption levels and exhibiting desirable levels of data stability and operating speed. An important aspect of the preferred embodiment of forming an SRAM according to the present invention is that the pull-down transistor of the SRAM is formed such that the drain of the pull-down transistor is formed without implanting arsenic or heavy N-type dopants. is there. It is known that ion implantation into a semiconductor substrate causes significant damage to the crystal lattice of the substrate. This is one of the reasons why the annealing step is always performed after the ion implantation step in the conventional integrated circuit manufacturing process. Conventionally, these annealing steps were thought to repair lattice damage in the implantation step and restore the implanted lattice to a high quality crystalline state. The present inventors have determined that the implantation of arsenic ions into the drain region of the pull-down transistor of the SRAM will damage the substrate in a manner that is not properly removed by annealing the substrate. This may reflect that the damage associated with arsenic implantation is so severe that it cannot be easily removed by annealing. Alternatively, the strain introduced into the lattice by accommodating large arsenic atoms may cause a different leakage component in the arsenic implanted drain of a conventional pull-down transistor than the leakage associated with the amorphous source or drain regions.

In any event, since the drains of the pull-down transistors are directly connected to the respective charge storage nodes of the SRAM cell, the level of charge leakage associated with arsenic ion implantation into the drains of the pull-down transistors is less than the charge storage node. This results in an undesirable level of leakage, which causes an undesirable increase in the power consumption of the SRAM cell. Unwanted charge leakage associated with using arsenic ion implantation to define the drain of the pull-down transistor of the SRAM cell is also achieved by implanting other large and heavy N-type dopants such as antimony (Sb). It will be clear if the drain of the pull-down transistor is specified. The present inventors have determined that when the drain of the pull-down transistor of the SRAM is defined only by phosphorus ion implantation, a reduction in the level of leakage from the charge storage node is observed. This aspect of the invention is particularly high in some embodiments by limiting the implantation dose to the pull-down transistor drain to less than about 1 × 10 ¹⁴ / cm ³ ions. Most preferably, the drain of the pull-down transistor defines a gate electrode, performs a first implant aligned with the edge of the gate electrode, forms an insulating sidewall spacer at the edge of the gate electrode, and aligns the second implant with the sidewall spacer. By performing the second implantation, it is possible to have a lightly doped drain (LDD) that is normally formed.

The use of a phosphorus-doped drain in a pull-down transistor of an SRAM cell reduces the typical driving capability of the pull-down transistor. Therefore, when the operating characteristics of the pull-down transistor are adjusted to reduce the leakage from the charge storage node, the pull-down transistor has sufficient driving capability as compared with the pass transistor to secure the stability of the SRAM cell. It is important to adapt the adjustments as you have. Such an adaptation can be made to the characteristics of the pass transistor and the characteristics of the pull-down transistor. Particularly preferred embodiments of the present invention provide improved drive capability to the source of the pull-down transistor to partially accommodate the reduced drive capability associated with a particularly preferred configuration of the drain of the pull-down transistor. This can be achieved by providing a relatively high level of arsenic doping in the source region of the pull-down transistor. In a particularly preferred embodiment of the present invention, the arsenic implant is a third implant into the source region of the pull-down transistor. Therefore, a particularly preferred embodiment of the present invention provides an asymmetric pull-down transistor for SRAM cells.

The source region of the pull-down transistor is
The peripheral circuits of the SRAM, in particular, have a high driving capability equivalent in many respects to the high driving capability of the ESD protection circuit of the SRAM. A particularly preferred embodiment of the present invention uses the same implantation step used to form at least some of the source / drain regions of the electrostatic discharge (ESD) protection circuit of the peripheral circuit, and simultaneously uses a pull-down transistor. To form a source. As a result, a source having a driving capability similar to the high driving capability of the source region and the drain region of the ESD protection transistor of the peripheral circuit is created for the pull-down transistor. These and other aspects of the invention will be described with reference to the drawings.

FIG. 1 shows two PMOS load transistors 10, 1 connected to form a cross-coupled inverter.
2 and two NMOS pull-down transistors 14, 1
SRAM cells (6 transistor cells to 6T)
Cell). Each of the PMOS load transistors 10, 12 has a corresponding NMOS pull-down transistor 14,
It has a gate connected to 16 gates. PMO
The drains of the S load transistors 10 and 12 correspond to the corresponding NM
It is connected to the OS transistors 14 and 16 to form an inverter having a conventional configuration. The source of the load transistor is connected to a high reference potential, typically V _CC, and the source of the pull-down transistor is connected to a low reference potential, which may be ground, typically V _SS . The PMOS transistor 10 and the NMOS transistor 14 constitute one inverter, and the gate of the PMOS transistor 10 and the gate of the NMOS transistor 14 are connected to the drains of the transistors 12 and 16 of the other inverter. Similarly, the gates of the PMOS transistor 12 and the NMOS transistor 16 constituting the other inverter are
It is connected to the drains of transistors 10 and 14. Therefore, the potential present at the drain (node N1) of the transistors 10, 14 of the first inverter is applied to the gates of the transistors 12, 16 of the second inverter, and the charge turns the second inverter ON or OFF. Work to maintain. Logically opposite potentials are present at the drains (nodes N2) of the transistors 12 and 16 of the second inverter and at the gates of the transistors 10 and 14 of the first inverter to turn off the first inverter with complementary OFF. Or O
It is maintained in the N state. Therefore, the latch of the illustrated SRAM has two stable states: a state in which a predefined potential is present on the charge storage node N1 and a low potential is present on the charge storage node N2, and a state in which a low potential is present on the charge storage node N1.
And a second state in which a predefined potential is present at the charge storage node N2. Binary data is recorded by toggling between the two states of the latch. Sufficient charge is stored in the charge storage node, and thus in the associated gate of the associated inverter,
One of the inverters must be explicitly kept "ON" and the other one "OFF", thereby preserving the state of the memory. The stability of the SRAM cell is such that the potential at the charge storage node fluctuates from a normal value,
The SRAM cell can be quantified by a margin that can still be maintained in its original state.

The state of an SRAM cell is conventionally read by selectively connecting two charge storage nodes N1, N2 of the cell to a pair of complementary bit lines (BL, BL bar). A pair of pass transistors 18, 20 is connected between the charge storage nodes N1, N2 and the corresponding bit lines BL, BL bar. Before the read operation, the bit lines BL and BL are equalized at a voltage intermediate between the high reference voltage and the low reference voltage, usually ・ · (V _CC −V _SS ), and the signal on the word line WL is passed. The transistor is turned on.
For example, N1 is charged to a predetermined potential of V _CC,
It is assumed that N2 is charged to a low potential V _SS . When the pass transistors 18 and 20 are turned on, charges are transferred from the node N1 through the pass transistor 18 to the bit line B.
Start to flow to L. The electric charge of the node N1 is stored in the bit line BL.
To the node N through the load transistor 10
It is supplemented by the charge flowing to 1. At the same time, charge is transferred from the bit line through the pass transistor 20 to the node N
2 and from node N2 through pull-down transistor 16. When the current flowing through pass transistor 18 becomes greater than that through transistor 10, charge begins to flow out of node N1, and when node N1 falls to a certain level, pull-down transistor 16 begins to turn off. When the current flowing through pass transistor 20 becomes greater than that flowing through pull-down transistor 16, charge begins to accumulate at charge storage node N2, and when node N2 is charged to a certain level, load transistor 10 begins to turn off.

In general, a six-transistor SRAM cell uses a thin film transistor (TFT) as the two load devices 10 and 12. Such two TFTs S
In the case of a RAM cell configuration, the source, drain and channel regions of the load transistors 10, 12 and the gate electrode are all formed of polysilicon adhered to an insulating material layer covering the lower layer of the SRAM circuit, The lower layer includes a pass transistor and a pull-down transistor formed on the surface of the substrate. The particular aspects of the TFT structure and the layout of the SRAM are not the focus of the discussion here and therefore will not be described further herein. Methods and structures for achieving a compact cell layout and achieving low levels of leakage from TFT-loaded devices are described in the Field Effect Thin-Film Transformer, which is hereby incorporated by reference.
US Patent No. 55 to Nishimura et al., entitled "istor for an SRAM with Reduced Standby Current"
14880. It should be noted that while the Nishimura patent uses arsenic implantation into the source and drain regions of the pull-down transistor, this portion of the Nishimura teaching is not incorporated herein as teaching.

One aspect of the present invention relates to using a common implant step to form a portion of the SRAM peripheral circuitry at the same time that the source region of the pull-down FET is formed. FIG. 2 shows one of the components of the peripheral circuit of the SRAM according to the present invention. Reference numeral 22 indicates a typical metal bonding pad used to connect each of the input / output terminals of the SRAM to other circuits.

For example, using the pad 22, the SRA
M can be given an address signal, SRAM can be given data, or can be read from it. One or more different levels of power supply voltage and reference voltage can also be provided to the SRAM from external contact pads such as those shown in FIG. The extension from the pad shown in the partially cutaway view is in contact with the source or drain of the transistor of the ESD protection circuit exemplified by the peripheral ESD circuit 24 of the SRAM. The illustrated ESD protection device 24 is a floating gate transistor having source / drain regions 26, 30 and a polysilicon floating gate 28. Each of the source / drain regions 26, 30 has an appropriate doping profile for the transistor to handle and drive relatively large currents. It is therefore desirable that these source / drain regions have particularly favorable characteristics for pull-down transistors of SRAM cells formed according to the present invention. It should be understood that there are other devices in the peripheral circuitry that also preferably have high current drive capability. For example, pad 2
It is desirable that an input / output (I / O) buffer that transfers signals between the input and output terminals 2 also has a high driving capability. Usually, however, the drive capability of such I / O circuits is not as good as the source characteristics of the desired pull-down transistor as for the source and drain regions of the ESD protection device. Therefore, it is most preferable that the source region of the pull-down transistor has the same current driving characteristics as the ESD protection transistor.
For simplicity of the following description, a single NMOS transistor of the ESD protection circuit 24, which differs from that shown in FIG. 2 but generally serves the same purpose, is shown in the figures from FIG. This discussion relates to peripheral devices as circuits that generally perform I / O functions including ESD protection for SRAMs. This is in contrast to the transistors and amplifiers found in the main memory cell array of the preferred SRAM device. Here, these transistors are called cell transistors.

FIG. 3 shows two cell transistors 14 and 18 corresponding to one of the pull-down transistors and one of the pass transistors of the 6T cell shown in FIG. FIG. 3 also shows an exemplary NMOS transistor 24 of the ESD protection circuit in the peripheral circuit. Of course, it will be appreciated that the various devices shown in FIG. 3 are not typically matched or configured in the manner shown in actual SRAM implementations. Rather, the configuration and alignment of FIG. 3 have been modified to simplify describing the teachings of the present invention. FIG. 3 shows various portions of the SRAM at an early stage of the process flow after the gate electrode has been defined and the first source / drain implant has been performed. SRAM is a silicon substrate 30
Field oxide device isolation region 32 formed thereon
Is formed on the substrate 30. Field oxide device isolation region 32 is a silicon local oxidation (LOCOS)
It may be formed by a technique or may be provided as a shallow trench isolation device by etching a trench in the substrate and then depositing an oxide to fill the trench by chemical vapor deposition. The definition of the shallow trench isolation structure is completed by a chemical mechanical polishing process. After the field isolation device 32 is provided on the substrate, a thermal oxide is grown on the substrate to a thickness of about 30-200 °. In some embodiments, growing a thicker gate oxide layer on the devices in the peripheral circuit may be necessary, especially if the peripheral circuit needs to accommodate higher operating voltages than those used for the memory cell array. It may be preferable.

[0020] Polysilicon is deposited, doped, and patterned on the surface of the device to define appropriate gate electrodes 42, 52 and 62 for each of the various types of transistors within the illustrated structure. Although the figures show gate electrodes of similar size and shape, the current drive and operating requirements of each of these transistors vary, and are adjusted to obtain the desired stability and performance characteristics of the SRAM. It is to be understood that this is often not the case in practice, as they usually have their respective properties. Still referring to FIG. 3, the gate electrodes 42, 52, 62 are then used as a mask for the self-aligned implantation of the lightly doped (N-) portions 40, 50, 60 of the source / drain regions of the illustrated device. Then, light blanket doping of phosphorus ions with low dose and low energy is performed on the substrate. This blanket implant of the lightly doped portion of the LDD source / drain region, according to a preferred embodiment of the present invention, requires about 3
The process is performed at an energy of 5 KeV to a dose of about 1 to 3 × 10 ¹³ / cm ² . The results of the process so far are shown schematically in FIG. The pull-down transistor 14 includes a source / drain region 40 formed on the surface of the substrate 30 and a gate electrode 42 formed on a gate oxide layer (not shown) on the surface of the substrate. Pass transistor 18 includes a source / drain region 50 formed on the surface of the substrate and a gate electrode 52 formed on a gate oxide layer. ES
The D protection circuit transistor 24 has a source / drain region 60
And a gate electrode 62. The gate electrodes of the pull-down transistor, pass transistor and ESD protection circuit transistor are formed at least partially of doped polysilicon. When the gate electrode is formed as a multi-layer conductor, at least the lowermost portion of the gate electrode is formed of a doped polysilicon layer. The bottom layer of doped polysilicon in the gates of the electrodes 42, 52, 62 of the pull-down and pass transistors may be formed of a single layer of polysilicon, although in other configurations of SRAM cells, tungsten silicide or Pull down transistors, pass transistors and ES with different layers of conductors containing titanium silicide
It may be incorporated in the gate electrode of the D protection circuit transistor.

FIG. 4 shows the device after forming insulating spacers on both sides of the gate electrode as part of the process of forming a lightly doped drain structure in the source / drain regions of the pass transistor, pull-down transistor and peripheral transistor. . The insulating spacer structure may be formed of silicon oxide, but in the case of fine design rules, the spacer structure is preferably silicon nitride. In the illustrated embodiment, the spacer structure is CVD
A layer of oxide is deposited to a thickness of between about 1500-2500 ° and the oxide layer is etched back to expose source / drain regions and to provide pull-down, pass and peripheral transistors 14, 18 and 24, respectively. It is formed by forming oxide spacer structures 44, 54 and 64 along the sidewalls of gate electrodes 42, 52 and 62. For an exemplary oxide layer, the etch-back operation is performed using reactive ion etching and fluorine etch chemistry. The thickness of the deposited layer largely determines the thickness of the sidewall spacer structure formed along the gate electrode.

After insulating spacers 44, 54 and 64 have been formed along the gate electrode, a second blanket implant of phosphorus ions is performed on the device to form a more heavily doped portion of the source / drain regions. I do. According to the present invention, the dose of phosphorus ions is about 1 × 10 ¹³ to 1 × 10 ¹⁴ / c at about 40 KeV by the second phosphorus implantation.
m ² . As a result of this implantation, a more heavily doped N-type region is formed in self-alignment with the spacer structure, and the source / drain regions 46, 56 of the pull-down, pass and ESD protection transistors 14, 18 and 24, respectively. And 66 are given LDD structures.

In addition to the devices shown, there are usually additional devices in the peripheral circuits of the SRAM, including various additional I / O circuits. These peripheral circuits typically include inverters and other types of buffer circuits with relatively high current drive capabilities. Such I /
The O circuit can be, for example, a coupled PMOS and NMO
It may include a CMOS inverter composed of S transistors, or may include an NMOS transistor alone or in combination with a PMOS transistor. Typically, the NMOS transistors of the I / O circuit are subjected to the first two ion implantations and then further implanted into these I / O or other peripheral circuits. Each of the pull-down, path, and ESD protection circuits shown in FIG. 4 is provided with a mask, and is implanted into the source / drain region of the NMOS transistor in the peripheral circuit. This implantation may be by arsenic ions implanted at an energy of about 55 KeV to a dose of about 2 × 10 ¹⁵ cm ² . Strip this mask and provide a new mask that will be used to complete the definition of the ESD circuit.

As shown in FIG. 5, the ESD mask 80
It is provided on a RAM. As shown schematically, the ESD mask covers the entire pass transistor and also covers the drain region of the pull-down transistor so that the drain of the pull-down transistor is not subjected to ESD injection. Since peripheral circuits other than the ESD protection circuit are covered with the ESD mask, they are not subjected to ESD injection. Next, the ESD injection is performed by using the ESD protection circuit transistor 2
4 for the source / drain region 67 and the source 48 of the pull-down transistor 14. No injection is performed on the drain 47 of the pull-down transistor.
The first part of the ESD implant provides a dose of about 1 × 10 ¹⁵ / cm ² arsenic ions at an energy of about 55 KeV. Finally, a pocket or halo implant of boron ions is performed on the source / drain region of the ESD protection circuit transistor to form a pocket doped region 68 and is performed on the source region of the pull-down transistor 14 to provide a pull-down transistor. A pocket doped region 49 adjacent to the channel is formed. Pocket injection is about 2
60 Ke to provide a dose of 5 × 10 ¹³ / cm ²
At an energy of V, it consists of boron ions implanted preferably at a tilt angle of about 30 ° with the substrate rotated. The pocket doped region serves to limit the punch-through effect. Next, the ESD mask 80 is peeled off.
After all implants have been performed, the various implants are annealed and an electric furnace anneal at a temperature of about 800 ° C. for about 20-30 minutes,
Or activated by either a rapid thermal anneal process at about 1000-1100 ° C. for about 10-60 seconds.

FIG. 6 is a partially different view of the SRAM memory cell array in the process step shown in FIG. In a practical embodiment, the pull-down transistors 14, 16 of the SRAM cell are formed during a common source injection. Therefore, the ESD mask 80 covers the drains 47 of the pull-down transistors 14 and 16 and exposes the common source region, and a relatively deep arsenic-implanted source having a P-type pocket doped region 49 around the source region 48. It is provided to provide an area 48.

Further processing is performed to provide an insulating layer on the device of FIG. 5 and a load device on the insulating layer. FIG.
The other process steps required to complete the SRAMs outlined above are conventional and are properly described above and in the Nishimura patent incorporated herein by reference. Therefore, other processing steps are not described herein.

Although the present invention has been described with particular attention to certain preferred embodiments of the invention, the invention is not limited to the specific embodiments described above. The scope of the invention is to be determined by the following claims.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a six transistor (6T) SRAM cell according to a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram of an electrostatic discharge (ESD) protection circuit that can be provided in a peripheral circuit of an SRAM formed according to a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating various portions of an SRAM at an early stage of fabrication according to a preferred embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating various portions of the SRAM at a stage subsequent to the stage shown in FIG. 3;

5 is a schematic diagram showing various parts of the SRAM at a stage following the stage shown in FIG. 4;

FIG. 6 illustrates an implantation performed on a common source region of two pull-down transistors of an SRAM cell formed according to a preferred embodiment of the present invention.

[Explanation of symbols]

 10, 12 PMOS load transistor 14, 16 NMOS pull-down transistor 18, 20 pass transistor

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-78256 (JP, A) JP-A-4-262574 (JP, A) JP-A-7-161841 (JP, A) JP-A-2- 58870 (JP, A) JP-A-6-163831 (JP, A) JP-A-6-140631 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8244 H01L 27 / 11 JICST file (JOIS)

Claims (19)

(57) [Claims] A plurality of static random access methods;
Memory (SRAM) cells and addressing SRAM cells
SRAM with an array of bit lines for
A high reference potential contact, a low reference potential contact for the SRAM cell.
Providing a point and a charge storage node; connecting between the charge storage node and the low reference potential contact;
A source connected to the sub-potential and a charge storage node
And the drainSource region as dopant
Containing phosphorus, arsenic, and boron,
Region does not have arsenic and boron as dopantspull
Providing a down transistor;Includes transistors with ESD source / drain regions
Only, the ESD source / drain regions
An ESD protection circuit containing arsenic, arsenic and boron
Steps and  Past connected between the charge storage node and the bit line
Providing a transistor; and a load connected between the charge storage node and the high reference potential contact.
Providing a device.And
Source region and EDS source of pull-down transistor
/ Arsenic ions and boron ions in the rain region Mask the pull-down transistor with an implantation mask
EDS source / drain area and pull-down
Pull-down transformer that is part of the transistor source area
Exposing the portion of the transistor, drain of the pull-down transistor
At least a pull-down transistor that is part of the
And also covering other parts, Arsenic ions in EDS source / drain region and pull
Injecting into the source region of the down transistor
When, Boron ions are added to the EDS source / drain region and
Pocket injection into the source region of the pull-down transistor
A statistic characterized by being injected by a step
How to create a random access memory. 2. The method of claim 1, wherein the source of the pull-down transistor has a pull-down source doping distribution and the ESD source / drain region has a pull-down source doping distribution. 3. A pull-down transistor comprising: a gate electrode provided on a gate oxide layer; a first phosphorus implant that is automatically aligned with the gate electrode; an insulating spacer provided along the gate electrode; The method of claim 1 formed by performing a second phosphorus implant, thereby providing a phosphorus LDD structure for the source and drain of the pull-down transistor. 4. An implantation mask having an opening in a peripheral circuit portion of the SRAM, and the step of implanting arsenic ions comprises
4. The method according to claim 3 , wherein arsenic ions are also applied to source / drain regions of peripheral transistors provided in a peripheral circuit of the RAM. 5. The peripheral transistor is an ESD for an SRAM.
5. The method according to claim 4 , which is part of a protection circuit. 6. A drain in a drain of a pull-down transistor.
Panto is essentially the method of claim 3 which is a phosphorus resulting in a dose of less than about 1 × ¹⁰ 14 / cm ^2. 7. A method of making an SRAM having a plurality of static random access memory (SRAM) cells having a pull-down transistor and a pass transistor, comprising: providing a gate electrode on a gate oxide layer; Performing a matching first phosphorus implant, providing an insulating spacer along the gate electrode, and performing a second phosphorous implant that automatically matches the insulating spacer, thereby providing a phosphorus LDD structure for the source and drain of the pull-down transistor. Providing a pull-down transistor by connecting the source region to a low reference potential and connecting the drain region to the charge storage node; and masking the pull-down transistor with an implantation mask to become a part of the source region of the pull-down transistor. Part of Exposing arsenic ions to the source region of the pull-down transistor, covering at least another portion of the pull-down transistor that is to be a part of the drain region of the pull-down transistor; and a path connected between the charge storage node and the bit line. A method comprising: providing a transistor; and providing a load device connected between a charge storage node and a high reference potential contact. 8. The implantation mask has an opening in a peripheral circuit portion of the SRAM, and the step of implanting arsenic ions comprises the step of:
8. The method according to claim 7 , wherein arsenic ions are also supplied to source / drain regions of peripheral transistors provided in a peripheral circuit of the RAM. 9. The SRAM according to claim 6, wherein the peripheral transistor is an ESD for an SRAM.
9. The method of claim 8 , wherein the method is part of a protection circuit. 10. The method of claim 9 , wherein the dopant in the drain of the pull-down transistor consists essentially of phosphorus providing a dose of less than about 1 × 10 ¹⁴ / cm ² . 11. A pull-down transistor, a method of creating a SRAM having a plurality of static random access memory (SRAM) cell and a pass transistor has a source and a drain, dopant in the drain
The source is essentially phosphorus and the dopant in the source
Providing a pull-down transistor consisting essentially of phosphorus, arsenic, and boron and having a higher dopant concentration than drain; and providing a pass transistor connected between the charge storage node and the bit line. Providing a load device connected to the charge storage node and the reference potential contact; and a source wherein the dopant consists essentially of phosphorus, arsenic, and boron.
EDS protection transistor with transistor having drain and drain
Providing a protection circuit. 12. The drain is doped by one or more implantations of phosphorus ions, each of which is about 1 × 10
The method of claim 11 having a dose of less than ¹⁴ / cm ^2. 13. A pull-down transistor comprising: a gate electrode on a gate oxide layer; a first phosphorus implant that automatically aligns with the gate electrode; an insulating spacer along the gate electrode; 12. The method of claim 11 , defined by performing two phosphorus implants, thereby providing a phosphorus LDD structure for the source and drain of the pull-down transistor. 14. The pull-down transistor is masked with an implantation mask to expose a portion of the pull-down transistor that is to be a source region of the pull-down transistor and to cover at least another portion of the pull-down transistor that is to be a drain region of the pull-down transistor. 12. The method of claim 11 , further comprising implanting arsenic ions into the source region of the pull-down transistor. 15. The semiconductor device according to claim 15, wherein the implantation mask has an opening in a peripheral circuit portion of the SRAM, and the step of implanting arsenic ions also supplies arsenic ions to a source / drain region of a peripheral transistor provided in the peripheral circuit of the SRAM. Item 15. The method according to Item 14 . 16. The peripheral transistor is an ES for SRAM.
The method according to claim 15 , which is part of a D protection circuit. 17. The method according to claim 17, wherein the drain of the pull-down transistor
Dopant Essentially, the method according to claim 11 which is a phosphorus resulting in a dose of less than about 1 × ¹⁰ 14 / cm ^2. 18. The method according to claim 18, wherein the drain of the pull-down transistor
Dopant Essentially, the method according to claim 16 which is a phosphorus resulting in a dose of less than about 1 × ¹⁰ 14 / cm ^2. 19. The method of claim 14 , wherein the arsenic ions are provided at a dose that is at least ten times greater than the dose of providing phosphorus ions to the drain of the pull-down transistor.