JP3249034B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a self-aligned ultrahigh-speed bipolar transistor and a CMOS transistor are formed on the same semiconductor substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the remarkable progress of mobile communication devices such as mobile phones, it has become necessary to integrate a high-frequency circuit and a highly integrated logic circuit in a semiconductor integrated circuit. Therefore, a self-aligned ultra-high-speed bipolar transistor suitable for high-speed ECL circuits and analog circuits,
There is a strong demand for a technology for integrating a highly integrated and low power consumption CMOS logic circuit on the same semiconductor substrate.

Hereinafter, a two-layer polycrystalline silicon self-aligned transistor and a CMOS transistor in which a base lead electrode and an emitter lead portion are formed in a self-aligned manner, which are widely used in the self-alignment technique, are formed on the same semiconductor substrate. The prior art that is also shown in Japanese Patent Application Laid-Open No. 63-281456 will be described with reference to the drawings.

FIG. 8 is a sectional view of a conventional semiconductor integrated circuit device. 8, reference numeral 54 denotes a P-type semiconductor substrate made of silicon; 51, an NPN bipolar transistor on the P-type semiconductor substrate 54; 52, a P-channel MOS transistor on the P-type semiconductor substrate 54;
The upper N-channel MOS transistor 57 is formed by ion implantation and heat treatment into an element isolation region in an N-type semiconductor epitaxial layer deposited on the entire surface of the P-type semiconductor substrate 54.
A first P-type well layer 59 formed so as to reach the type semiconductor substrate 54 is a LOCOS film for isolating elements.
In the following, the NPN bipolar transistor 51,
P-channel MOS transistor 52 and N-channel MO
A description will be given for each element of the S transistor 53.

First, in the NPN bipolar transistor 51 of FIG. 8, 55A is an N-type buried collector layer formed on a P-type semiconductor substrate 54 by ion implantation and heat treatment, and 56A is N deposited on the entire surface of the P-type semiconductor substrate 54.
Collector layer formed by ion implantation and heat treatment in the epitaxial layer of the type semiconductor, 61 is an emitter / base forming region formed in a self-aligned manner, and 62A is formed of polycrystalline silicon doped with a P-type impurity. NP
Base extraction electrode of N bipolar transistor 51, 6
3A is an insulating film on the upper surface of the base lead electrode formed of a TEOS film or the like, and 64A, 64B, 64C and 64D are T
Insulating side walls of the base extraction electrode formed of an EOS film or the like, and 65 are insulating side walls 64B and 64 of the base extraction electrode.
An emitter extraction opening formed by C in a self-aligned manner; 66, an emitter extraction electrode made of polycrystalline silicon into which an N-type impurity is introduced; 67, a collector extraction electrode made of polycrystalline silicon into which an N-type impurity is introduced; Reference numeral 68 denotes an external base layer into which impurities are introduced by heat treatment through the base extraction electrode electrode 62A, 69 denotes an active base layer formed by heat treatment, and 70 denotes heat treatment through the emitter extraction electrode 66 by insulating sidewalls 64B and 64C of the base extraction electrode. Self-aligned emitter layer 71
Is a collector contact layer formed by heat treatment.

Next, in the P-channel MOS transistor 52 shown in FIG. 8, 55B is an N-type buried well layer formed on the P-type semiconductor substrate 54 by an ion implantation method, and 56B is formed by ion implantation and heat treatment in the epitaxial layer. 60A is a first gate insulating film formed by oxidizing the surface of the epitaxial layer;
62C is a first gate electrode made of polycrystalline silicon into which an N-type impurity is introduced, 63C is an insulating film on the upper surface of the first gate electrode made of a TEOS film or the like, and 64E is a first gate electrode made of a TEOS film or the like. An insulating side wall, 72A is a first LDD layer formed using the side surface of the first gate electrode 62C as a side wall, and 73A is self-aligned by ion implantation using the insulating side wall 64E of the first gate electrode as a side wall. This is the first source / drain layer formed.

Next, in the N-channel MOS transistor 53 of FIG. 8, 58 is a second P-type well layer formed so as to reach the P-type semiconductor substrate 54 by ion implantation and heat treatment in the epitaxial layer, and 60B is A second gate insulating film formed by oxidizing the surface of the epitaxial layer; 62D, a second gate electrode made of polycrystalline silicon doped with an N-type impurity; 63D, a second gate made of a TEOS film or the like Insulating film on top of electrode, 64G is TE
An insulating side wall of a second gate electrode made of an OS film or the like, 72C
Is a second LDD layer formed using the side surface of the second gate electrode 62D as a side wall, and 73C is a second LDD layer formed in a self-aligned manner by ion implantation using the insulating side wall 64G of the second gate electrode as a side wall. Source 2
It is a drain layer.

With the above configuration, in each MOS transistor, for example, P-channel MOS transistor 52,
LD that hardly generates hot carriers that degrade operating characteristics
In order to realize the D structure, the side surface of the first gate electrode 62C and the insulating side wall 64E of the first gate electrode are used as side walls.

In the NPN bipolar transistor 51, the dimensions of the emitter layer 70 are reduced by forming the insulating side walls 64B and 64C of the base extraction electrode in a self-alignment manner in the same process as the insulating side wall 64E of the first gate electrode. As a result, the junction capacitance is reduced, the distance between the base extraction electrode 62A and the emitter layer 70 is shortened, the base resistance is reduced, and the high frequency characteristics are greatly improved.

[0010]

The distance between the external base layer 68 and the emitter layer 70 (hereinafter abbreviated as "first parameter") for the base resistance value and the carrier transit time in the base which influence the operation characteristics of the bipolar transistor 51. Is an important factor. For example, for the hot carrier resistance and the saturated drain current value which affect the operation characteristics of the MOS transistor 52, the distance between the first gate electrode 62C and the first source / drain layer 73A is large. (Hereinafter referred to as "
Parameter) is an important factor.

However, in the conventional semiconductor integrated circuit device, the first side wall 64B of the base extraction electrode and the first side wall 64E of the first gate electrode are formed in a single process by the first process. A parameter and a second parameter are determined. Therefore, the insulating side wall 64B
It is extremely difficult to optimize all the operating characteristics by a single process with a film thickness of 64E and 64E.
In order to ensure the performance of the OS transistor 52, the insulating side wall 64E of the first gate electrode, which determines the LDD structure, tends to be optimized with priority over the insulating side wall 64B of the base lead-out electrode. There was a problem that it was difficult to secure them.

The NPN bipolar transistor 51
, The insulating side walls 64B and 64C of the base extraction electrode formed of a thick insulating film around the emitter-base junction.
Is formed, when the insulating side wall having a large heat capacity cools, the contracting stress is applied to the periphery of the emitter-base junction, so that the leakage characteristics between the emitter and the base are deteriorated, Since the width becomes narrower due to the miniaturization, the aspect ratio (the ratio between the height and the diameter of the emitter lead-out opening) of the emitter lead-out opening 65 becomes large, so that the emitter resistance due to the emitter lead-out electrode 66 increases. Had.

The present invention solves the above-mentioned conventional problems by optimizing the operating characteristics of the bipolar transistor and the MOS transistor for each element, improving the leakage characteristics between the emitter and the base, and reducing the emitter resistance. Accordingly, the present invention provides a semiconductor integrated circuit device whose performance is further improved.

[0014]

In order to achieve the above object, the present invention is to form a first side wall on a side surface of a base extraction electrode and a second side wall on a side surface of a gate electrode by different steps. The first side wall is constituted by an insulating film and a conductor film, and the second side wall is constituted by an insulating film.

[0015] Specifically, a solution taken by the invention of claim 1 is connected to an external base layer surrounding the base layer,
A base electrode having a first sidewall on a side surface and having a first insulating film on the upper surface, the emitter layer was formed in a self-aligned manner by the said base electrode and said first side wall and an emitter lead-out electrode bipolar transistor having, as well as a second gate electrode having sidewalls, a source-drain layers formed in a self-aligned manner by the the said gate electrode said second sidewall on the side surface and having a second insulating film on the upper surface The first side wall is formed of a third insulating film on the base extraction electrode side and a conductor film on the side opposite to the base extraction electrode, assuming that the semiconductor integrated circuit device includes MOS transistors having the same structure mounted on the same semiconductor substrate. And the second side wall has a gate formed by the same process as the third insulating film.
The fourth insulating film and the counter-gate electrode side formed on the electrode side
This is constituted by a fifth insulating film .

According to the structure of the first aspect, since the first side wall of the bipolar transistor is formed of the thin insulating film on the base extraction electrode side and the conductor film on the side opposite to the base extraction electrode, it is formed of a thick insulating film. Since the heat capacity of the first side wall is lower than in the case where
Since the conductor film on the side wall of the electrode and the emitter extraction electrode are integrated, the substantial diameter of the emitter extraction opening increases, and the aspect ratio (the ratio between the height and the diameter of the emitter extraction opening) decreases. Further, the first side wall formed on the side surface of the base extraction electrode of the bipolar transistor and the second side wall formed on the side surface of the gate electrode of the MOS transistor can be formed by different processes. The distance between the external base layer and the emitter layer of the bipolar transistor and the distance between the gate electrode and the source / drain layer of the MOS transistor can be adjusted independently.

[0017]

Further, since the second sidewall of the gate electrode of the MOS transistor is constituted by the fourth insulating film and the fifth insulating film, the interval and the MOS transistor of the external base layer and the emitter layer of the bipolar transistor The degree of freedom in which the distance between the gate electrode and the source / drain layer can be adjusted independently increases, and the thickness of the third insulating film formed by the same process as that of the fourth insulating film becomes thinner.

According to a second aspect of the present invention, in the first aspect ,
The fifth insulating film adds a structure of a silicon oxide film.

According to a third aspect of the present invention, in the first aspect,
The second side wall has a configuration in which the base extraction electrode is also formed on a side surface extending on an element isolation film surrounding the external base.

According to a fourth aspect of the present invention, in the configuration of the first aspect,
The third insulating film adds a configuration made up of an oxide film and a silicon nitride film of the electrode formed in order from the side in contact with the base extraction electrode.

According to a fifth aspect of the present invention, in the first aspect,
The conductor film adds a structure made of polycrystalline silicon.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, wherein an element isolation film for insulating a bipolar transistor and a MOS transistor is formed on a semiconductor substrate, and a gate insulating film is formed in an element region excluding the element isolation film. After a first step of forming a film and removing the gate insulating film in a region where a bipolar transistor is to be formed by etching, a first conductive film and a first insulating film are sequentially deposited on the entire surface of the semiconductor substrate. Performing a second step and etching the first insulating film and the first conductor film;
Wherein an insulating film on the base electrode and the base electrode of the bipolar transistor, a third step of forming an insulating film on the gate electrode and the gate electrode of the MOS transistor, the side surface of the base electrode, said After forming a second insulating film on the upper surface of the emitter formation region surrounded by the base extraction electrode and the side surface of the gate electrode, a third insulating film and a second conductor are formed on the entire surface of the semiconductor substrate. A fourth step of sequentially depositing a film, and etching the second conductive film to form a second insulating film, a third insulating film and a third insulating film on the side surface of the base extraction electrode and the side surface of the gate electrode. A fifth step of forming a first side wall composed of a second conductive film, and forming the third insulating film and the second insulating film on the emitter forming region and the source / drain forming region by the first step. Side of A sixth step of forming an opening of the emitter extraction electrode in a self-aligning manner by removing the third conductor film by etching using the mask as a mask; and depositing a third conductor film on the entire surface of the semiconductor substrate. By selectively etching the conductive film of the above, an emitter extraction electrode is formed on the opening of the emitter extraction electrode, and the base extraction electrode other than the side surface of the base extraction electrode covered with the emitter extraction electrode is formed. A seventh step of removing the second conductive film in the first side wall on the side surface and the side surface of the gate electrode by etching, and depositing a fourth insulating film on the entire surface of the semiconductor substrate. Etching is performed on the insulating film No. 4 to form a second side wall composed of the second insulating film, the third insulating film and the fourth insulating film on the side surface of the gate electrode And a ninth step of forming a source / drain formation region in a self-aligned manner by the second side wall and the gate electrode.

According to the sixth aspect of the present invention, the first side wall of the bipolar transistor is formed of a thin insulating film on the base extraction electrode side and a conductor film on the side opposite to the base extraction electrode, and thus is formed using a thick insulating film. Since the heat capacity of the first side wall is lower than that of the first side wall, the contracting stress applied to the periphery of the emitter-base junction is reduced. Further, since the conductor film on the side opposite to the base extraction electrode on the first side wall and the emitter extraction electrode are integrated with each other, the substantial diameter of the emitter extraction opening is increased, so that the aspect ratio (the height of the emitter extraction opening and the height of the emitter extraction opening is reduced). Ratio to the diameter). Further, since the first side wall formed on the side surface of the base extraction electrode of the bipolar transistor and the second side wall formed on the side surface of the gate electrode of the MOS transistor are formed by different processes, the external base layer and the emitter layer of the bipolar transistor are formed. And the distance between the gate electrode of the MOS transistor and the source / drain layer can be determined independently.

[0025]

Further, the second side wall of the side surface of the gate electrode, the second insulating film, for constituting the third insulating film and the fourth insulating film, the distance between the external base layer and the emitter layer of the bipolar transistor In addition, the degree of freedom for independently adjusting the distance between the gate electrode of the MOS transistor and the source / drain layer increases, and the third insulating film can be formed thin.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a sectional structure of a semiconductor integrated circuit device according to a first embodiment of the present invention. In FIG. 1, 10 is a P-type semiconductor substrate made of silicon, 1 is an NPN bipolar transistor on the P-type semiconductor substrate 10, 2
Is a P-channel MOS transistor on the P-type semiconductor substrate 10, 3 is an N-channel MOS transistor on the P-type semiconductor substrate 10, 14A is an element isolation in an epitaxial layer of an N-type semiconductor deposited on the entire surface of the P-type semiconductor substrate 10. An element isolation layer 14B formed to reach the P-type semiconductor substrate 10 by ion implantation and heat treatment in the region. The PB is formed by ion implantation and heat treatment in the N-type semiconductor epitaxial layer deposited on the entire surface of the P-type semiconductor substrate 10. Type semiconductor substrate 10
P-type well layer formed to reach
B, 15C, 15D and 15E are LOCs for separating the elements.
This is an OS film. The structure of each of the NPN bipolar transistor 1, the P-channel MOS transistor 2, and the N-channel MOS transistor 3 will be described below.

First, in the NPN bipolar transistor 1 shown in FIG. 1, 12A is an N-type buried collector layer formed on a P-type semiconductor substrate 10 by ion implantation and heat treatment, and 13A is deposited on the entire surface of the P-type semiconductor substrate 10. N
Collector layer formed by ion implantation and heat treatment in the epitaxial layer of the type semiconductor, 17 is an emitter / base forming region formed in a self-aligned manner, 18A is an NPN made of polycrystalline silicon doped with a P-type impurity. Base extraction electrode of bipolar transistor 1, 19A is TE
An insulating film on the upper surface of the base extraction electrode made of an OS film or the like;
A is an oxide film on the side of the base extraction electrode formed by oxidizing the base extraction electrode 18A by heat treatment, 21A is a silicon nitride film on the side of the base extraction electrode formed by low pressure CVD and formed by etching, 22A and 2A.
2B is a polycrystalline silicon film on the side surface of the base extraction electrode formed by etching under reduced pressure CVD and formed by etching.
Reference numeral 3 denotes an emitter layer formed in a self-aligned manner by the polycrystalline silicon films 22A and 22B on the side surfaces of the base extraction electrode by heat treatment through an emitter extraction electrode 25; 24, a collector contact layer formed by heat treatment; and 25, an N-type impurity. Emitter extraction electrode made of polycrystalline silicon introduced, 26 is a collector extraction electrode made of polycrystalline silicon doped with N-type impurities, 32A is an insulating side wall of a base extraction electrode made of a TEOS film or the like, and 33 is a base extraction electrode. An emitter lead-out opening formed in a self-aligned manner by the insulating side walls 22A and 22B, 34 is an external base layer into which impurities are introduced by heat treatment through the base lead-out electrode 18A, and 35 is an active base layer formed by heat treatment.

Next, in the P-channel MOS transistor 2 shown in FIG. 1, 12B is an N-type buried well layer formed on the P-type semiconductor substrate 10 by ion implantation, and 13B.
Is an N-type well layer formed by ion implantation and heat treatment in the epitaxial layer; 16C is a first gate insulating film formed by oxidizing the surface of the epitaxial layer;
18C is a first gate electrode made of polycrystalline silicon into which N-type impurities are introduced, 19C is an insulating film on the upper surface of the first gate electrode made of a TEOS film or the like, and 20C is a film which oxidizes the first gate electrode 18C by heat treatment. An oxide film on the side surface of the first gate electrode formed by sputtering, 21C is a silicon nitride film on the side surface of the first gate electrode formed by low-pressure CVD and etched, and 27A is a silicon nitride film on the side surface of the first gate electrode. A first LDD layer formed with the film 21C as a side wall, and a first layer 29A formed of a TEOS film or the like.
Insulating sidewalls 30A of the first gate electrode are first source / drain layers formed in a self-aligned manner by ion implantation using the insulating sidewall 29A of the first gate electrode as a sidewall.

Next, in the N-channel MOS transistor 3 shown in FIG. 1, reference numeral 14B denotes a second P-type well layer formed to reach the P-type semiconductor substrate 10 by ion implantation and heat treatment in the epitaxial layer, 16D. Is a second gate insulating film formed by oxidizing the surface of the epitaxial layer, 18D is a second gate electrode made of polycrystalline silicon doped with an N-type impurity, and 19D is a second gate electrode made of a TEOS film or the like. An insulating film on the upper surface of the gate electrode, 20D is an oxide film on the side surface of the second gate electrode formed by oxidizing the second gate electrode 18D by heat treatment, and 21D is a reduced pressure CV.
A silicon nitride film on the side surface of the second gate electrode deposited by the method D and formed by etching, 28A is a second LDD layer formed using the silicon nitride film 21D on the side surface of the second gate electrode as a sidewall, and 29B is TEOS. An insulating side wall 31A of the second gate electrode made of a film or the like is a second source / drain layer formed in a self-aligned manner by ion implantation using the insulating side wall 29B of the second gate electrode as a side wall.

The P-type semiconductor substrate 10 is made of silicon in which boron has a resistivity of about 10 Ω · cm and a plane orientation of (100), and has an NPN bipolar transistor 1, a P-channel MOS transistor 2 and an N-type A channel MOS transistor 3 is integrated.

The N-type buried collector layer 12A of the NPN bipolar transistor 1 has an impurity of arsenic or antimony introduced at a sheet resistance of 50 to 150 Ω / □, and has a thickness of 1 to 2 μm.
m is formed at a junction depth of m. The N-type buried well layer 12B of the P-channel MOS transistor 2 is formed at a junction depth of 1 to 2 μm with arsenic or antimony impurities introduced at a sheet resistance of 50 to 150 Ω / □. By forming the N-type buried well layer 12B, a P-channel MOS
The first source / drain layer 30A of the transistor 2 and P
The electric breakdown voltage with the mold semiconductor substrate 10 can be improved.

Arsenic or phosphorus impurities having a thickness of 0.8 to 1.5 μm are introduced into the entire upper surface of the P-type semiconductor substrate 10, and an N-type epitaxial layer having a specific resistance of 1 to 5 Ω · cm is deposited. . The thickness of the epitaxial layer is N-type collector layer 1.
This is a region shown in the vertical direction of the 3A and N-type well layers 13B. The N-type collector layer 13A is formed in the epitaxial layer by introducing a phosphorus impurity having a surface concentration of about 5 × 10 ¹⁶ cm ⁻³ so as to reach the N-type buried collector layer 12A of the NPN bipolar transistor 1. Is 0.8 to 1.5 μm. The N-type well layer 13B is made of P
N-type buried well layer 1 of channel MOS transistor 2
A phosphorus impurity having a surface concentration of about 5 × 10 ¹⁶ cm ⁻³ is introduced into the epitaxial layer to reach 2B,
The depth of the diffusion layer is 0.8 to 1.5 μm.

The thickness of the epitaxial layer and the impurity concentration of the N-type buried collector layer 12A and the N-type well layer 13B are as follows:
It is an important parameter that determines device performance such as device breakdown voltage, carrier transit time and base junction capacitance of the NPN bipolar transistor 1, and device breakdown voltage and source-drain junction capacitance of the P-channel MOS transistor 2. Optimized.

The element isolation layer 14A is formed in the epitaxial layer by introducing a boron impurity having a surface concentration of about 7 × 10 ¹⁶ cm ^-3 so as to reach the P-type semiconductor substrate 10 in the element isolation region of the NPN bipolar transistor 1. The depth of the diffusion layer is 1.2 to 2.0 μm. The P-type well layer 14B has a surface concentration of 7 × 10 ¹⁶ cm ⁻³ so as to reach the P-type semiconductor substrate 10 of the N-channel MOS transistor ^3.
The boron layer is formed in the epitaxial layer by introducing an impurity of about boron, and the depth of the diffusion layer is 1.2 to 2.0 μm.

Element isolation layer 14A and P-type well layer 14B
Of the diffusion layer and the impurity concentration determine not only the device performance such as the device breakdown voltage and the junction capacitance of the N-channel MOS transistor 3 but also the device isolation breakdown voltage of the NPN bipolar transistor 1. Therefore, when the depths and impurity concentrations of the diffusion layers of the element isolation layer 14A and the P-type well layer 14B are insufficient, the breakdown voltage between the N-type buried collector layer 12A and the N-type buried well layer 12B decreases.

The LOCOS films 15 A, 15 C, 15 D, and 15 E are formed by selectively oxidizing element isolation regions of the NPN bipolar transistor 1, the P-channel MOS transistor 2, and the N-channel MOS transistor 3.
This is a device isolation film. The LOCOS film 15B is made of NP
Collector contact layer 2 of N bipolar transistor 1
4 and the separation region between the external base layer 34, an element isolation film formed by selectively oxidizing. These element isolation
The thickness of the film is 400-800 nm .

If the LOCOS film 15B is thin, the NPN
If the LOCOS film 15D is thin, the P-channel MOS transistor 2 and the N-channel M
This leads to a decrease in the element isolation breakdown voltage of the OS transistor 3.
If the thickness is too large, the step at the edge of the LOCOS film will increase.

The first gate oxide film 16C is an insulating film having a thickness of about 10 nm formed on the surface of the epitaxial layer of the P-channel MOS transistor 2 by a pyrogenic oxidation method. The second gate oxide film 16D has a thickness of 10 nm formed on the surface of the epitaxial layer of the N-channel MOS transistor 3 by a pyrogenic oxidation method.
This is a degree of insulating film.

In the NPN bipolar transistor 1, one end of the base extraction electrode 18A is bonded to the external base layer 34, and the other end of the base extraction electrode 18A is polycrystalline silicon having a thickness of 300 to 400 nm so as to ride on the LOCOS films 15B and 15C. After the film is deposited, the sheet resistance is 100-2
A P-type impurity boron of 00 Ω / □ is introduced and formed by etching.

The gate electrodes 18C and 18D are made of N-type impurities having a sheet resistance of 20 to 40 Ω / □ after a polycrystalline silicon film having a thickness of 300 to 400 nm is deposited on the P-channel MOS transistor 2 and the N-channel MOS transistor 3. Of phosphorus or arsenic is introduced and formed by etching.

The insulating film 19A on the base extraction electrode upper surface, the insulating film 19C on the first gate electrode upper surface, and the insulating film 19D on the second gate electrode upper surface have a thickness of 12
A TEOS film or the like of 0 to 250 nm is deposited and formed by etching.

In the P-channel MOS transistor 2, an oxide film 20C on the side surface of the first gate electrode, a silicon nitride film 21C on the side surface of the first gate electrode, and an insulating side wall 29A of the first gate electrode have a thickness of 100 to 200 nm.
Forms a first source / drain layer 30A in a self-aligned manner with respect to the first gate electrode 18C.

The first source / drain layer 30A has a junction depth of about 0.2 μm and a boron impurity having a surface concentration of 1 ×.
It is formed by being introduced at about 10 ²⁰ cm ^-3 . First LD
The D layer 27A has a junction depth of about 0.2 μm, an impurity of boron introduced at a surface concentration of about 1 × 10 ¹⁸ cm ⁻³ , and is formed using the silicon nitride film 21C on the side surface of the first gate electrode as a side wall.

In the N-channel MOS transistor 3, the oxide film 20D on the side surface of the second gate electrode, the silicon nitride film 21D on the side surface of the second gate electrode, and the insulating side wall 29B of the second gate electrode have a thickness of 100 to 200 nm.
Forms a second source / drain layer 31A in a self-alignment manner with respect to the second gate electrode 18D.

The second source / drain layer 31A has a junction depth of about 0.1 μm and an arsenic impurity having a surface concentration of 1 × 1.
It is formed by being introduced at about 0 ²⁰ cm ^-3 . Second LDD
The layer 28A is formed with a junction depth of about 0.2 μm, a phosphorus impurity introduced at a surface concentration of about 1 × 10 ¹⁸ cm ⁻³ , and the silicon nitride film 21D on the side surface of the second gate electrode as a side wall.

With these LDD structures, a P-channel MO
S transistor 2 and N channel MOS transistor 3
Hot carrier resistance is improved by optimizing the thickness of the insulating side wall 29A of the first gate electrode and the thickness of the insulating side wall 29B of the second gate electrode to 100 to 200 nm as described above. Sufficient device characteristics, such as performance and saturation drain current value, can be obtained.

In the NPN bipolar transistor 1, the oxide film 20A on the side surface of the first base extraction electrode having a thickness of 15 to 30 nm, the silicon nitride film 21A on the side surface of the first base extraction electrode having a thickness of 40 to 80 nm, and the thickness 200
On the side wall of the polycrystalline silicon film 22A having a thickness of 200 to 300 nm on the side surface of the first base extraction electrode having a thickness of about nm, the emitter extraction opening 33 is formed in a self-aligned manner.

The emitter extraction electrode 25 and the collector extraction electrode 26 are formed by etching by introducing arsenic of an N-type impurity having a thickness of 150 to 300 nm and a sheet resistance of 150 to 300 Ω / □.

The external base layer 34 has a junction depth of 0.2 to
0.4 μm and surface concentration of 1 × 10 ²⁰ cm ^{−3 to} 3 × 10 ²⁰
Impurity boron is introduced from the base extraction electrode 18A having a size of cm ⁻³ and is formed.

The active base layer 35 has a junction depth of 0.15
Surface concentration of 1 × 10 ¹⁹ cm ^{-3 to} 3 × 1
It is formed by introducing an impurity boron of 0 ¹⁹ cm ⁻³ .

The emitter layer 23 has a junction depth of 0.05 to
0.1 μm and surface concentration of 1 × 10 ²⁰ cm ^{−3 to} 3 × 10 ²⁰
Arsenic, which is an impurity of cm ^−3, is formed by being introduced from the emitter extraction electrode 25.

The collector contact layer 24 has a junction depth of 0.05 to 0.1 μm and a surface concentration of 1 × 10 ²⁰ cm ⁻³ .
Arsenic as an impurity of 3 × 10 ²⁰ cm ⁻³ is formed by being introduced from the collector extraction electrode 26.

As described above, on the side surface of the base extraction electrode 18A, the oxide film 20A on the side surface of the base extraction electrode, the silicon nitride film 21A on the side surface of the base extraction electrode, and the side surface of the base extraction electrode 18A in order from the side surface portion of the base extraction electrode 18A. By forming the three-layered side wall of the polycrystalline silicon film 22A, the emitter extraction opening 33 and the emitter layer 23 are formed in a self-aligned manner with respect to the base extraction electrode 18A and the external base layer 34. The oxide film 20A on the side surface of the base extraction electrode and the silicon nitride film 21A on the side surface of the base extraction electrode form the base extraction electrode 18.
It becomes an electrical insulating film between A and the emitter extraction electrode 25.

As a feature of this embodiment, since the thick insulating film on the side wall of the conventional base extraction electrode 18A is formed of two thin insulating films, the insulating film on the peripheral portion of the emitter-base junction contracts. The stress is reduced, and the leakage or the like generated between the emitter and the base can be suppressed. Further, since the side of the side of the base extraction electrode 18A which is in contact with the emitter extraction electrode 25 is made of polycrystalline silicon, which is a conductor, the substantial diameter of the polycrystalline silicon in the emitter extraction opening 33 is increased. Since the ratio (the ratio between the height and the diameter of the emitter extraction opening) is reduced, the emitter resistance of the emitter extraction electrode 25 made of polycrystalline silicon is reduced.

The same process as that for forming the polycrystalline silicon film 22A formed on the side surface of the base extraction electrode 18A is performed.
If the polycrystalline silicon film formed also on the side surface extending to the OCOS film 15B is not removed, other wiring layers leak or increase parasitic capacitance through the polycrystalline silicon film which is a conductor film. Although it is sufficiently conceivable that the characteristics of the NPN bipolar transistor 1 may be deteriorated by performing the above process, it is removed by the process of forming the insulating side wall 29A of the first gate electrode. Can be avoided.

The three-layered side wall of the base extraction electrode 18A of the NPN bipolar transistor 1 leads to an increase in the base resistance when the side wall is thick, and the carrier traveling affected by the external base layer 34 having a high impurity concentration when the side wall is thin. Leads to an increase in time. NPN bipolar transistor 1
The thickness of the three-layer side wall that determines the first parameter of the operating characteristics of the above is optimized to 200 to 300 nm as described above. The first gate electrode 18C and the second gate electrode 18C determine the second parameter of the operating characteristics of the P-channel MOS transistor 2 and the N-channel MOS transistor 3.
The thickness of the side wall of the gate electrode 18D is 10 as described above.
It is optimized to be 0 to 200 nm, and the effect of independently optimizing the thickness of the side wall of each electrode of the NPN bipolar transistor 1 and the MOS transistors 2 and 3 is extremely large.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 2 to 7 are sectional views in the order of steps of a method for manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention. In FIG. 2, reference numeral 10 denotes a P-type semiconductor substrate made of silicon, and 11 denotes N deposited on the entire surface of the P-type semiconductor substrate 10.
Epitaxial semiconductor layer, 1 is a P-type semiconductor substrate 10
The upper NPN bipolar transistor, 2 is a P-channel MOS transistor on the P-type semiconductor substrate 10, 3 is an N-channel MOS transistor on the P-type semiconductor substrate 10, 12
A is an N-type buried collector layer of the NPN bipolar transistor 1 formed on the P-type semiconductor substrate 10;
Is a P-channel M formed on the P-type semiconductor substrate 10
This is an N-type buried well layer of the OS transistor 2.

The semiconductor integrated circuit device according to the present embodiment described below has an NPN bipolar transistor on a P-type semiconductor substrate 10 made of silicon having a specific resistance of about 10 Ω · cm into which boron is introduced and a plane orientation of (100). 1, a P-channel MOS transistor 2 and an N-channel MOS transistor 3 are integrated.

First, a window is opened on the surface of the P-type semiconductor substrate 10 by photolithography in a region where a resist NPN bipolar transistor 1 and a P-channel MOS transistor 2 are to be formed. Using this resist pattern as a mask, arsenic or antimony ions are implanted from the surface of the P-type semiconductor substrate 10. The dose of ion implantation is 1 ×
Acceleration energy is about 40-60 keV at about 10 ¹⁵ cm ^-2
It is.

Next, after removing the resist by plasma ashing using oxygen gas, the temperature was reduced to 1150 to 1200.
Heat treatment for about 15 to 30 minutes at ℃
An N-type buried collector layer 12A and an N-type buried well layer 12B having a sheet resistance of 50 μm / □ to 2 μm are formed.

Next, an N-type epitaxial layer 11 having a thickness of 0.8 to 1.5 μm and a specific resistance of 1 to 5 Ω · cm due to arsenic or phosphorus impurities is deposited on the surface of the P-type semiconductor substrate 10. The N-type epitaxial layer 11 has a temperature of 1050 using a mixed gas of dichlorosilane and arsine.
The deposition is performed at a temperature of about 80 × 133.322 Pa.

Next, in FIG. 3, a description will be given of the manufacturing method after describing the reference numerals newly added to FIG. 13A
Is an N-type collector layer formed on the N-type epitaxial layer 11, 13B is an N-type well layer formed on the N-type epitaxial layer 11, and 14A is a P-type layer formed on the N-type epitaxial layer 11. An element isolation layer 14B formed to reach the semiconductor substrate 10 is a P-type well layer of the N-channel MOS transistor 3 formed to reach the P-type semiconductor substrate 10 above the N-type epitaxial layer 11, 15A, 15B. , 15C, 15D and 15E are LOCOS films for isolating respective elements, 16A is an insulating film formed by oxidizing the surface of the N-type epitaxial layer 11, 16C
Is a first gate insulating film of the P-channel MOS transistor 2 formed by oxidizing the surface of the N-type epitaxial layer 11, and 16D is a first gate insulating film of the N-channel MOS transistor 3 formed by oxidizing the surface of the N-type epitaxial layer 11. This is a second gate insulating film.

First, a window is opened in a predetermined region of the surface of the N-type epitaxial layer 11 where a resist NPN bipolar transistor 1 and a P-channel MOS transistor 2 are to be formed using photolithography. Using this resist pattern as a mask, phosphorus ions are implanted from the surface of the N-type epitaxial layer 11. The dose of the ion implantation is about 1 × 10 ¹³ cm ⁻² and the acceleration energy is 100 ke.
About V.

Next, after removing the resist by plasma ashing using oxygen gas, a resist window is opened using photolithography in the element isolation region of the NPN bipolar transistor 1 and the formation region of the N-channel MOS transistor 3. Boron ions are implanted using the resist pattern as a mask. The dose of ion implantation is 1 × 1
The acceleration energy is 20 at 0 ¹³ cm ^{-2 to} 2 × 10 ¹³ cm ^-2.
It is about keV. After removing the resist by plasma ashing with oxygen gas, the temperature was reduced to 11 in a nitrogen gas atmosphere.
A heat treatment is performed at about 00 ° C. for 90 to 150 minutes.

Thus, the depth of the diffusion layer reaching N-type buried collector layer 12A of NPN bipolar transistor 1 is 0.8 to 1.5 μm and the surface concentration is 5 × 10 ¹⁶ cm.
The depth of the diffusion layer reaching the N-type collector layer 13A of about ^-3 and the N-type buried well layer 12B of the P-channel MOS transistor 2 is 0.8 to 1.5 μm, and the surface concentration is 5 × 10 5
An N-type well layer 13B of about ¹⁶ cm ^-3 is formed. Further, the depth of the diffusion layer reaching the P-type semiconductor substrate 10 in the element isolation region of the NPN bipolar transistor 1 is 1.2 to
An element isolation layer 14A having a surface concentration of about 7 × 10 ¹⁶ cm ^{−3 at} 2.0 μm and a diffusion layer reaching the P-type semiconductor substrate 10 of the N-channel MOS transistor 3 having a depth of 1.2 to 2.
A P-type well layer 14B having a thickness of 0 μm and a surface concentration of about 7 × 10 ¹⁶ cm ⁻³ is formed.

Next, the surface of the epitaxial layer 11 is
A silicon nitride film to be used as a selective mask when forming a COS film is formed. The silicon nitride film is deposited to a thickness of about 120 nm by a low pressure CVD method using a mixed gas of dichlorosilane and ammonia. An NPN bipolar transistor 1, a P-channel MOS transistor 2 and an NPN bipolar transistor 1 are formed on the silicon nitride film by photolithography.
Element isolation region of channel MOS transistor 3 and N
The silicon nitride film is removed by dry etching using a predetermined resist pattern in the base collector electrode lead-out portion separation region of the PN bipolar transistor 1 as a mask. For dry etching, a mixed gas of a chlorofluorocarbon gas and a bromine-based gas is used. By this dry etching, the silicon nitride film at a predetermined position in the element isolation region is removed. After removing the resist by oxygen plasma ashing, pyrogenic oxidation is performed at a temperature of about 1050 ° C. for about 60 minutes, and the LOCOS films 15A, 15B, 15
Form C, 15D and 15E. The thickness of these LOCOS films is 400 to 800 nm.

Next, after removing the silicon nitride film using a phosphoric acid solution, a resist window is opened using photolithography in a predetermined region where the P-channel MOS transistor 2 is to be formed, and the dose is determined using this resist pattern as a mask. Is implanted with boron ions of about 4 × 10 ¹² cm ⁻² and acceleration energy of about 20 KeV. This is a P-channel MOS
This is impurity introduction for controlling the threshold voltage of the transistor 2. After removing the resist by oxygen plasma ashing, a resist window is similarly opened in a predetermined region where the N-channel MOS transistor 3 is to be formed by photolithography, and a dose of 3 × 10 ¹² cm ⁻² is formed using this resist pattern as a mask. About 40K acceleration energy
Implant boron ions of about eV. Thereby, the threshold voltage of N channel MOS transistor 3 is controlled.
By the above-described threshold-controlled ion implantation, the P-channel M
The threshold voltage of the OS transistor 2 is -0.5 to -0.0.
8V, the threshold voltage of the N-channel MOS transistor 3 is 0.5 to 0.8V.

Next, after removing the resist by oxygen plasma ashing, the entire surface of the N-type epitaxial layer 11 is subjected to pyrogenic oxidation at a temperature of about 900 ° C. for about 30 minutes to form an insulating film 16A having a thickness of about 10 nm. A first gate insulating film 16C and a second gate insulating film 16D are formed.

Next, in FIG. 4, a description will be given of the manufacturing method after describing the reference numerals newly added to FIG. Reference numeral 17 denotes a self-aligned emitter / base forming region, 1
8A is a base lead electrode of the NPN bipolar transistor 1 made of polycrystalline silicon, and 18C is a P-channel MO.
A first gate electrode made of polycrystalline silicon of the S transistor 2, 18D is a second gate electrode made of polycrystalline silicon of the N-channel MOS transistor 3, and 19A is NP
An insulating film on the upper surface of the base extraction electrode made of the TEOS film of the N bipolar transistor 1, 19C is a P-channel MOS
An insulating film on the upper surface of the first gate electrode made of the TEOS film of the transistor 2, 19D is an insulating film on the upper surface of the second gate electrode made of the TEOS film of the N-channel MOS transistor 3, and 20A is oxidized by the heat treatment of the NPN bipolar transistor 1. An oxide film on the side surface of the base extraction electrode formed as described above, 20C is an oxide film on the side surface of the first gate electrode formed by oxidation of the P-channel MOS transistor 2, and 20D is an oxide film on the side surface of the N-channel MOS transistor 3. An oxide film formed on the side surface of the second gate electrode formed by oxidation, 34 is an external base layer of the NPN bipolar transistor 1, and 35 is an active base layer of the NPN bipolar transistor 1.

First, using a predetermined resist pattern using photolithography as a mask, the insulating film 16A shown in FIG. 3 in the region of the NPN bipolar transistor 1 is selectively etched using a mixed solution of ammonium fluoride and hydrofluoric acid. And remove.

Next, after removing the resist by oxygen plasma ashing, the entire surface of the epitaxial layer 11 is formed to a thickness of 300 to 400 by a low pressure CVD method using silane gas.
After depositing a polycrystalline silicon film for forming an electrode of each element of 5 nm, using a predetermined resist pattern of the NPN bipolar transistor 1 as a mask, the dose amount is 5 ×
The acceleration energy is 4 at 10 ¹⁵ cm ^-2 to 1 × 10 ¹⁶ cm ^-2
Boron ions of about 0 KeV are implanted. Thereafter, the resist is removed by oxygen plasma ashing. Next, using a predetermined resist pattern of the P-channel MOS transistor 2 and the N-channel MOS transistor 3 as a mask,
Phosphorus ions with a dose of 1.5 × 10 ¹⁶ cm ^{−2 to} 3 × 10 ¹⁶ cm ⁻² and an acceleration energy of about 40 KeV are implanted.

Next, after the resist is removed by oxygen plasma ashing, the entire surface of the deposited polycrystalline silicon film is formed to a thickness of 120 to 120 ° C. by a reduced pressure CVD method at a temperature of about 700 ° C. using a mixed gas of TEOS and oxygen. Deposit a 250 nm oxide film. Next, using a predetermined resist pattern as a mask, the oxide film deposited using a mixed gas of CHF ₃ , ammonia and oxygen is dry-etched. Subsequently, anisotropic etching is performed on the polycrystalline silicon film deposited using a mixed gas of SF ₆ and C ₂ ClF _5, and the sheet resistance of the NPN bipolar transistor 1 becomes 100 to 200.
A base extraction electrode 18A of Ω / □ is formed, and a P-channel MOS transistor 2 and an N-channel M
The first gate electrode 18C and the second gate electrode 18 in which the sheet resistance of the OS transistor 3 becomes 20 to 40 Ω / □
Form D. On each electrode, insulating films 19A, 19C and 19D made of an oxide film having a thickness of 120 to 250 nm are formed, and at the same time, the emitter / base forming region 17 of the NPN bipolar transistor 1 is opened.

Next, after the resist pattern is removed by oxygen plasma ashing, the temperature in an oxygen atmosphere is 900 ° C.
Heat treatment for about 30 minutes, thickness 15-30nm
Oxide film 20A on the side of the base extraction electrode of NPN bipolar transistor 1, oxide film 20C on the side of the first gate electrode of P-channel MOS transistor 2, and oxide film on the side of the second gate electrode of N-channel MOS transistor 3 Form 20D.

Next, a boron impurity in the base extraction electrode 18A of the NPN bipolar transistor 1 is introduced into the N-type collector layer 13A by a heat treatment at a temperature of about 950 ° C. in a nitrogen atmosphere for about 30 minutes. 0.2 ~
0.4 μm and surface concentration of 1 × 10 ²⁰ cm ^{−3 to} 3 × 10 ²⁰
An external base layer 34 of cm ⁻³ is formed.

Next, using a resist pattern formed by photolithography and the base lead-out electrode 18A of the NPN bipolar transistor 1 as a mask, a dose amount of 1 × 10
Boron ions of about ¹³ cm ⁻² and acceleration energy of about 10 KeV are implanted into the emitter / base formation region 17 to have a junction depth of 150 to 250 nm and a surface concentration of 1 × 10 ¹⁹ c.
An active base layer 35 of m ^{-3 to} 3 × 10 ¹⁹ cm ^-3 is formed. After that, the resist pattern is removed by oxygen plasma ashing.

Next, in FIG. 5, a description will be given of the manufacturing method after describing the reference numerals newly added to FIG. 21
A is a silicon nitride film on the side of the base extraction electrode of the NPN bipolar transistor 1, 21C is a silicon nitride film on the side of the first gate electrode of the P-channel MOS transistor 2, and 21D is a silicon nitride film on the side of the second gate electrode of the N-channel MOS transistor 3. A silicon nitride film, 22A and 22B are polycrystalline silicon films on the side of the base extraction electrode of the NPN bipolar transistor 1, 22E is a polycrystalline silicon film on the side of the first gate electrode of the P-channel MOS transistor 2, and 22F is an N-channel MOS transistor 3. second polycrystalline silicon film of the gate electrode side of the 33 polycrystalline silicon
An emitter lead-out opening formed in a self-aligned manner by the sidewalls of the capacitor films 22A and 22B .

First, an insulating film on the side surface of each electrode of 40 to 80 nm is formed on the entire surface of each element on the N-type epitaxial layer 11 by a reduced pressure CVD method using a mixed gas of dichlorosilane and ammonia. A silicon nitride film is deposited.

Next, a polycrystalline silicon film for forming the side walls of the base extraction electrodes 18A and 18C of the NPN bipolar transistor 1 having a thickness of about 200 nm is formed on the silicon nitride film deposited by the low pressure CVD method using silane gas. accumulate.

Next, the polycrystalline silicon film deposited by using a mixed gas of SF ₆ and CCl ₄ is subjected to anisotropic etching, so that the polycrystalline silicon film 22
A and 22B, a polycrystalline silicon film 22E on the first gate electrode side surface and a polycrystalline silicon film 22F on the second gate electrode side surface are formed.

Next, etching is performed by using a mixed gas of a chlorofluorocarbon gas and a bromine-based gas, and the silicon nitride film 21A on the side of the base extraction electrode, the side of the first gate electrode, and the side wall made of the polycrystalline silicon film as a mask. The silicon nitride film 21C and the silicon nitride film 21D on the side surface of the second gate electrode are formed.

Next, using a mixed solution of ammonium fluoride and hydrofluoric acid, the collector electrode formation region and the emitter lead-out opening 33 of the NPN bipolar transistor 1 and the source / drain formation regions of the MOS transistors 2 and 3 are etched. To remove the oxide film. Thereby, the NPN
In the bipolar transistor 1, a 200-300 nm-thick side wall composed of three layers of the oxide film 20A on the side of the base extraction electrode, the silicon nitride film 21A on the side of the base extraction electrode, and the polycrystalline silicon film 22A on the side of the base extraction electrode is formed. At the same time, the emitter extraction opening 33 is formed in a self-aligned manner.

As a feature of the present embodiment, the first parameter which determines the base resistance value of the NPN bipolar transistor 1 and the carrier transit time in the base is self-aligned by the three-layered side wall formed in the above steps. Is determined.

Next, referring to FIG. 6, a description will be given of a manufacturing method after explaining the reference numerals newly added to FIG. Reference numeral 23 denotes an emitter layer formed in a self-aligned manner by the polycrystalline silicon films 22A and 22B on the side of the base extraction electrode of the NPN bipolar transistor 1, 24 denotes a collector contact layer formed by heat treatment of the NPN bipolar transistor 1, and 25 denotes an NPN bipolar transistor. The emitter lead-out electrode made of polycrystalline silicon of the transistor 1 and NPN 26
The collector lead electrode 27A of the bipolar transistor 1 made of polycrystalline silicon is a silicon nitride film 21C on the side surface of the first gate electrode of the P-channel MOS transistor 2.
First LDD layer formed as a side wall, 2
Reference numeral 8A denotes a second LDD layer formed by using the silicon nitride film 21D on the side surface of the second gate electrode of the N-channel MOS transistor 3 as a side wall.

First, polycrystalline silicon for forming an emitter extraction electrode 25 and a collector extraction electrode 26 with a thickness of 150 to 300 nm on the entire surface of each element on the N-type epitaxial layer 11 by a low pressure CVD method using silane gas. Deposit the film. 1 × dose to the deposited silicon film
Arsenic ions of about 10 ¹⁶ cm ^-2 and acceleration energy of about 60 KeV are implanted.

Next, at a temperature of 900 ° C. in a nitrogen atmosphere.
Heat treatment is performed for 30 to 60 minutes to diffuse the arsenic impurity in the deposited silicon film into the N-type collector layer 13A of the NPN bipolar transistor 1 to form the collector contact layer 24 and to diffuse into the active base layer 35. To form an emitter layer 23. The junction depth of the collector contact layer 24 and the emitter layer 23 is 50 to 100 nm, and the surface concentration is 1 × 10 ²⁰ cm ^{−3 to} 3 × 10 ²⁰ cm ⁻³ .

Next, a predetermined resist pattern formed by photolithography is used as a mask, and a pressure of 100 × 133.322 mPas using a mixed gas of HCl, HBr and oxygen.
RF etching was performed on the deposited polycrystalline silicon film at ~ 200 × 133.322 mPa, and the sheet resistance was 1
50-300Ω / □ NPN bipolar transistor 1
Emitter extraction electrode 25 and collector extraction electrode 26
To form

Next, RF etching under the same conditions as the above-described etching is continuously performed, and the side surface of the base extraction electrode 18A other than the emitter / base formation region 17 of the NPN bipolar transistor 1 and the P-channel MOS transistor 2
The polycrystalline silicon film 22E on the side surface of the first gate electrode and the polycrystalline silicon film 22F on the side surface of the second gate electrode of the N-channel MOS transistor 3 are removed. After that, the resist is removed by oxygen plasma ashing.

Next, using a resist pattern by photolithography and the silicon nitride film 21C on the side surface of the first gate electrode of the P-channel MOS transistor 2 as a mask, the dose is about 5 × 10 ¹² cm ⁻² and the acceleration energy is 20 KeV. The first LDD layer 27A of the P-channel MOS transistor 2 is formed in a self-alignment manner with respect to the silicon nitride film 21C on the side surface of the first gate electrode by implanting boron ions of a degree. The junction depth of the first LDD layer 27A is about 0.2 μm and the surface concentration is about 1 × 10 ¹⁸ cm ⁻³ . After that, the resist is removed by oxygen plasma ashing.

Next, a resist pattern is formed by photolithography using the silicon nitride film 21D on the side surface of the second gate electrode of the N-channel MOS transistor 3 as a mask.
The dose is about 1 × 10 ¹³ cm ^-2 and the acceleration energy is 4
By implanting phosphorus ions of about 0 KeV, N 2 is self-aligned with the silicon nitride film 21D on the side surface of the second gate electrode.
Second LDD layer 28A of channel MOS transistor 3
To form The junction depth of the second LDD layer 28A is 0.2
At about μm, the surface concentration is about 1 × 10 ¹⁸ cm ⁻³ . After that, the resist is removed by oxygen plasma ashing.

As a feature of this embodiment, since the conventional thick insulating film on the side wall of the emitter lead-out electrode 18A is formed as a thin two-layer insulating film, the shrinkage stress of the insulating film applied to the periphery of the emitter-base junction is reduced. And leakage between the emitter and the base can be suppressed. Further, since the side wall of the side surface of the base extraction electrode 18A which is in contact with the emitter extraction electrode 25 is made of polycrystalline silicon which is a conductor, the substantial diameter of the emitter extraction opening 33 is increased. (The ratio of height to diameter) is reduced, and the emitter resistance of the emitter extraction electrode 25 made of polycrystalline silicon is reduced.

If the polycrystalline silicon film formed on the side surface of the base extraction electrode 18A other than the emitter / base formation region 17 of the NPN bipolar transistor 1 is not removed, the polycrystalline silicon film is a conductor film. As a result, there is a possibility that the characteristics of the NPN bipolar transistor 1 are degraded by leaking other conductor layers or increasing the parasitic capacitance. However, since this polycrystalline silicon film has been removed by the step of removing the polycrystalline silicon film 22E and the like on the side surface of the first gate electrode, this problem can be avoided without particularly increasing the number of steps.

Next, in FIG. 7, a description will be given of the manufacturing method after describing the reference numerals newly added to FIG. 29A
Is an insulating side wall of the first gate electrode made of the TEOS film of the P-channel MOS transistor 2, and 29B is an N-channel M
The insulating side wall 30A of the second gate electrode made of the TEOS film of the OS transistor 3 and the first source electrode 30A formed in a self-aligned manner using the insulating side wall 29A of the first gate electrode of the P-channel MOS transistor 2 as a side wall. A drain layer 31A is a second source / drain layer formed in a self-aligned manner using the insulating side wall 29B of the second gate electrode of the N-channel MOS transistor 3 as a side wall;
Reference numeral 32A is an insulating side wall of a base lead electrode made of a TEOS film of the NPN bipolar transistor 1.

First, an insulating film on the side wall of a gate electrode having a thickness of about 150 nm is formed on the entire surface of each element on the N-type epitaxial layer 11 by a reduced pressure CVD method at a temperature of about 700 ° C. using a mixed gas of TEOS and oxygen. An oxide film for forming is deposited.

Next, the oxide film deposited using a mixed gas of CHF ₃ , oxygen and helium is subjected to anisotropic etching to form an insulating side wall 29 A of the first gate electrode of the P-channel MOS transistor 2 and an N-channel MOS transistor. The insulating side wall 29B of the second gate electrode of the transistor 3 and the insulating side wall 3 of the base extraction electrode of the NPN bipolar transistor 1
Form 2A.

Thus, the P-channel MOS transistor 2 is composed of three layers: the oxide film 20C on the side surface of the first gate electrode, the silicon nitride film 21C on the side surface of the first gate electrode, and the insulating side wall 29A of the first gate electrode. Side walls are formed. In addition, a side wall including three layers of an oxide film 20D on the side surface of the second gate electrode of the N-channel MOS transistor 3, a silicon nitride film 21D on the side surface of the second gate electrode, and an insulating side wall 29B of the second gate electrode is formed. You.

As a feature of this embodiment, a P-channel MO
The second parameter that affects the hot carrier resistance and the saturated drain current value of the S transistor 2 is determined in a self-aligned manner by the three-layered sidewall formed in the above steps. The same applies to N-channel MOS transistor 3. Therefore, the first parameter that determines the operating characteristics of the NPN bipolar transistor 1 and the P-channel M
It can be determined independently of the second parameter that determines the operating characteristics of the OS transistor 2 and the N-channel MOS transistor 3, and the respective optimum values can be obtained.

Next, using a resist pattern by photolithography and the insulating side wall 29A of the first gate electrode of the P-channel MOS transistor 2 as a mask, the dose is about 5 × 10 ¹⁵ cm ⁻² and the acceleration energy is 10 KeV.
The first source / drain layer 30A of the P-channel MOS transistor 2 is formed in a self-aligned manner with respect to the insulating side wall 29A of the first gate electrode by implanting boron ions of a degree. The first source / drain layer 30A has a junction depth of 0.1 mm.
The surface density is about 1 × 10 ²⁰ cm ^{−3 at} about 2 μm.

Next, after removing the resist by oxygen plasma ashing, the resist pattern is formed by photolithography and the insulating sidewall 29B of the second gate electrode of the N-channel MOS transistor 3 is used as a mask, and the dose is 5 × 10 ¹⁵ cm ^−. Arsenic ions of about ² and an acceleration energy of about 40 KeV are implanted, and a second source / drain layer 31A of the N-channel MOS transistor 3 is formed in a self-alignment manner with the insulating side wall 29B of the second gate electrode. The junction depth of the second source / drain layer 31A is 0.1 μm.
And the surface concentration is about 1 × 10 ²⁰ cm ⁻³ . After that, the resist is removed by oxygen plasma ashing.

[0102]

As described above, according to the semiconductor integrated circuit device of the first aspect, the first side wall formed on the side surface of the base extraction electrode of the bipolar transistor and the side surface of the gate electrode of the MOS transistor. Can be formed by a different process. Since the distance between the external base layer and the emitter layer of the bipolar transistor and the distance between the gate electrode and the source / drain layer of the MOS transistor can be independently adjusted, these distances are respectively optimized.

The first side wall formed on the side surface of the base extraction electrode of the bipolar transistor is composed of a thin insulating film on the base extraction electrode side and a conductor film on the side opposite to the base extraction electrode. As a result, the shrinkage stress applied to the peripheral portion of the emitter-base junction is reduced, so that deterioration of characteristics such as leakage between the emitter and the base can be avoided.

Furthermore, since the conductor film on the first side wall is integrated with the emitter extraction electrode and the diameter of the emitter extraction electrode is substantially increased, the aspect ratio (the ratio between the height and the diameter of the emitter extraction opening) is small. Therefore, the emitter resistance of the emitter extraction electrode is reduced.

In addition, since the space between the external base layer and the emitter layer of the bipolar transistor and the space between the gate electrode and the source / drain layer of the MOS transistor can be independently adjusted, the first and second parameters are increased. Has been further optimized. Further, since the third insulating film becomes thinner and the conductor film becomes thicker, deterioration of characteristics such as leakage between the emitter and the base is further improved, and the emitter resistance is further reduced.

[0106] According to the semiconductor integrated circuit device according to the invention of claim 2 can be on the effects of the semiconductor integrated circuit device according to the invention of claim 1 is obtained, to reliably obtain a fifth insulating film.

According to the semiconductor integrated circuit device of the third aspect of the present invention, the effect of the semiconductor integrated circuit device of the first aspect of the present invention can be obtained. Is formed also on the side surface extending on the element isolation film surrounding the element isolation film, so that other conductor layers leak through each other and increase the parasitic capacitance through this conductor film as compared with the case where the conductor film is not removed. The characteristic deterioration of the bipolar transistor can be prevented without increasing the number of steps.

According to the semiconductor integrated circuit device of the fourth aspect of the present invention, the effects of the semiconductor integrated circuit device of the first aspect of the present invention can be obtained, and the third insulating film can be reliably obtained.

According to the semiconductor integrated circuit device according to the fifth aspect of the present invention, the effect of the semiconductor integrated circuit device according to the first aspect of the present invention can be obtained, and the conductor film can be reliably obtained.

[0110] independently with the method for fabricating a semiconductor integrated circuit device according to the invention of claim 6, the distance between the external base layer and the emitter layer of a bipolar transistor, and a distance between the gate electrode and the source-drain layer of the MOS transistor Therefore, the base resistance value and the carrier transit time in the base that affect the operation characteristics of the bipolar transistor, and the hot carrier resistance and the saturated drain current value that affect the operation characteristics of the MOS transistor are optimized.

The first side wall formed on the side surface of the base extraction electrode of the bipolar transistor is formed of a thin insulating film on the base extraction electrode side and a conductor film on the side opposite to the base extraction electrode. As a result, the shrinking stress applied to the peripheral portion of the emitter-base junction is reduced, so that deterioration of characteristics such as leakage between the emitter and the base can be prevented.

Since the conductor film on the first side wall is integrated with the emitter extraction electrode and substantially increases the diameter of the emitter extraction electrode, the aspect ratio (the ratio between the height and the diameter of the emitter extraction opening) is small. Therefore, the emitter resistance of the emitter extraction electrode is reduced.

Further, since the conductor film on the first side wall formed on the side surface on which the base extraction electrode extends on the element isolation film surrounding the external base is removed, the case where the conductor film is not removed is provided. In comparison with this, it is possible to prevent the deterioration of the characteristics of the bipolar transistor, in which the other wiring layers leak or increase the parasitic capacitance via the conductor film, without increasing the number of steps.

In addition, since the distance between the external base layer and the emitter layer of the bipolar transistor and the distance between the gate electrode and the source / drain layer of the MOS transistor can be independently adjusted, the first and second parameters are increased. Has been further optimized. Further, since the third insulating film becomes thinner and the first conductor film becomes thicker, deterioration in characteristics such as leakage between the emitter and the base is further improved, and the emitter resistance is further reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view in a process order of a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view in a process order of a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view in a process order of a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view in a process order of a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a sectional view in order of process of a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view in a process order of a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 8 is a sectional view of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 NPN bipolar transistor 2 P-channel MOS transistor 3 N-channel MOS transistor 10 P-type semiconductor substrate 11 N-type epitaxial layer 12A N-type buried collector layer 12B N-type buried well layer 13A N-type collector layer 13B N-type well layer 14A Element isolation Layer 14B P-type well layer 15A LOCOS film 15B LOCOS film 15C LOCOS film 15D LOCOS film 15E LOCOS film 16A Insulating film 16C First gate insulating film 16D Second gate insulating film 17 Emitter / base forming region 18A Base extraction electrode 18C No. 1 gate electrode 18D Second gate electrode 19A Insulating film on top surface of base extraction electrode 19C Insulating film on top surface of first gate electrode 19D Insulating film on second gate electrode upper surface 20A Acid on side surface of base extraction electrode Film 20C Oxide film on first gate electrode side surface 20D Oxide film on second gate electrode side surface 21A Silicon nitride film on base extraction electrode side surface 21C Silicon nitride film on first gate electrode side surface 21D Second gate electrode side surface 22A Polycrystalline silicon film on the side of base extraction electrode 22B Polycrystalline silicon film on the side of base extraction electrode 22E Polycrystalline silicon film on the side of first gate electrode 22F Polycrystalline silicon film on the side of second gate electrode 23 Emitter Layer 24 Collector contact layer 25 Emitter extraction electrode 26 Collector extraction electrode 27A First LDD layer 28A Second LDD layer 29A Insulating side wall of first gate electrode 29B Insulating side wall of second gate electrode 30A First source / drain Layer 31A Second source / drain layer 32A Base extraction Insulating side wall of electrode 33 Emitter extraction opening 34 External base layer 35 Active base layer 51 NPN bipolar transistor 52 P-channel MOS transistor 53 N-channel MOS transistor 54 P-type semiconductor substrate 55A N-type buried collector layer 55B N-type buried well layer 56A N-type collector layer 56B N-type well layer 57 First P-type well layer 58 Second P-type well layer 59 LOCOS film 60A First gate insulating film 60B First gate insulating film 61 Emitter / base forming region 62A Base Leading electrode 62C First gate electrode 62D Second gate electrode 63A Insulating film on top surface of base leading electrode 63C Insulating film on top surface of first gate electrode 63D Insulating film on second gate electrode upper surface 64A Insulating side wall of base leading electrode 64B Absolute base extraction electrode Side wall 64C Insulated side wall of base extraction electrode 64D Insulated side wall of base extraction electrode 64E Insulated side wall of first gate electrode 64G Insulated side wall of second gate electrode 65 Emitter extraction opening 66 Emitter extraction electrode 67 Collector extraction electrode 68 External base layer 69 Active base layer 70 Emitter layer 71 Collector contact layer 72A First LDD layer 72C Second LDD layer 73A First source / drain layer 73C Second source / drain layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8249 H01L 27/06

Claims (6)

(57) [Claims] A first insulating film connected to an external base layer surrounding the base layer and having a first insulating film on an upper surface and a first insulating film on a side surface;
A base electrode having sidewalls, the base lead-out conductive
A gate electrode having a second sidewall on the side surface and having a second insulating film on the bipolar transistor, and an upper surface having an emitter self-aligned manner forming layer and the emitter extraction electrode by said To pole first side wall And the gate
In the semiconductor integrated circuit device which MOS transistors are mixed on the same semiconductor substrate and a source-drain layers formed in a self-aligned manner by said To pole second sidewall, the first sidewall base lead A third insulating film on the electrode side and a conductive film on the side opposite to the base extraction electrode, wherein the second side wall is formed by the same process as the third insulating film.
A fourth insulating film formed on the gate electrode side and an anti-gate electrode;
A semiconductor integrated circuit device comprising a pole-side fifth insulating film . 2. The semiconductor integrated circuit device according to claim 1 , wherein said fifth insulating film is a silicon oxide film. 3. The semiconductor integrated circuit according to claim 1, wherein the second side wall is also formed on a side surface on a side where the base lead-out electrode extends on an element isolation film surrounding the external base. Circuit device. 4. The semiconductor integrated circuit according to claim 1, wherein said third insulating film comprises an oxide film and a silicon nitride film of said electrode formed in order from a side contacting said base lead electrode. apparatus. 5. The semiconductor integrated circuit device according to claim 1, wherein said conductive film is made of polycrystalline silicon. 6. A first step of forming an element isolation film for insulating a bipolar transistor and a MOS transistor on a semiconductor substrate, and forming a gate insulating film in an element region excluding the element isolation film, and forming the bipolar transistor. A second step of sequentially depositing a first conductor film and a first insulating film over the entire surface of the semiconductor substrate after removing the gate insulating film in a region to be etched by etching; And etching the base film of the bipolar transistor, the insulating film on the base extraction electrode, and the MO.
A third step of forming an insulating film on the gate electrode and the gate electrode of the S transistor on a side surface of the base side of the extraction electrode, the upper surface and the gate electrode of the emitter formation region surrounded by the base extraction electrode a After forming the second insulating film, a fourth insulating film and a second conductor film are sequentially deposited on the entire surface of the semiconductor substrate.
And etching the second conductor film,
A fifth step of forming a first side wall composed of the second insulating film, the third insulating film, and the second conductive film on a side surface of the base extraction electrode and a side surface of the gate electrode; And removing the third insulating film and the second insulating film on the source / drain formation region by etching using the first side wall as a mask, thereby forming an opening of the emitter extraction electrode in a self-aligned manner. A sixth step, and after depositing a third conductor film on the entire surface of the semiconductor substrate,
By selectively etching the third conductor film,
To form the emitter drawing electrode on the opening of the emitter lead-out electrode, the base lead-out conductive than the side surface of the emitter lead-out electrode covered by said base electrode
A seventh step of removing the second conductive film in the first side wall on the side surface of the pole and the side surface of the gate electrode by etching;
And after depositing a fourth insulating film on the entire surface of the semiconductor substrate,
Etching the fourth insulating film to form a second side wall composed of the second insulating film, the third insulating film, and the fourth insulating film on a side surface of the gate electrode; 8
And a ninth step of forming a source / drain formation region in a self-aligned manner by the second side wall and the gate electrode.