JP3241894B2 - Absolute encoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder, and more particularly to a means for converting an absolute pattern into an absolute position.

[0002]

2. Description of the Related Art For example, a conventional absolute encoder for converting an absolute pattern of a maximum period sequence (M sequence) into an absolute position is disclosed in Japanese Patent Application Laid-Open No. 57-17521.
No. 1 and Japanese Patent Application Laid-Open No. 63-231215 have an absolute encoder. JP-A-57-17
In the absolute encoder disclosed in Japanese Patent No. 5211, a ROM is used as an absolute position conversion means, and the absolute position of the detected position is directly obtained from each detected absolute signal. In other words, the absolute position can be converted at all the detected positions representing the absolute position by using a ROM which is a lookup table for converting the detected data into the absolute position.

On the other hand, in the absolute encoder disclosed in Japanese Patent Application Laid-Open No. 63-231215, every time one clock pulse is input after clearing the reference M code generation circuit, the M corresponding to the rotational position (θ) of the code plate is input. Different M codes are sequentially output until the code (m) is reached. M code (m) corresponding to rotation position (θ) from reference M code generation circuit
Is output, the number of clock pulses input until the M code (m) is output is counted by a counter so that the M code (m) corresponds to the rotational position (θ). It was made.

[0004]

As described above, in the conventional absolute encoder, the absolute position conversion is performed by a ROM or a pattern generation circuit. In the former case, in which absolute position conversion is performed for all positions using the ROM, the capacity of the ROM increases as the number of pulses (the number of minimum reading units) of the absolute encoder increases. For example, when 2 ⁿ pulses become 2 ^{n + 1} pulses, the capacity of the ROM becomes 2 · (n + 1) / n times. Therefore, the circuit of the absolute encoder is changed to a semi-custom I
If created in C, most of the number of gates of the semi-custom IC is used for the ROM portion for absolute position conversion, and the semi-custom IC cannot be used as a control section of the encoder. There was an inconvenience that I could not do it.

In the latter case where the absolute position conversion is performed by the pattern generation circuit, the time required for the absolute position conversion varies greatly depending on the absolute pattern, that is, depending on the positional relationship between the reference position and the detected position. For example, in an absolute encoder with a clock of 1 MHz and 2048 pulses, the required time is 1 μs at minimum and 2.048 at maximum.
ms. Therefore, when controlling a motor or the like using an absolute encoder, there is an inconvenience that a required time difference is too large and stable control is difficult. The present invention has been made in view of the above-described problems, and has as its object to provide an absolute encoder in which the capacity of a ROM for absolute position conversion is small and the time required for converting to an absolute position is small. I do.

[0006]

According to the present invention, one absolute position is represented by a predetermined number of bit patterns, and an absolute pattern having a plurality of the predetermined number of bit patterns is formed. And a plurality of detecting elements which are relatively moved with respect to the code plate and which are arranged corresponding to the predetermined number of bit patterns, read the absolute pattern and output a bit pattern signal. detection means, among the plurality of bit patterns corresponding to a plurality of said bit pattern, absolutely to be converted only certain bit pattern signal corresponding to a specific bit pattern on the absolute position
Position conversion means; pattern signal change means for changing the bit pattern signal by calculation until the bit pattern signal read by the detection means becomes the specific bit pattern signal convertible by the absolute position conversion means; Calculating means for calculating position information of the code plate with respect to the detecting means based on the possible bit pattern signal and the number of times of change in the pattern signal changing means. I do.

According to a preferred aspect, the pattern signal changing means changes the bit pattern signal in the pattern arrangement order formed in the absolute pattern.
Further, it is preferable that the absolute position conversion unit includes a determination unit that determines whether or not the bit pattern can be converted based on an arbitrary digit of the bit pattern.

[0008]

The absolute encoder of the present invention detects an absolute signal (hereinafter, simply referred to as "pattern") consisting of a binary sequence from a position corresponding to the absolute pattern. Here, only a plurality of specific patterns can be directly converted to absolute positions by the absolute position conversion means. First, it is determined whether or not the detected pattern can be directly converted to an absolute position by the absolute position conversion means. If conversion is possible, the converted absolute position can be used as the absolute position of the detected position.

Conversely, if conversion is not possible, the detected pattern is used as the initial value of the pattern generating circuit, and patterns shifted one by one in a predetermined direction along the absolute pattern are sequentially generated in synchronization with the clock signal. As described above, this operation is repeated while determining whether each generated pattern can be directly converted into an absolute position by the absolute position conversion means. Eventually, when the generated pattern matches one of the above-described convertible specific patterns, an absolute position corresponding to the convertible pattern is determined, and the absolute position and the number of changes are calculated, for example, to perform addition / subtraction. By such calculations, the absolute position of the detected position can be finally obtained. Note that whether to perform subtraction or addition depends on the shift direction.

As described above, in the absolute encoder of the present invention, the absolute position can not be directly converted at all the detection positions, but can be directly converted only at a specific detection position. Therefore, by appropriately limiting the number of patterns that can be directly subjected to absolute position conversion, RO
The capacity of M can be suppressed to a desired range. Further, the maximum time required to determine the absolute position of the detection position depends on the interval between the patterns whose absolute position can be converted. In other words, if the number of patterns that can be directly converted into absolute positions is appropriately secured, and the intervals are made substantially equal, it is possible to suppress the variation in the time required for converting to absolute positions to a desired range.

[0011]

An embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram schematically showing a configuration of an absolute encoder according to a first embodiment of the present invention. FIG. 2 shows an absolute pattern generated by a generator polynomial of X ⁵ + X ³ + X ⁰ , which is a pattern in which one 0 is inserted in a portion where four 0s are consecutive in a fifth-order M sequence (maximum periodic sequence) pattern. It is. In other words,
The absolute pattern shown in FIG. 2 is a sequence of 2 ⁵ = 32 binary numbers, and 32 reading patterns are possible.

The absolute encoder shown in FIG.
Display means 1 on which the absolute pattern is formed
It has. FIG. 1 shows only a part of the absolute pattern shown in FIG. The sign display means 1
For example, the optical type has a binarized pattern such that light shielding is 1 and transmission is 0. The illustrated absolute encoder further reads the pattern information of the code display means 1 and converts it into a digital signal (binarization).
Detecting means 2 for detecting The detecting means 2 is constituted by five detecting elements such as a photodiode array, and the output of the detecting means 2 is connected to the LSB (least significant bit) side of the shift register 3 via the selector 4.

The MSB of the shift register 3 (the most significant bit )
Data and 2 ¹ of data bits) are input to the exclusive-OR output circuit 5, the output of which is connected to the LSB of the shift register 3 through the selector 4. further,
The parallel output of the shift register 3 is connected to the ROM 7, and the parallel output of the ROM 7 is connected to the subtraction circuit 9. The selector 4 and the shift register 3 are configured to be controlled by the controller 6. On the other hand, the output of the controller 6 is connected to a counter 8, and the parallel output of the counter 8 is connected to a subtraction circuit 9. The subtraction circuit 9 is also configured to be controlled by the controller 6.

The ROM 7 is constructed so that the absolute position conversion can be directly performed on the eight types of 5-bit sequence pattern signals shown in FIG. 3 among the 32 read pattern signals. In other words, the converted data of the eight types of 5-bit sequence pattern signals shown on the left side of the figure in the ROM 7 can be converted into absolute positions, and are converted into the absolute positions shown on the right side of the figure. The shift register 3 can sequentially generate a 5-bit sequence pattern shifted rightward by one bit in FIG. 1 from the detected 5-bit sequence pattern in synchronization with a clock.

The operation of the absolute encoder according to the present embodiment configured as described above will be specifically described. Among the absolute patterns of the code display means 1, the detection means 2
The pattern portion where the five detection elements oppose is read and binarized. Next, the detection data of the detection means 2, that is, the binary sequence of the detection data 10111 from the MSB side is input to the shift register 3 via the selector 4 in accordance with an instruction from the controller 6. More specifically, the data is loaded into the shift register 3 from the MSB side in order from the data on the left side of the detection means 2 in the figure, that is, the MSB side. Thus, the detection data 10111 has been input to the shift register 3 from the right side (MSB side) in the figure.

The detection data 10111 (LSB) output in parallel from the shift register 3 is input to an address bus of the ROM 7, and the controller 6
Clear the counter 8 via -1. In ROM7,
It is determined whether or not the input 5-bit sequence pattern signal can be directly converted to an absolute position. That is, it is checked whether or not the detection data 10111 on the address bus matches the convertible pattern on the left side of FIG. As shown in FIG. 3, the detected data 10111 cannot be absolutely converted in the ROM 7. Therefore, the ROM 7 outputs the absolute position conversion impossible signal L to the controller 6.

The controller 6 which has received the absolute position conversion impossible signal L from the ROM 7 switches the selector 4 via the output line 6-2, and outputs the MSB data of the shift register 3 generated by the exclusive OR output circuit 5 to the data. 2 ¹ data and exclusive ORing of the shift register 3 through the selector 4 L
Input to SB. In this case, since the data of the MSB is 1 and the data of 2 ¹ is 1, the exclusive OR generated by the exclusive OR output circuit 5 is 0. Therefore,
In the shift register 3, the data of the LSB becomes 0,
The remaining data is shifted one by one to the MSB side, and finally becomes 01110 from the MSB side. The controller 6 also outputs a clock signal to the shift register 3 and the counter 8 via the output line 6-3.

As described above, at the first clock, the data generated by the shift register 3 becomes 01110. By repeating the above operation, the shift register 3
Occurs, and changes to 11101, 11011, and 10110 in synchronization with the second and subsequent clocks. This change in the generated data coincides with the pattern change in which the detected data 10111 is shifted rightward in the figure by one bit at a time in the absolute pattern of FIG.

In the above pattern change, the first to third patterns
The generated data 01110, 11101 and 11011 generated by the shift register 3 in synchronization with the second clock cannot be absolutely converted in the ROM 7. Meanwhile, 4
Since the generated data 10110 generated by the shift register 3 in synchronization with the second clock can be converted in absolute position,
The ROM 7 outputs an absolute position convertible signal H to the controller 6. At this time, the ROM 7 outputs the value 01011 (see the fourth row in FIG. 3) of the absolute position information a of the convertible generated data 10110, that is, 11 in decimal, to the subtraction circuit 9 via the data bus.

On the other hand, the counter 8 counts 4 which is the number of times the shift register 3 is shifted. The counted value 4 indicates that the convertible pattern is the detection data 10
This indicates that the position has been shifted to the right by 4 bits from 111, that is, relative position information k with respect to the detected position of the absolute position convertible pattern. The count of the counter 8 is input to the subtraction circuit 19. Upon receiving the absolute position information a = 11 from the ROM 7 and the relative position information k = 4 from the counter 8, the subtraction circuit 9 calculates a−k = 7 and finally obtains the absolute position corresponding to the detection data 10111. . In order to average the required number of pattern changes, it is preferable that the absolute positions corresponding to the specific bit pattern signals that can be converted are at equal intervals as much as possible.

FIG. 6 is a block diagram schematically showing a configuration of an absolute encoder according to a second embodiment of the present invention. The second embodiment has the same configuration as the first embodiment, but basically differs from the first embodiment in that
Reference numeral 17 denotes that the NOR circuit 10 is built in, and that the special absolute position conversion circuit 20 and the selection circuit 11 are additionally provided. 6, the components corresponding to the components in FIG. 1 are denoted by the same reference numerals.

More specifically, the MS of the shift register 3
The two data on the B side are connected to the NOR circuit 10 of the ROM 17. On the other hand, the output of the shift register 3 is connected to the selection circuit 11 via the special absolute position conversion circuit 20. The input of the selection circuit 11 is connected to the parallel output of the subtraction circuit 9. The RO of the second embodiment
Pattern signals that can be converted to absolute positions in M17 and their absolute positions are as shown in FIG. As shown, in the second embodiment, eight types of pattern signals starting with 00 from the MSB side can be converted.

The operation of the absolute encoder according to the second embodiment configured as described above will be specifically described. Of the absolute pattern of the code displaying means 1, a pattern portion where the five detecting elements of the detecting means 2 face is read and binarized. Next, the detection data of the detection means 2,
That is, a binary sequence of the detection data 10111 is input from the MSB side to the shift register 3 via the selector 4 according to an instruction from the controller 6. Specifically, data is loaded into the shift register 3 from the MSB side in order from the data on the left side of the detection means 2 in the figure, that is, on the MSB side. Thus,
This means that the detection data 10111 has been input to the shift register 3 from the right side (MSB side) in the figure.

The detection data 10111 output in parallel from the shift register 3 is input to the address bus of the ROM 17, and the controller 6 clears the counter 8 via the output line 6-1. The two data on the MSB side of the detection data of the address bus of the ROM 17 are both 0,
That is, the output signal of the NOR circuit 10 becomes H only when the pattern starts from 00 on the MSB side, and in other cases, the output signal of the NOR circuit 10 becomes L. in this way,
The output signal H of the NOR circuit 10 is a signal indicating that absolute position conversion is possible in the ROM 17, and the output signal L is a signal indicating that absolute position conversion is not possible.

First address bus detection data 1011
1, the two bits on the MSB side are not 00, so that this detection data 10111 is, as shown in FIG.
In M17, absolute position conversion is not possible. Therefore, the NOR circuit 10 outputs the absolute position conversion impossible signal L to the controller 6. The controller 6 receiving the absolute position conversion impossible signal L from the NOR circuit 10 outputs the output signal 6-
2, the selector 4 is switched via the exclusive OR circuit 5, and the MSB data of the shift register 3 generated by the exclusive OR
The exclusive OR with the ¹ data is input to the LSB of the shift register 3 via the selector 4. In this case, MSB
The data is 1, 2 ¹ data exclusive generated by the exclusive OR output circuit 5 from a 1 is 0.

The controller 6 outputs a clock signal to the shift register 3 and the counter 8 via the output line 6-3. Thus, the generated data generated by the shift register 3 at the first clock is 01110. By repeating the above operation, the shift register 3
Is generated in synchronization with the second and subsequent clocks, 11101, 11011, 10110, and 0110.
0, 11000, 10001, and 00011.
This change in generation data is consistent with the pattern change to shift one bit from the detected data 10111 rightward in the figure in the absolute pattern of FIG.

In the above pattern change, the first to seventh patterns
Generated data 01110, 11101, 11011, 10 generated by the shift register 3 in synchronization with the second clock
Since 110, 01100, 11000, and 10001 are not patterns starting from 00, absolute position conversion is not possible in the ROM 7. On the other hand, since generated data 00011 generated in synchronization with the eighth clock can be absolutely converted in a pattern starting from 00, NO
The R circuit 10 sends an absolute position conversion enable signal H to the controller 6.
Is output. At this time, the ROM 17 outputs the value 01111 (see the fifth row in FIG. 4) of the absolute position information a of the convertible generated data 00011, that is, 15 as a decimal number to the subtraction circuit 9 via the data bus.

On the other hand, the counter 8 counts 8 which is the number of times the shift register 3 is shifted. The counted value 8 indicates that the convertible pattern is the detection data 10
This indicates that the position has been shifted to the right by 8 bits from 111, that is, relative position information k with respect to the detected position of the absolute position convertible pattern 00011. The count of the counter 8 is input to the subtraction circuit 9. ROM1
Receiving the absolute position information a = 15 from the counter 7 and the relative position information k = 8 from the counter 8, the subtraction circuit 9 calculates a−k = 7
Is calculated, and an absolute position corresponding to the detection data 10111 is finally obtained.

By the way, in the case of a rotary type absolute encoder that converts an angle into a digital code,
When the M-sequence pattern is used for the absolute pattern,
The minimum number of reading units is (2 ⁿ -1). For this reason, it is common to insert one 0 in a portion where (n-1) 0s are continuous to form an absolute pattern of 2 ⁿ pulses. As a result, for example, in the two embodiments described above,
00 is stored in the shift register 3 as detected or generated data.
When 000 is input, generated data to be shifted next cannot be generated from the special data 00000. In other words, the data of the shift register 3 is 0
When it reaches 0000, the next generated data is also 0000
It will be 0.

When the data 10000 one pulse before the data 000000 is input to the shift register 3, the next data 00001 is generated instead of the next data 000000. In other words, data 00
000, the absolute position eventually shifts. Thus, the data 0000 is stored in the shift register 3.
When data 10000 before or 0 pulse is input,
A pattern to be generated next cannot be generated in the shift direction. Therefore, in the first embodiment, the two patterns can be subjected to absolute position conversion in the ROM 7. On the other hand, in the second embodiment, data 0
Although 0000 can be absolutely position-converted in the ROM 17, the data 10000 is not a pattern starting with 00 from the MSB side, so that absolute position conversion is not possible.

Therefore, in the second embodiment, the data 10000
A special case absolute position conversion circuit 20 is provided as a means for specially performing absolute position conversion for the absolute position conversion shown in FIG. That is, when the data is 10000, the special case absolute position conversion circuit 20 performs absolute position conversion by a combination circuit or the like as an exception and outputs the corresponding absolute position value 11111 to the selection circuit 11. The reason why the pattern starting with 00 from the MSB side can be absolutely converted is that the data 000000 can always be absolutely converted from the MSB side. In this case, since the data 00000 cannot be created by the pattern generation circuit, the absolute position conversion becomes impossible when the read detection data is 000000.

Therefore, if the data starting with 01 can be converted to an absolute position, it is necessary to perform the absolute position conversion on the detected data 000000 by an exceptional treatment, which complicates the circuit configuration. To avoid the above-described exception handling, the data 1000 is stored in the shift register 3.
When 0 is input or when data 10000 is generated in the shift register 3, the shift direction needs to be reversed. Specifically, the LSB of the shift register 3
Data and it may be input exclusive OR of the 2 ¹ data to the MSB of the shift register 3.

FIG. 7 shows the configuration of a combinational circuit for performing absolute position conversion in the ROM 7 of the first embodiment. In the illustrated combinational circuit, inputs on the left side in the figure are X4, X3, X2, X1, and X0 in order from the top, and inputs on the right side are Y4, Y3, Y2, Y1, Y0, and E in order from the top.
Q. Here, X4 to X0 respectively correspond to data from the MSB side of the convertible pattern shown on the left side in FIG. On the other hand, Y4 to Y0 respectively correspond to data from the MSB side of the binary number sequence indicating the absolute position of the convertible pattern shown on the right side in FIG.
The EQ corresponds to the absolute position conversion enable signal H or the absolute position conversion disable signal L.

In the above embodiment, the present invention has been described by taking the M-sequence absolute pattern as an example.
Multiple bit patterns are aligned in the reading direction
It is clear that it is possible to apply the present invention also absolute pattern that. Further, in the above-described embodiment, the present invention has been described by taking the fifth-order M-sequence absolute pattern as an example. However, it is apparent that the present invention can be applied to higher-order absolute patterns. Further, in the second embodiment, the unique data 0
Although the absolute position can be converted for data 10000 adjacent to one side of 0000, the absolute position can be converted for data 00001 adjacent to the other side, or both adjacent data 10000 and 00001 can be converted.
May be absolute position transformable together. Further, the patterns whose absolute position can be converted need not be at regular intervals, and the smaller the number, the smaller the capacity of the ROM.

[0035]

As described above, in the absolute encoder of the present invention, the capacity of the ROM, which is a look-up table for converting an absolute pattern into an absolute position, can be greatly reduced to 1/4 or less.
The time required for the absolute position conversion can be shortened to about 10 μs. Therefore, according to the present invention, a small and cost-effective absolute encoder can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of an absolute encoder according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an M-sequence absolute pattern.

FIG. 3 is a diagram showing a 5-bit pattern whose absolute position can be converted and corresponding absolute positions in the ROM of FIG. 1;

FIG. 4 is a diagram showing a 5-bit pattern whose absolute position can be converted and corresponding absolute positions in the ROM of FIG. 6;

FIG. 5 is a diagram showing contents of absolute position conversion performed as a special treatment in the second embodiment.

FIG. 6 is a block diagram schematically showing a configuration of an absolute encoder according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a combinational circuit that performs absolute position conversion in the ROM of the first embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Code display means 2 Detecting means 3 Shift register 4 Selector 5 Exclusive OR output circuit 6 Controller 7 ROM 8 Counter 9 Subtraction circuit 10 NOR circuit 11 Selection circuit 20 Special case absolute position conversion circuit

Continuation of the front page (72) Inventor Yuji Yamazaki 471 Nagaodaicho, Sakae-ku, Yokohama-shi, Kanagawa Prefecture Inside Nikon Yokohama Works (56) References JP-A-5-118872 (JP, A) JP-A-5-49165 ( JP, A) JP-A 63-126822 (JP, U) JP-A 3-91914 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01D 5/00-5/64 H03M 7/00

Claims (3)

(57) [Claims] An absolute position is represented by a predetermined number of bit patterns, and a code plate on which an absolute pattern having a plurality of the predetermined number of bit patterns is formed; Detecting means for reading the absolute pattern and outputting a bit pattern signal, the detecting means having a plurality of detecting elements respectively arranged corresponding to a predetermined number of bit patterns, and a plurality of the bit patterns corresponding to a plurality of the bit patterns among the signals, it can be converted by the absolute position converting means and said detecting the bit pattern signal means is read by the absolute position converting means for enabling convert only certain bit pattern signal corresponding to a specific bit pattern on the absolute position Calculating the bit pattern signal until the specific bit pattern signal is obtained.
Includes a pattern signal changing means for changing I, based on the number of changes in the bit pattern signal that can be converted to the pattern signal changing means, and a calculating means for calculating the position information of the code plate with respect to said detecting means Absolute encoder. 2. The absolute encoder according to claim 1, wherein the pattern signal changing unit changes the bit pattern signal in a pattern arrangement order formed in the absolute pattern. 3. The method according to claim 1, wherein the absolute position conversion unit includes a determination unit that determines whether the bit pattern can be converted based on an arbitrary digit of the bit pattern. Absolute encoder.