JP3058371B2 - Absolute encoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder capable of detecting an absolute position.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication Nos. Sho 57-175211 and Sho 60-152916 disclose a one-track type absolute encoder capable of knowing an absolute position with only one track. The code plate of such a one-track type absolute encoder includes two minute regions (called minimum reading units) having different physical properties such as reflectance, transmittance, polarization state, magnetic properties, and magnetization direction. Are arranged in a predetermined relationship, that is, a one-track type absolute pattern is formed.

The one-track type absolute encoder has a plurality of detecting elements arranged at intervals of a minimum reading unit interval along the pattern of the code plate, and detects the pattern by moving relative to the code plate. A detection unit is provided.

[0004]

A conventional one-track type absolute encoder is disclosed in Japanese Patent Application No. 2-96.
As disclosed in Japanese Patent No. 815, detection signals of a plurality of detection elements are sequentially selected and read out.
Therefore, in the case of the pulse number P (2 ^n-1 <P ≦ 2 ⁿ ), at least n clocks are required to read out the detection signals of the n detection elements. For example, in the case of 1024 pulses (2 ¹⁰ ), 1
It took 10 clocks to read the detection signals from the zero detection elements.

The present invention has been made in view of such a situation, and it is an object of the present invention to reduce the time for reading out detection signals of a plurality of detection elements for detecting an absolute pattern without greatly increasing the number of signal lines. With the goal.

[0006]

An absolute encoder according to the present invention comprises a code plate having an absolute pattern for detecting an absolute position, and N (N is 3) arranged along the code plate pattern. Detecting means for detecting the pattern by relatively moving with respect to the code plate, and M detecting means (M is 2 or more and smaller than N) from the N detecting elements. (Integral number), and selecting means (for example, the switch circuit 6 in the embodiment) for sequentially selecting the detection elements and outputting detection signals from the selected M elements.

[0007] N is preferably a multiple of M.

[0008]

In the absolute encoder of the present invention having the above-described structure, M detection elements are sequentially selected from N detection elements, and pattern detection signals are output from the selected M elements. As compared with the above, the detection signal can be read by N / M clock, and the read time can be reduced to 1 / M.

[0009]

FIG. 1 shows the configuration of an embodiment of an absolute encoder according to the present invention. This embodiment is an example in which the present invention is applied to a one-track type absolute encoder, and specifically, is a 2047-pulse linear absolute encoder. The long code plate 2 has a one-track absolute pattern 4 composed of an M-sequence pattern whose generating polynomial is represented by the following equation.

X ¹¹ + x ¹⁰ + x ⁹ + x ⁸ + x ⁷ + x ⁶ + x ⁵ +
^{x 4 + x 3 + x 2} + x 1 + x 0

[0011] 1 constituting the absolute pattern 4
Of the 6 bits, 11 bits indicate the position and 5 bits are for error detection. Sixteen detection elements, that is, photodiodes D1 to D16 are provided at intervals of a minimum reading unit interval along the absolute pattern 4 of the code plate 2 so as to be relatively movable with respect to the code plate 2.

Amplifiers A1 to A16 are provided on the output sides of the photodiodes D1 to D16, respectively, and comparators C1 to C16 are provided on their output sides, respectively.
Is provided. Therefore, the analog detection signals output from the photodiodes D1 to D16 are amplified by the amplifiers A1 to A16, respectively, and then converted into binary signals by the comparators C1 to C16. Output lines of the comparators C1 to C16 are connected to 16 input lines of the switch circuit 6.

The switch circuit 6 has four output lines. The switch circuit 6 operates on the basis of the clock pulse output from the clock pulse generator 8, and four switches, that is, 16 photodiodes D from 16 input lines.
Four bits are sequentially selected from 1 to D16, and binary signals corresponding to the pattern detection signals of the selected four photodiodes are output to four output lines.

The four output lines of the switch circuit 6 are connected to the inputs of the shift registers 10, 12, 14, and 16, respectively. The shift registers 10, 12, 14, and 16 each have four bit positions and output serially input binary signals in parallel. The output lines of the shift registers 10, 12, 14, and 16 are respectively
It is connected to the corresponding address line among the 16 address lines of the ROM 18. The ROM 18 outputs a signal indicating an absolute position according to the input of the 16 address lines.

Next, the operation of the embodiment of FIG. 1 will be described. The analog detection signals output from the photodiodes D1 to D16 are amplified by the amplifiers A1 to A16, respectively, converted into binary signals by the comparators C1 to C16, and supplied to the 16 input lines of the switch circuit 6. Is done.

The switch circuit 6 operates on the basis of the clock pulse output from the clock pulse generator 8, and switches the photodiodes D1, D5,
Binary signals b1, b5, b9 and b13 corresponding to the analog detection signals of D9 and D13 are transferred to shift register 1
0, 12, 14 and 16 and at the second clock pulse, the photodiodes D2, D6, D10
And binary signal b corresponding to the analog detection signal of D14
2, b6, b10 and b14 are stored in shift register 1
0, 12, 14 and 16 and at the third clock pulse, the photodiodes D3, D7, D11
And binary signal b corresponding to the analog detection signal of D15
3, b7, b11 and b15 are stored in shift register 1
0, 12, 14 and 16 and at the fourth clock pulse, the photodiodes D4, D8, D12
And binary signal b corresponding to the analog detection signal of D16
4, b8, b12 and b16 in shift register 1
Feed to inputs 0, 12, 14 and 16.

At this time, the shift register 10 outputs the binary signals b1, b2, b3 and b4 to the corresponding address lines of the ROM 18, and the shift register 12 outputs the binary signals b5, b6, b7 and b8. The shift register 14 outputs the binary signals b9, b10, b11 and b12 to the corresponding address lines of the ROM 18, and the shift register 16 outputs the binary signals b9, b10, b11 and b12 to the corresponding address lines of the ROM 18.
The value signals b13, b14, b15 and b16 are stored in ROM
18 to the corresponding address lines. ROM 18
A signal indicating an absolute position corresponding to the binary signals b1 to b16 as the address input is output.

In the above embodiment, the binary signals corresponding to the detection signals of every fourth photodiode are simultaneously supplied to the shift registers 10, 12, 14, and 16. Not limited to this, for example,
Bit signals corresponding to the detection signals of four adjacent photodiodes are simultaneously output to the shift registers 10, 12, 1
4 and 16. In short, it suffices if the binary signals corresponding to the detection signals of all the photodiodes can be supplied to the corresponding address lines of the ROM 18 in any order.

In the above embodiment, the amplifiers and the comparators are provided on the respective output sides of the photodiodes D1 to D16, and the switch circuit 6 is provided at the subsequent stage. However, the 16 photodiodes D1 to D16 are provided.
The means for sequentially selecting the four detection signals from among the four detection signals may be an analog switch, and the four output signals of the analog switch may be converted into binary signals and supplied to the shift registers 10 to 16.

Although the above embodiment relates to a one-track type absolute encoder, the present invention is not limited to this.
Also applicable to encoders.

Although the above embodiment relates to a linear encoder, the present invention is not limited to this, and can also be applied to a rotary encoder in which tracks are formed along the circumference.

[0022]

As described above, as described above, the absolute
According to the encoder, M detection elements are sequentially selected from N detection elements, and a pattern detection signal is output from the selected M elements. Thus, the time required to read the detection signal can be reduced, and the position can be detected in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an absolute encoder according to the present invention.

[Explanation of symbols]

 D1 to D16 Photodiode 2 Code plate 4 Absolute pattern 6 Switch circuit 8 Clock pulse generator 10, 12, 14, 16 Shift register 18 ROM

Claims (3)

(57) [Claims] 1. A code plate having an absolute pattern for detecting an absolute position, and N (N is an integer) arranged along the code plate pattern.
Detecting means for detecting the pattern by relatively moving with respect to the code plate and having three or more positive integers, and M (M is 2 or more and N Selecting means for sequentially selecting the detection elements by smaller positive integers and outputting detection signals from the selected M elements. 2. The absolute encoder according to claim 1, wherein said N is a multiple of said M. 3. The absolute encoder according to claim 1, wherein the pattern is a one-track type absolute pattern.