JP3239696B2 - Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path switching type delay circuit for switching a delay time by selecting one path from a plurality of paths having different delay times.

[0002]

2. Description of the Related Art Conventionally, this type of delay circuit is configured as shown in FIG. This delay circuit connects a first path A1 to A4 and a second path B1 to B4 of each stage to a selector 11
To 14 and finally connect the paths A4 and B4 at the last stage.
Is connected to the input terminal of the OR gate 15.

The input terminal of the selector 11 is connected to the input terminal IN, and the output terminal of the OR gate 15 is connected to the output terminal OUT. Also, the first paths A1 to A4 have a delay time T1.
And 2 ⁿ (n is an integer) delay gates D (T1), and the second paths B1 to B4 have a delay time T2 (T1> T2) of 2
^{It has n} (n is an integer) delay gates D (T2).

In this example, the numbers of gates of paths A1 to A4 are 1, 2, 1, and 2, respectively, and the numbers of gates of paths B1 to B4 are 1, 2, 0, and 0, respectively.

In the configuration shown in FIG. 4, the signal supplied to the input terminal IN is selectively led out to either the path A1 or the path B1 by the first-stage selector 11, and is inputted to the second-stage selector 12. You. Delay gate D of path A1
The delay time T1 of (T1) is equal to the delay gate D of the path B.
It is longer than the delay time T2 of (T2). Therefore, a delay time difference between the delay gate D (T1) and the delay gate D (T2) can be generated in the output of the second-stage selector 12 in accordance with the selection of the paths A1 and B1.

A signal passing through one of the paths A1 and B1 is selectively led out to one of the paths A2 and B2 by the second-stage selector 12, and is input to the third-stage selector 13. The delay time T1 × 2 of the two-stage delay gate D (T1) of the path A2 is equal to the two-stage delay gate D of the path B2.
It is longer than the delay time T2 × 2 of (T2). Therefore, 3
The outputs of the selectors 13 of the first stage include delay gates D (T1) and D (T1) for one to three stages including the delay difference between the outputs of the selectors 12 of the second stage according to the selection of the paths A2 and B2. T
The delay time difference from 2) can be caused.

The signal passed through either of the paths A2 and B2 is selectively derived by the selector 13 at the third stage to either the path A3 or the path B3 and input to the selector 14 at the fourth stage. Path A3 includes a delay gate D (T1), but path B3 does not include a delay gate. For this reason,
The output of the fourth-stage selector 14 includes delay gates D (T1) for 1 to 7 stages including the delay difference between the outputs of the second and third-stage selectors 12 and 13 in accordance with the selection of the paths A3 and B3. And a delay time difference between the delay gate D (T2) and the delay gate D (T2).

The signal passed through one of the paths A3 and B3 is selectively derived to either the path A4 or the path B4 by the fourth-stage selector 14, and is input to the OR gate 15. The path A4 includes a two-stage delay gate D (T1), but the path B3 does not include a delay gate. Therefore, the output of the OR gate 15 is connected to the selector 1 of the second to fourth stages.
A delay time difference between the delay gate D (T1) and the delay gate D (T2) for 1 to 15 stages including the delay difference of the outputs 2 to 14 can be generated.

Therefore, the delay circuit having the above-described configuration can appropriately select the paths A1 to A4 and B1 to B4 to transmit the signal supplied to the input terminal IN to the delay gate D (1 to 15 stages). T1) and a delay time difference between the delay gate D (T2) and the output from the output terminal OUT.

By the way, since the delay circuit shown in FIG. 4 is a four-stage path switching system, if the delay time T1 of the delay gate D (T1) is set to 1, the paths A1, The delay time difference of B1 is 1/4, and the delay time difference of paths A2 and B2 selected by the second-stage selector 7 is 1
/ 2, paths A3, B3 selected by the third-stage selector 13
Is 1 and the delay time difference between the paths A4 and B4 selected by the selector 14 in the fourth and fourth stages is 2.

The relationship between the delay time of the delay gate D (T1) and the delay time of the delay gate D (T2) is expressed by the delay gate D (T
1) and D (T2) are generalized as n, and the delay gate D (T2) becomes a delay gate D (T2).
It has a delay time of (1-1 / 2 ⁿ ) with respect to the delay time of 1). The delay gate D (T1) and the delay gate D
The delay time difference of (T2) becomes the resolution of the delay circuit.

As described above, in the conventional delay circuit shown in FIG. 4, the paths A1 to A4 and the paths B
By performing selection control to arbitrarily combine 1 to B4,
The delay time can be varied programmably.

The above operation is performed by the delay gate D (T
In some cases, the delay time T2 of the delay gate D (T2) is larger than the delay time T1 of 1). If the relationship between the delay times of the delay gate D (T1) and the delay gate D (T2) at this time is generalized in the same manner as described above, the delay gate D (T
2) is (1+) with respect to the delay time of the delay gate D (T1).
1/2 ⁿ ).

However, when the conventional delay circuit based on the path switching method is made monolithic, a change in gate delay due to a temperature change and a variation in delay time between manufacturing lots occur. For this reason,
It was impossible to obtain a delay time as designed, and it was extremely difficult to realize a delay circuit requiring accuracy. Also, once monolithic, it was impossible to change the resolution.

[0015]

In a conventional delay circuit based on a path switching method, a change in gate delay due to a temperature change and a variation in delay time between manufacturing lots occur in monolithic implementation. Therefore, it is extremely difficult to realize a highly accurate delay circuit. Also, once monolithic, it was impossible to change the resolution.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a delay circuit capable of freely setting a resolution and setting a highly accurate delay time by compensating for manufacturing and temperature variations.

[0017]

In order to achieve this object, the present invention is directed to a plurality of circuits each having 2 ⁿ (where n is an integer) the same number of variable delay gates D in series in each stage. Paths A11 to A14, B11 to B1 of a plurality of stages
4. a delay processing unit 21 including path selection units 211 to 215 for selectively connecting the paths of the plurality of stages and a plurality of paths for each stage and setting a delay time; The same variable delay gates D as those used for the paths of the system are connected in series, arranged in close proximity to the paths, and delay time generating means 221 and 231, which are delayed by one cycle through the input clocks f0 and f1. Phase error detecting means 222, 232 for detecting the input / output phase error of the delay time generating means 221, 231; control signal generating means for generating the delay time control signals CTR1, CTR2 from the detection results of the phase error detecting means 222, 232 223, 233, the delay time control signal CTR
1, a plurality of delay time compensators 22 and 23 for simultaneously controlling the delay time of the variable delay gate D used for the path of the corresponding system together with the internal variable delay gate D by the CTR 2;
From the reference clock f0, the plurality of delay time compensators 22,
And a clock generation unit 24 that generates each of the input clocks f0 and f1 with a fixed frequency relationship. An arbitrary delay time is set by switching the path of the delay processing unit 21. To do.

[0018]

In the delay circuit according to the present invention, the delay processing section 21
The same variable delay gate D is used for the paths A11 to A14 and B11 to B14 of the respective systems, and for example, the paths A11 to A of the A system are used.
A variable delay gate D, which is the same as the variable delay gate D used in A14, is connected in series by the number necessary to delay the reference clock f0 by one cycle, and the delay time generation means 22
1, a delay time control signal CTR1 for determining the amount of phase shift by comparing the phase of the reference clock f0 with the output of the delay time generating means 221 and generating a delay time control signal CTR1 for correcting the shift is generated. By this control signal, the variable delay gate D of the delay time generation means 221 and the paths A11 to A
Fourteen variable delay gates D are controlled simultaneously.

The clock generating means 24 generates a clock f1 having a fixed frequency relationship from the reference clock f0.
A variable delay gate D, which is the same as the variable delay gate D used for the paths B11 to B14 of the B system, is connected in series as delay time generation means 231 and the paths B11 to B14
14, the clock f1 and the delay time generating means 2
31 to determine the amount of phase shift, and to generate a delay time control signal CTR2 for correcting the shift. The control signal is used to control the variable delay gate D of the delay time generator 231 and the paths B11 to B14. The variable delay gate D is controlled simultaneously.

The delay time generation means 221 and the paths A11 to A
14. Since the delay time generation means 231 and the paths B11 to B14 are arranged close to each other, they have the same degree of variation, and have the same delay time control signals CTR1 and CTR.
Variable delay gate D of path of corresponding system using TR2
, It is possible to control and compensate for variations in delay time. Further, the difference between the delay time of the variable delay gate D controlled by the delay time compensator 22 and the delay time of the variable delay gate D controlled by the delay time compensator 23 is compensated for even if there is variation, so that the resolution is improved. Compensated.

By setting the clock f1 generated by the clock generating means 24 to an arbitrary frequency,
The delay time of the variable delay gate D controlled by the delay time compensator 23 can be changed. That is, the resolution of the delay circuit formed by the difference between the delay time and the delay time of the variable delay gate D controlled by the delay time compensator 23 can be set arbitrarily.

[0022]

Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a configuration of a delay circuit based on a four-stage path switching system according to the present invention. The delay circuit includes a delay processing unit 21 that performs a delay process on an input signal by switching a path between a system A and a system B, and a first delay time that compensates for fluctuations and variations in delay time of a delay gate of the path of the system A. A compensating unit 22, a second delay time compensating unit 23 for compensating for variations and variations in the delay time of the delay gate of the path of the B system, and determining a delay time of the path of the B system with respect to the path of the A system. A PLL (phase locked loop) circuit 24 is provided.

The delay processing unit 21 includes a first path A1 of each stage.
1 to A14 and the second paths B11 to B14
1 to 214, the path A1 at the final stage
4, B14 is connected to the input terminal of the OR gate 215.

The input terminal of the selector 211 is connected to the input terminal IN, and the output terminal of the OR gate 215 is connected to the output terminal OUT.
Connected to. Also, paths A11 and B11, A12 and B
12, 1 for A13 and B13, 1 for A14 and B14
, 2, 4, and 8 variable delay gates D (all having the same structure) are interposed in series.

The first delay time compensator 22 includes the same number of variable delay gates D as the variable delay gates D used for the paths A11 to A14 of the A system, the number of which is required to delay the reference clock f0 by one cycle. The delay time generation circuit 221 connected in series, the reference clock f0 and the delay time generation circuit 221
And a low-pass filter (LPF) 223 that passes a low-frequency component of the output of the phase comparator 222 to generate a DC voltage signal. And

The output of the low-pass filter 223 is supplied as a delay time control signal CTR1 to each variable delay gate D of the delay time generation circuit 221.
To the variable delay gates D to A14. The delay time generation circuit 221 is a path A1 of the A system of the delay processing unit 21.
1 to A14.

Similarly, the second delay time compensator 23
A delay time generation circuit 231 in which the same variable delay gates D as the variable delay gates D used for the paths B11 to B14 of the system are connected in series by the number necessary to delay the reference clock f1 by one cycle; A phase comparator (PD) 232 for comparing the phase of the reference clock f1 'delayed by the delay time generation circuit 231 with a reference clock f1', and a low-frequency component of the output of the phase comparator 232 is passed to generate a DC voltage signal. A low-pass filter (LPF) 233.

The output of the low-pass filter 233 is supplied to each variable delay gate D of the delay time generation circuit 231 as a delay time control signal CTR2, and at the same time, the B system path B11
To the variable delay gates D to B14. The delay time generation circuit 231 is a path B1 of the B system of the delay processing unit 21.
1 to B14.

The number of variable delay gates of the delay time generation circuit 221 of the first delay time compensation unit 22 and the number of variable delay gates of the delay time generation circuit 231 of the second delay time compensation unit 23 are set to be the same.

The PLL circuit 24 generates the reference clock f1 from the reference clock f0, and is specifically configured as shown in FIG.

In FIG. 2, the reference clock f0 is frequency-divided by the frequency divider (1 / X) 241 by X, and the output clock f1 is frequency-divided by the frequency divider (1 / Y) 242 by the Y frequency divider. PD) 243. This phase comparator 2
Reference numeral 43 compares the phases of both inputs and outputs a phase error signal. This phase error signal is a low-pass filter (L
PF) 244, after being converted into a DC voltage signal,
The signal is amplified at 45 and supplied to a voltage controlled oscillator (VCO) 246 as a voltage control signal.

The voltage controlled oscillator 246 generates a clock f1 having a frequency corresponding to the control voltage signal. The clock f1 is supplied to the above-described frequency divider 242 and has a second delay time as an output clock f1. Compensation unit 2
3 is supplied.

Next, the operation of the above configuration will be described. First, in the PLL circuit 24, the input reference clock f 0 is frequency-divided by X in the frequency divider 241, and the phase of the signal obtained by frequency-dividing the output clock f 1 in Y by the frequency divider 242 is compared in the phase comparator 243. Here, nothing is output when both phases match, but if they are out of phase, a phase error signal corresponding to the shift is output.

This phase error signal is supplied to a low-pass filter 24.
At 4, only the low frequency portion is extracted and converted to a DC voltage signal. This signal is amplified by the amplifier 245, and the voltage controlled oscillator 246 is oscillated by the amplified signal. The oscillation frequency of the voltage controlled oscillator 246 is the output clock f1 of the PLL circuit 24. As described above, the output clock f <b> 1 is frequency-divided by the frequency divider 242 and supplied to the phase comparator 243.

By the above operation, the input / output of the PLL circuit 24 is controlled so that f0 / X = f1 / Y (1). Therefore, the output f1 of the PLL circuit 24 is fixed at a frequency Y / X times that of the input f0.

On the other hand, the delay processing section 21 has substantially the same configuration as that of the conventional delay circuit shown in FIG. 4, but the delay time of each stage is controlled by the first delay time compensating section 22 until the last stage. The delay processing is performed using the delay time difference between D and the variable delay gate D controlled by the second delay time compensator 23.

Next, the delay time generation circuit 221 of the first delay time compensator 22 is designed to have a delay time of one cycle of the reference clock f0. Further, the delay time generation circuit 231 of the second delay time compensator 23 is designed to have a delay time of one cycle of the clock f1 obtained by converting the reference clock f0 by the PLL circuit 24.

In practice, the delay time of the delay time generation circuits 221 and 231 varies with the design value depending on the temperature.
It needs to be compensated because it varies. Therefore, the reference clock f0 is input to the delay time generation circuit
The output and input phases are delayed by a period
Compare at 22. Here, if the phases match, the phase comparator 222 does not output anything, but if the phases are shifted, a phase error signal corresponding to the shift to the low-pass filter 223 is output.

The low-pass filter 223 is connected to the phase comparator 2
22 is converted into a DC voltage signal by passing only the low frequency portion. This signal controls each variable delay gate D of the delay time generation circuit 221 as a delay time control signal CTR1. That is, the delay time generation circuit 221
The delay time of each gate is determined by the delay time control signal C
The delay time is controlled by TR1 and is adjusted to a delay time of one cycle of the reference clock f0 as a whole.

This delay time generation circuit 221 is arranged in the vicinity of the paths A11 to A14 of the A system of the delay processing unit 21, and the delay time control signal CTR1 output from the low-pass filter 223 is supplied to each of the variable delay gates of the paths A11 to A14. Distribute to D. In this case, since the delay time generation circuit 221 and the paths A11 to A14 are arranged close to each other, their variations are substantially the same.

Therefore, by controlling the variable delay gates D of the paths A11 to A14 using the same delay time control signal CTR1, the delay time can always be adjusted to the design value irrespective of temperature changes and variations.

Similarly, also in the second delay time compensating section 23, the clock f1 is input to the delay time generating circuit 231 and delayed by one cycle, and the output and input phases are compared by the phase comparator 232. A phase error signal is generated, converted into a DC voltage signal by a low-pass filter 233, and each variable delay gate D of the delay time generation circuit 231 is controlled as a delay time control signal CTR2.

That is, the delay time of the delay time generation circuit 231 is determined by the gate delay time of the delay time control signal CTR2.
And is adjusted to a delay time of one cycle of the clock f1 as a whole.

The delay time generation circuit 231 is arranged near the B-system paths B11 to B14, and the low-pass filter 2
33 to the delay time control signal CTR2
It distributes and supplies the variable delay gates D11 to B14. In this case, the delay time generation circuit 231 and the paths B11 to B14
Are arranged close to each other, and the variation is substantially the same.

Therefore, by controlling the variable delay gates D of the paths B11 to B14 using the same delay time control signal CTR2, the delay time can always be adjusted to the design value regardless of the temperature change and variation.

The resolution of this delay circuit is determined by the delay time of the variable delay gate D for one stage controlled by the first delay time compensator 22 and the variable delay for one stage controlled by the second delay time compensator 23. This is the difference between the delay times of the delay gate D. Since each is compensated for manufacturing and temperature variations, the resolution is compensated.

Here, the first and second delay time compensating units 2
Assuming that the number of stages of the variable delay gates D of 2, 23 is N, the first
The delay time of the variable delay gate D for one stage of the delay time compensator 22 is (1 / f0 * 1 / N), and the delay time of the variable delay gate D for one stage of the second delay time compensator 23 Is (1 / f1 * 1 / N). From this, the resolution φ of the delay circuit is obtained from the equation (1) as follows: φ = (1 / f0 * 1 / N) − (1 / f1 * 1 / N) = (1−X / Y) * (1 / f0 * 1 / N) (2) Therefore, the frequency divider 24 of the PLL 24
The resolution can be freely changed by arbitrarily setting 1, 242.

In order to delay the signal input to the delay processing section 21 for an arbitrary time, the selectors 211 to 2 of each stage
At 14, appropriate paths A11 to A14 and B11 to B14 are selected. The delay time of the variable delay gate D at each stage is automatically adjusted by the delay time control signals CTR1 and CTR2. Therefore, the output signal of the delay processing unit 21 is a signal delayed with extremely high accuracy.

Therefore, the delay circuit having the above configuration has
The resolution can be freely set, and a highly accurate delay time can be set by compensating for manufacturing and temperature variations. In the embodiment shown in FIG. 1, the number of selector stages of the delay processing unit 21 and the number of variable delay gates in each stage can be increased or decreased as necessary.

FIG. 3 shows the configuration of another embodiment of the delay circuit according to the present invention. In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The delay circuit shown in FIG. 3 differs from the delay circuit shown in FIG. That is, in the delay processing unit 21, the paths A11 to A11
A14, B11 to B14 are selected with a two-input two-output structure (2
Selectors 216 to 21 for outputting one of two input terminals)
A selector 219 having an 8 and 1 input and 1 output structure is used.

In FIG. 3, an input signal supplied to an input terminal IN is directly input to a selector 216 through both paths A11 and B11, and one of the signals is selected and output to both paths A12 and B12. Is done.

Similarly, the transmission signals on the paths A12 and B12 are input to the selector 217, and one of the signals is selected and output to both the paths A13 and B13, and the path A1
3 and B13 are input to the selector 218, one of the signals is selected and output to both of the paths A14 and B14, and the transmission signal of the paths A14 and B14 is input to the selector 219 and one of the signals is input to the selector 219. The signal is selected and output to the output terminal OUT.

Even in such a configuration, the variable delay gates D of the paths A11 to A14 are exactly the same as in the embodiment shown in FIG.
Is compensated by the delay time control signal CTR1 from the first delay time compensator 22 and the dispersion of the variable delay gates D of the paths B11 to B14 is compensated by the delay time control signal CTR2 from the second delay time compensator 23. be able to. In addition, the delay time difference of one stage of the variable delay gate D of the delay time generation circuits 221 and 231 which is the resolution of the delay circuit can be compensated for manufacturing and temperature variations.

In the above embodiment, as in the previous embodiment, the number of selector stages of the delay processing section 21 and the number of variable delay gates in each stage can be increased or decreased as necessary. Also,
In each embodiment, the number of paths is two. However, the number of paths may be more. In this case, a delay time compensator is provided for each system, and the input clock of each delay time compensator is
A similar effect can be obtained if the circuit is configured to generate from a reference clock. It goes without saying that various other modifications are included in the present invention.

[0055]

As described above, according to the present invention, it is possible to provide a delay circuit capable of freely setting the resolution, compensating for manufacturing and temperature variations, and generating a highly accurate delay time. .

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a delay circuit according to the present invention.

FIG. 2 is a block circuit diagram showing a specific configuration of the PLL circuit shown in FIG.

FIG. 3 is a block circuit diagram showing a configuration of another embodiment of the delay circuit according to the present invention.

FIG. 4 is a block circuit diagram showing a configuration of a delay circuit based on a conventional path switching method.

[Explanation of symbols]

 Reference numerals 11 to 14 selector 15 OR gate 21 delay processing section 211 to 214 selector 215 OR gate 216 to 219 selector 22 first delay time compensation section 221 delay time generation circuit 222 phase comparator (PD) 223 low-pass filter (LPF) 23 2 delay time compensator 231 delay time generator 232 phase comparator (PD) 233 low-pass filter (LPF) 24 PLL circuit 241, 242 divider 243 phase comparator (PD) 244 low-pass filter (LPF) 245 amplifier 246 voltage Control oscillator (VCO) IN input terminal OUT output terminal f0, f0 ', f1, f1' Clock A1 to A4, B1 to B4 path A11 to A14, B11 to B14 path

Claims (4)

(57) [Claims] 1. A 2 ⁿ (where, n is an integer) in each stage in the path of a plurality of systems of a plurality of stages that each system has the same number of the same variable delay gate (D) in series with one another (A11, A12, A13, A14, B11, B12, B1
3, B14), a path selecting means (211, 212, 2) for selectively connecting a plurality of paths of the plurality of stages for each stage and setting a delay time.
13,214,215), and the same variable delay gate (D) that is provided for each path system and is used for the path of the corresponding system, and connected in series, A delay time generating means (221,231) which is arranged close to the path and is delayed by one cycle through the input clock (f0, f1);
Phase error detecting means (222, 2
32), control signal generating means (223, 233) for generating delay time control signals (CTR1, CTR2) from the detection results of the phase error detecting means (222, 232), and the delay time control signals (CTR1, CT
R2) and a plurality of delay time compensators (22, 23) that simultaneously control the delay time of the variable delay gate (D) used for the path of the corresponding system together with the internal variable delay gate (D), and the reference clock (f0) From the plurality of delay time compensation units (22, 2
3) a clock generation unit (24) that generates the input clocks (f0, f1) with a fixed frequency relationship, and sets an arbitrary delay time by switching the path selection of the delay processing unit (21). A delay circuit, characterized in that: 2. The method according to claim 1, wherein said path selecting means (2)
11,212,213,214) are delay circuits characterized by being selectors. 3. The delay circuit according to claim 1, wherein said phase error detecting means (222, 232) is a phase comparator, and said control signal generating means (223, 233) is a low-pass filter. 4. The clock generation unit according to claim 1,
(24) is a first frequency divider (24) for dividing the frequency of the reference clock (f0).
1) and a second frequency divider (242) for dividing the output clock (f1)
A phase comparator (243) for comparing the phases of the outputs of the first and second frequency dividers to obtain a phase error signal; and generating the output clock (f1). And a clock generation means (244, 245, 246) for controlling the frequency so that the output phase error signal disappears, wherein the frequency is controlled by the frequency division ratio of the first and second frequency dividers (241, 242). A delay circuit, wherein a delay time resolution of a delay processing section (21) is determined.