JP3237698B2 - Feedback control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a feedback control device for controlling a control target such as an inverter and a converter.

[0002]

2. Description of the Related Art For example, a feedback control device may be configured as shown in FIG. 1 for an uninterruptible power supply (UPS). In FIG. 1, an inverter 2 is provided at an output stage of a DC power supply 1 including a rectifier circuit, a storage battery, etc., and reactors (inductances) Lu, Lv, Lw of a low-pass filter, and an insulating transformer including primary and secondary windings and a core. 3. Capacitors Cu, Cv, Cw for a low-pass filter and a load 4 are sequentially provided. The inverter 2 has a function of converting DC into AC and controlling the voltage of the load 4 to have a constant amplitude and a sine wave.

As shown in FIG. 2, an inverter 2 has a controllable semiconductor switch Q1, Q2, Q3, Q4, such as a transistor or an IGBT, between a pair of DC power supply lines 1a and 1b.
Q5 and Q6 are connected in a three-phase bridge, and the switches Q1 to Q6
And diodes D1 to D6 are connected in parallel.
The switch Q1-Q6 are controlled by the PWM pulses in a manner well known 3-phase output lines 2u, is intended to obtain 2v, 2w to a three-phase AC voltage inverter output voltage v _iu consisting, v _iv, the v _iw. The control terminals of the switches Q1 to Q6 are shown in FIG.
Is connected to the PWM pulse forming circuit 5 shown in FIG.

[0004] The PWM pulse forming circuit 5 is provided with a u-phase, v-phase and w-phase inverter operation amount v supplied from a control circuit 6.
_{Based on ru} (n), v _rv (n), and v _rw (n), a well-known PWM pulse for controlling on / off of the switches Q1 to Q6 is formed. Note that the inverter operation amount is single-phase or 1-phase.
Indicated by v _r or v _r (n) when describing the only phase component, u phase of the three-phase circuit, v-phase, is shown indexed u, v, and w when showing an inverter operation amount of the w-phase I have. The sampling time is indicated by (n). FIG.
Is a comparator CP for one phase of the PWM pulse forming circuit 5
And a triangular wave generator TW and a distribution circuit DR. The comparator CP compares the inverter operation amount v _ru (n) with the triangular wave voltage Vt of the triangular wave voltage generator TW, as shown in FIG. 9A, and generates a PWM pulse shown in FIG. 9B.
The distribution circuit DR distributes the PWM pulses obtained from the comparator CP and another phase comparator (not shown) to the switches Q1 to Q6. The switches Q1 and Q2, the switches Q3 and Q4, and the switches Q5 and Q6 are driven so as not to be simultaneously turned on, as is well known. The triangular wave voltage Vt is a repetition frequency (for example, 20 Hz) sufficiently higher than the frequency (for example, 50 Hz) of the inverter output AC voltage.
kHz).

[0005] Reactors (inductances) Lu, Lv
, Lw are the ON / OFF states of the switches Q1 to Q6 of the inverter 2.
In order to attenuate a harmonic component generated by turning off, the inverter 2 and the primary winding of the transformer 3 are connected in series to the lines 2u, 2v, and 2w.

For example, CT or hoe
Current detectors 7u and 7w composed of
Have been combined. Current detectors 7u and 7w are controlled
Quantity i _iAs the inverter output current i_iu, I_iwDetect
Things. A / D connected to current detectors 7u, 7w
The converter 8 has a sampling period (sampling time interval).
T_sAnd the analog detection current i_iu, I_iwSample
Switch and sample extracted by this switch
To a digital signal.
Inverter current i as the state quantity of_iu(N-1, m),
And i_iw(N-1, m) is output. N is the current time
Point, n-1 is one sampling period T_sPrevious time, (n-
1, m) is mT from time point n-1_sIndicates when time has advanced
You. n−1, time difference between time m and time n (1−m) T_s
Is the time required for calculation by the control circuit.
Td. Here, m is the time between the time point n-1 and the time point n.
It is a coefficient that satisfies 0 <m <1 for representing a time point.

[0007] Capacitors Cu, Cv, and Cw as filters for removing harmonic components generated by turning on and off the switches Q1 to Q6 of the inverter 2 are a three-phase power supply between the secondary winding of the transformer 3 and the load 4. Y connection is made between lines 9u, 9v, and 9w. Therefore, capacitors Cu, Cv,
Cw will be connected in parallel to the 3-phase load 4, capacitors Cu, Cv, the voltage of Cw v _cu, v _cv, v
_cw corresponds to each phase voltage of the load 4.

Current detectors 10u and 10w are provided to obtain the currents of the capacitors Cu and Cw as the state quantities _ic (n) at the time point n for compensating for the dead time. If the current of the load 4 u-phase and w-phase i _Lu, and i _Lw, i _cu between capacitor current i _cu, i _cw and the inverter output current i _iu, and i _iw load current i _Lu, and i _LW = I _iu -i _Lu and i _cw =
i _iw −i _Lw (when the excitation current of the transformer 3 is ignored). A / connected to the current detectors 10u and 10w
The D converter 11 _outputs the currents i _cu , i at the sampling period T _s.
a switch for sampling _cw and a circuit for converting a sample extracted by the switch into a digital signal,
It outputs digital amounts of capacitor currents _icu (n-1, m) and _icw (n-1, m). (N-1, m) in the capacitor current has the same meaning as (n-1, m) described in the inverter current.

[0009] control variable v _c as the load 4 voltage or capacitor Cu, the voltage v _cu of Cw, isolation transformer 12 and the A / D converter 13 to detect the v _cw is provided.
A / D converter 13 includes a sampling period T _s in the load voltage v _cu, v a switch for sampling the _cw, and a circuit for converting the samples extracted with the switch to digital, the load voltage v _cu (n-1 , _M ), v _cw (n−1,
m) is output. (N-1, m) at this load voltage
Has the same meaning as (n-1, m) in the inverter current described above.

The control circuit 6 controls the inverter output current i
_iu (n-1, m), i _iw (n-1, m), capacitor current i _cu (n-1, m), _ic w (n-1, m) and load voltage v _cu (n-1, m) m), v _cw (n−1, m), and manipulated _variables v _ru , v _rv , for performing feedback control of the inverter 2.
v _rw is created. In an embodiment of the present invention described later, the control circuit 6 controls the voltage v of the load 4.
_The inverter 2 is controlled so that _cu , _vcv , and _vcw become constant voltages in a sine wave _shape with little distortion, and prevent the transformer 3 from being biased due to the offset of the control system (such as the offset of the current detector).

FIG. 4 shows details of the control circuit 6 of FIG. The control circuit 6 has an output voltage command value generator 20. The output voltage command value generator 20 is a voltage command value _Vcu ^* (n) and _vcw composed of a sine wave voltage having a predetermined amplitude to be a target value (reference value) of the voltages _vcu and _vcw of the load 4 in FIG. ^* (N)
At a constant sampling period T _s .

The subtractors 21u and 21w constituting the u-phase and w-phase voltage controllers are provided with voltage command values _vcu ^* (n) and _vcw.
^* (N) load voltage detection value indicating a control amount v _c from v _cu (n
-1, m) and v _cw (n-1, m) are subtracted. Coefficient unit (multiplier) 22 that can be considered as a part of the voltage controller
u and 22w multiply the outputs of the subtracters 21u and 21w by a predetermined coefficient K _pv indicating a gain.

LP as transformer bias excitation preventing means 24
F (low-pass filters) 24u and 24w are A /
The inverter current i _iu (n−1,
m) and i _iw (n−1, m) to output DC components i _oou (n) and i _oow (n) of the inverter output current. The DC component of only one phase is indicated by i _oo (n).

A subtractor 23 for forming a current command value
u and 23w are LP from the outputs of the coefficient units 22u and 22w.
F24u, and outputs the current command value by subtracting the output of 24w u-phase and w-phase i _cu ^* (n) and i _cw ^* (n). The current command values obtained from the subtracters 23u and 23w can be expressed by the following equations. _icu ^* (n) = _Kpv { _vcu ^* (n) _-vcu (n-1)}
−i _oou (n) i _cw ^* (n) = K _pv {v _cw ^* (n) −v _cw (n−1)}
−i _oow (n) Note that, if only one phase is represented without the suffixes indicating the u phase and the w phase, the result is as follows. ^{_{i c * (n) = K}} pv {v c * (n) -v c (n-1)}
−i _oo (n)

U-phase and w-phase current controllers 25u, 25w
Is the current command value i _cu obtained from the subtracters 23u and 23w.
^* (N), _icw ^* (n) and u-phase and w-phase state quantities _icu (n-1, m), i obtained from the A / D converter 11 in FIG.
_{Based on cw} (n-1, m), u-phase and w-phase inverter operation amounts v _ru (n) and v _rw (n) shown in the following equations are created. v _ru (n) = {P / (K _n T _s )} i _cu ^* (n) −i
_{Du '(n) -i cu'} (n)} v rw (n) = {P / (K n T s)} {i cw * (n) -i
Here _{Dw '(n) -i cw'} (n)}, P is an arbitrary constant, nominal value of K _n is K _inv / L (where, K _inv the main circuit of the inverter 2 in FIG. 1 to the load 4 (L is a constant indicating the inductance of the control target.), _Icu ^* (n)
And _icw ^* (n) are the state quantities _icu (n) and _icw at the time point n.
The command values (n), i _Du ′ (n) and i _Dw ′ (n) are estimated disturbance values in the control object, i _cu ′ (n) and _ic w ′
(N) is _icu (n-1, m) = _iiu (n-1, m) _-iLu (n-
1, m) i _cw (n−1, m) = i _iw (n−1, m) −i _Lw (n−
1, m) are the values of the state quantities of the u-phase and the w-phase predicted at the time point n at the time point (n-1, m). The inverter operation amount v _r (n) for only one phase without the suffixes indicating the u phase and the w phase can be expressed by the following equation. _{v r (n) = {P} / (K n T s)} {i c * (n) -i
_{D '(n) -i c'} (n)}

1 and 4, the v-phase current and voltage detecting means and the current detector are not provided. Instead, as shown in FIG. 4, a subtractor 26 for generating the v-phase manipulated variable v _ru (n) is provided. Note that the control target in FIG. 1 is a three-phase non-grounded system, and the sum of the currents of each part is zero. Therefore, the v phase can be obtained from the u phase and the w phase. Subtractor 2
_{Reference numeral 6} outputs the v-phase operation amount v _rv (n) by subtracting the u-phase operation amount v _ru (n) and the w-phase operation amount v _rw (n). The inverter operation amount for only one phase output from the control circuit 6 is represented by v _r (n).

FIG. 5 equivalently shows only a main circuit from the inverter 2 to the load 4 in FIG. Controlled object 27, the output or controlled variable v _c, when the input or manipulated variable and v _r, are those that can be represented by the following equation.

[0018]

(Equation 2)

In the above equation, i _i is a state quantity of the controlled object, i _L is an arbitrary disturbance, K _inv is a gain, and C and L are constants indicating a capacitance and an inductance of the controlled object. The correspondence between these and FIG. 1 is shown, i _i is i _iu ,
i _L corresponds to i _Lu , i _Lw corresponds to i _iw , K _inv corresponds to the amplification (gain) of the inverter 2, and C and L correspond to Lu.
, Lv, Lw and Cu, Cv, Cw.

[0020] In FIG. 5, the amplifier i.e. a coefficient unit 28 is intended to obtain a K _inv v _r in equation (2). Subtractor 2
9 are those obtained formula (2) to _{(K inv v r -v c)} . The arithmetic circuit 30 performs 1 / (LS) arithmetic processing. S denotes a Laplace operator, since 1 / S represents an integration process, the arithmetic circuit 30 is K _inv v _r a -v _c integrated, whereas 1 / L multiplication and outputting the state quantity i _i I do. The subtractor 31 calculates i _i −i _L of the equation (1), and
And outputs a state quantity _ic corresponding to the capacitor currents _icu and _icw . i _L denotes a disturbance component, and the load current i _Lu ,
i _Lw . The arithmetic circuit 32 calculates i _i −
i _L is integrated and multiplied by 1 / C to obtain a control amount v
Outputs _c . Controlled variable v _c is load voltage or the capacitor voltage v _cu in FIG 1, v corresponds to _cw.

FIG. 6 shows an equivalent circuit of one of the current controllers 25u and 25w of FIG. 4, that is, one phase of the current controller. Incidentally, in response to the ^* command value i _c in FIG. 6 (n) ^* is in Figure 4 i _cu (n) or i _cw ^* (n), the state of FIG. _{6 i c (n-1,} m) is Fig. _Icu (n-1, m) or i of 4
The control amount v _r (n) in FIG. 6 corresponds to _cw (n−1, m), and corresponds to v _ru (n) or v _rw (n) in FIG. The current controller shown in FIG. 6 is disclosed in Japanese Patent Application Laid-Open No. Hei 7-78034 (Japanese Patent Application No. 5-247491) to the present applicant, and is a predicted value _ic 'of the state quantity _ic (n). (N), the inverter operation amount v _r (n), and the disturbance estimation value i _D ′ (n) are obtained according to the following equation. _{i c '(n) = i} c (n-1, m) + K n v r (n-1) (3) v r (n) = {P / (K n T s)} {i c * (n _{) -i D (n) -i c} '(n)} (4) i D' (n) = i c (n-1, m) - [m {i c * (n-1) -i D ' (n-1)] + ( 1-m) [i c * (n-2) -i D '(n-2)}] (5)

The current controller shown in FIG. 6 includes a first arithmetic processing unit 33 for executing the operation of the above equation (4) and a second arithmetic processing unit for executing the operation of the above equation (3). 34
And a third operation processing unit 35 for executing the operation of the above equation (5). The first arithmetic processing unit 33 calculates _ic ^*
A subtractor 36 for subtracting i _D '(n) from (n) and a subtractor 3 for subtracting i _c ' (n) from the output of the subtractor 36
7 and a multiplier 38 for multiplying the output of the subtracter 37 by P / (K _{n Ts} ).
_r (n) is output. The second arithmetic processing unit 34 calculates Equation (3)
The one-sample delay means 39 shown in Z ^-1 to obtain the second term of the right side of _{v r (n-1),} v r (n-1) multiplier for multiplying the constants K _n with respect to 40 When, the multiplier 40 and the output of the i _cu obtained from a / D converter _{1 1} of Figure 1 (n-
1, m) or i _c (n−) corresponding to i _cw (n−1, m).
1, m) and an adder 41 that adds
_Is output as i _c '(n). Third arithmetic processing unit 35
Calculates two one-sample delay means 42 and 43 for performing arithmetic processing on the equation (5), a multiplier 44 for the coefficient m, and a coefficient m−
It comprises a multiplier 45, an adder 46, and a subtractor 47. Note that the adder 46 outputs the second term on the right side of Expression (5).

FIG. 7 shows in principle the relationship between the state quantity i _c (t) and the manipulated variable v _r (t) in the digital control shown in FIGS. If n is the current time, n-
1 represents a time point before T _s times, n + 1 denotes the time point after T _s times. In FIG. 7, sampling is performed, for example, at a time point indicated by (n-1, m) between the time points n-1 and n, and the operation is executed at the time point n after the computation dead time _Td .
Therefore, m takes a value in the range of 0 to 1.

FIG. 8 shows the predicted value i _c '(n) in FIG.
2 shows a state of control using. For example, the manipulated variable v output at the time point n-1 between the time point n-1 and the time point n.
_r (n-1) (output of delay means 39) and (n-1, m)
A predicted value _ic '(n) according to the equation (3) is generated from the control amount _ic (n-1, m) sampled at the time, and output at the time n using the value _ic ' (n). Manipulated variable v
Calculate _r (n). The details of the arithmetic processing in FIG. 5 are substantially the same as the arithmetic processing in FIG. 5 of JP-A-7-78034 (Japanese Patent Application No. 5-247491).

[0025]

When the current controller shown in FIG. 6 is used, the manipulated variable is calculated using the predicted value i _c ′ (n) of the state quantity and the estimated disturbance value i _D ′ (n). v since determining the _r (n), it is possible to match the control amount v _c a relatively high accuracy for example of the command value v _c consisting sine wave of constant amplitude ^{* (n).} Incidentally, when the control target includes the transformer 3, there is a problem of bias excitation. The control circuit 6 of FIG.
JP-A-7-78034 (Japanese Patent Application No. 5-247491)
Is provided with a bias excitation preventing means 24, which is not disclosed, so that the bias excitation is suppressed. However, this does not completely prevent biased excitation. This is because the frequency in the feedback control loop composed of the current control system, that is, the current detectors 10u and 10w in FIG. 1, the current controllers 25u and 25w in FIG. 4, the inverter 2, the inductances Lu, Lv and Lw, and the transformer 3 in FIG. It is considered that the gain characteristic becomes flat on the low frequency side as shown in FIG. 10, DC and low frequency components remain in _ic , and partial excitation of the transformer 3 occurs. When the degree of the partial excitation increases, an excessive current flows to the inverter 2. This type of problem is caused by the current detector 7
It can be prevented by strictly adjusting the DC offset of the sensors u, 7w, 10u, 10w, etc. to zero. However, in an actual product, the DC offset amount changes due to temperature and aging. It is difficult to do.

An object of the present invention is to provide a feedback control device capable of easily suppressing a DC offset amount by compensation.

[0027]

To solve the above problems SUMMARY OF THE INVENTION The present invention for achieving the above object, a control amount v _c is the output of the controlled object including a transformer, an input is the operation amount of the control object between v _r

[0028]

(Equation 3)

(Where C and L are constants indicating the capacitance and inductance of the controlled object, i _i is the state quantity of the controlled object, i _L is an arbitrary disturbance component, and K _inv is a constant indicating the gain.) A feedback control of a controlled object represented by the following relational expression, wherein the controlled variable _vc , the state variable _ii, and the disturbance component i _{L of the} controlled object are
Detection means for detecting as a digital amount or i _i and i _L of the difference _(i i -i _L) amounts corresponding to i _c and the predetermined sampling time intervals T _s, the control amount v _c
Means for detecting value to generate a command value v _c ^* to be followed by a digital quantity of the controlled variable v the manipulated variable v predetermined time intervals _r for the control object so as to follow the detected value of _c in ^{_{T s, i c * (n}} ) = K pv {v c * (n) -v c (n-1)}
−i _oo (n) v _r (n) = {P / (K _n T _s )} _ic ^* (n) −
_{i D '(n) -i c} ' (n)} [ However, where, n is the current time, (n-1) time earlier T _s time than time n, i _c '(n) is i _c (n-1,
m) or i _i (n−1, m) −i _L (n−1, m), the predicted value of the state quantity _ic at the time point n, where (n−
1, m) is mT _s (where m is n−
A coefficient that satisfies 0 <m <1) for representing a time point between 1 and n) indicates a time point advanced by time. ｝, I _c ^* (n) is i
command value c (n), arbitrary constant Kpv is showing a gain, P is any constant, nominal value of K _n is _{K inv / L, i oo (} n) is the DC component of the state quantity _i i, v _c ^* ( n) is a command value of v _c (n), and i _D ′ (n) is an estimated disturbance value. Formula according calculated in (1-m) T _s times], the feedback control system that includes a digital arithmetic means for outputting said manipulated variable v _r in the controlled object after (1-m) T _s times, The digital operation means calculates a predicted value _ic '(n) of the state quantity _ic (n) at the time point n for the purpose of dead time compensation, by _ic ' (n) = _ic (n-1, m). + K _n v _r (n-
1) means for calculating by the calculation of the expression; and the disturbance estimation value i _D ′
(N) a _{i i '(n) = i} i' (n-1) + K a [K b {i c *
(N−1) −i _D ′ (n−1)｝ − i _i (n−1)] i _D ′ (n) = _ic (n−1, m) −i _i ′ (n) (where here, i _i 'intermediate variables, K _a is the time constant, K
_b is a constant that indicates the gain, which is set smaller value than 1 for DC component removal of said control amount v _c. ) And means for calculating the DC component i _oo (n). The means for obtaining the DC component i _oo (n) is _defined as i _oo (n) = i _oo (n−
1) + K _f {i _i (n−1, m) −i _oo (n−1)}
(However, where, k _f is the time constants.) It is desirable that the means for obtaining the arithmetic expressions. Further, the control target can be an inverter, an inductance, a transformer, a load, and a capacitor. Also,
As described in claim 4, the disturbance component i _L is a load current, and i
_c (n−1, m) is replaced by i _i (n−1, m) −i _L (n−
1, m). Claims 5 and 6
The capacitor can be connected to the primary winding side of the transformer as shown in FIG. Wherein indicating a v _c of claim 1 corresponds to equation (1) described above, wherein indicating the i _i corresponds to the formula (2) described above.

[0030]

According to the present invention, the DC and low-frequency gains of the frequency characteristics in the current control system can be reduced, and the partial excitation of the transformer can be prevented. That is, it is possible to easily prevent the transformer from being excited by the current controller without adjusting the DC offset of the detection system to zero.

[0031]

First Embodiment Next, a first embodiment of the present invention will be described. The feedback control device according to the first embodiment differs from the conventional feedback control device shown in FIGS. 1 to 6 in that a part of the current controllers 25, 25u, and 25w is changed.
6 are the same as those of the conventional apparatus shown in FIGS. 1 to 6, and FIGS. 1 to 5 are regarded as a part of the embodiment.

The current controller 25 'of this embodiment is configured as shown in FIG. The configuration of the current controller 25 'of FIG. 11 except for the third arithmetic processing unit 35' for obtaining the estimated disturbance value i _D '(n) is the same as that of the current controller 25 of FIG. Therefore, in FIG. 11, portions common to FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.
The third operation processing unit 35 'in FIG. 11 is configured to execute the operation of the following equation. _{i i '(n) = i} i' (n-1) + K a [K b {i c * (n-1) -i D '(n-1)} - i i' (n-1)] ( _{6) i D '(n)} = i c (n-1, m) -i i' (n) (7) where, where, _{i i} '(n) is an intermediate variable, K _a is the filter time constant, K _b is a filter gain set to be smaller than 1, i _i ′ (n−1) is a value of i _i (n) T _s before, and i _D ′ (n−1) is i _D ′ (n). The value _ic ^* (n-1) before the time T _s is the command value i expressed by the equation (3).
_Shows the value of _c ^* (n) before T _s time.

A third operation for executing the operation of equation (6)
Calculation processing unit 35 'includes a first T _s time delay means 42, as shown in FIG. 11, a first multiplier 48 for multiplying the coefficients K _b corresponding to the filter gain in the delay output, the first a subtractor 49, a second T _s time delay means 50, a second multiplier 51 for multiplying the constant corresponding to the filter time constant K _a
, An adder 52, and a second subtractor 47. First
The delay means 42 of the formula _{i c} ^* right contained in the second term of (6) (n-1) -i D '(n-1) is obtained. The second delay means 50 is an intermediate variable i _i '(n) indicating a state quantity.
_Is output as the value i _i '(n-1) before the time Ts. The first subtractor 49 subtracts the output of the second delay means 50 from the output of the second multiplier 48. Second multiplier 51 hand side of equation (6) by multiplying the K _a to the output of the first subtractor 49
Output the value of the term. The adder 52 adds the output of the multiplier 51 to the output of the delay means 50, and adds the intermediate variable i _i 'in equation (6).
(N) is output. The second subtractor 47 executes the operation of Expression (6) and outputs the disturbance estimation value i _D ′ (n).

FIG. 12 shows the third arithmetic processing unit 35 'shown in FIG. 11 using the well-known Z-transform method. The delay means 42 and the subtractor 47 in FIG. 12 are the same as those indicated by the same reference numerals in FIG. Block 61 is a filter time constant K
_a including the filter gain K
Indicates _b .

In this embodiment, the estimated disturbance value i _D '(n)
Is calculated by the equations (6) and (7), the same effect as when the frequency characteristic filter of FIG. 13 is inserted into the voltage control system of FIG. 1 is obtained, and the main circuit including the transformer 3 (the control target)
Is suppressed, and the bias excitation of the transformer 3 is also suppressed. In short, the frequency characteristics in the current control system are shown in FIG.
As shown in (1), the fact that the DC component is lower than 0 dB at and near the DC means that the DC component does not easily flow through the control target including the transformer 3, and the bias excitation of the transformer 3 is prevented. As described above, if the DC component can be suppressed by the current controller 35 ', the current detectors 7u, 7u of FIG.
w, 10u, 10w, and the DC excitations in the A / D converters 8, 11 and the like can be prevented from being biased even if they are not strictly adjusted to zero.

[0036]

Second Embodiment Next, a feedback control device according to a second embodiment will be described with reference to FIG. However, in FIG. 14 and FIGS. 15 and 16 showing third and fourth embodiments to be described later, substantially the same parts as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. The feedback control device of FIG. 14 differs from that of FIG. 1 in that the positions of the current detectors 10 u and 10 w are changed, and that the subtractors 71 and 72 are provided in the output stage of the A / D converter 11. 1 is identical to that of FIG. However,
The current controllers 25u and 25w shown in FIG.
Is replaced by a current controller 25 'shown in FIG. 6 which is the same as that of the first embodiment. It should be _noted that i _i ,
i _c, v detection means _c is a current detector 7u, 7w, 10
u, 10w, A / D converters 8, 11, 13, transformer 1
2. It comprises subtractors 71 and 72.

In FIG. 14, the current detectors 10u, 10w
Is electromagnetically or magnetically coupled to the lines 9u, 9w on the load side of the capacitors Cu, Cv, Cw to detect the load currents i _Lu , i _Lw . Therefore, from the A / D converter 11, i _Lu, i _Lu based on _{i Lw (n-1, m} ) and i _Lw
A signal indicated by (n-1, m) is output. The subtractors 71 and 72 as operation means include inverter currents i _iu (n−1, m) and i indicating the state quantity obtained from the A / D converter 8.
i obtained from the A / D converter 11 from _iw (n−1, m)
_Lu (n-1, m) and _iLw (n-1, m) are subtracted respectively to obtain _icu (n-1, m) and _icw (n-1, m). That is, the subtracters 71 and 72 execute the operation of the following equation. _icu (n-1, m) = _iiu (n-1, m) _-iLu (n-
1, m) i _cw (n−1, m) = i _iw (n−1, m) −i _Lw (n−
1, m) u-phase and w-phase i _cu (n) obtained from the subtracters 71 and 72
−1, m) and icw (n−1, m) are comprehensively represented by one phase, and are _ic (n−1, m), as in the first embodiment. It is input to the subtractor 47.

[0038] There are relationships _{i c} = i i -i _L between the output current i _i and the capacitor Cu ～Cw current i _c of the inverter 2 and the load current i _L in FIGS. 1 and 14 (trans 3 when ignoring the excitation current), _{i c,} i i, detects any two among i _L, it is possible to know the remaining one. According to this principle, the second embodiment of FIG.
_The values corresponding to _i and i _L are detected, and i _cu (n−1, m) and i corresponding to i _c are detected using subtractors 71 and 72.
_{Since the} configuration is the same as that of the first embodiment _{except that cw} (n-1, m) is obtained, the same operation and effect as those of the first embodiment are obtained.

[0039]

Third Embodiment A feedback control device according to a third embodiment shown in FIG. 15 is configured such that the capacitors Cu, Cv and Cw are connected to one of the transformers 3.
Current detectors 7u, 7w of lines 2u, 2v, 2w on the next side
14 in that it is connected between the installation point of
The other configuration is the same as that of FIG. Even if the capacitors Cu, Cv and Cw are connected to the primary side of the transformer 3, the same operation and effect as those of the first and second embodiments can be obtained.

[0040]

Fourth Embodiment A feedback control device according to a fourth embodiment shown in FIG.
The configuration is the same as that of FIG. 15 except that capacitors v, 2w, v, and 2w are arranged between the transformer 3 and the transformer 3. In the fourth embodiment in which the load current detection point is shifted to the primary side of the transformer 3, the same operation and effect as in the first to third embodiments can be obtained.

[0041]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) In FIG. 15 and FIG.
u, similarly capacitor Cu and 1 to 10w, can be arranged to detect the current i _cu, i _cw of Cw. (2) Although the current and voltage of the u-phase and the w-phase are detected in the embodiment, all of the u-phase, the v-phase and the w-phase are respectively detected, and the voltage controller and the current controller of the v-phase in FIG. Can be provided independently. (3) The control target can be a single-phase inverter circuit. (4) A part or all of the A / D converters 8, 11, 13 and the subtracters 71, 72 can be included in the control circuit 6 side. (5) The subtractors 71 and 72 in FIGS. 14, 15 and 16 can be provided on the input side of the A / D converters 8 and 11 as analog subtractors.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a feedback control device according to a conventional example and an example.

FIG. 2 is a circuit diagram showing the inverter of FIG. 1;

FIG. 3 is a block diagram showing a part of the PWM pulse forming circuit of FIG. 1;

FIG. 4 is a block diagram illustrating a control circuit of FIG. 1;

5 is a diagram equivalently showing the inverter of FIG. 1 and its output stage.

FIG. 6 is a block diagram equivalently or functionally showing a conventional example of the current controller of FIG. 4;

FIG. 7 is a diagram for explaining a relationship between a sampling time point and an operation time point of an input to the current controller of FIG. 6;

8 is a diagram showing a relationship between a control amount, a predicted value, and an operation amount in the current controller of FIG. 6;

FIG. 9 is a waveform diagram showing inputs and outputs of the comparator of FIG. 3;

10 is a frequency characteristic diagram of a current control system in the feedback control device of FIG. 1 including the current controller of FIG. 6;

FIG. 11 is a block diagram equivalently showing a current controller according to the first embodiment of the present invention.

FIG. 12 is a block diagram functionally showing a third arithmetic processing unit in FIG. 11;

13 is a frequency characteristic diagram of a current control system in the feedback control device of FIG. 1 including the current controller of FIG. 11;

FIG. 14 is a block diagram illustrating a feedback control device according to a second embodiment.

FIG. 15 is a block diagram illustrating a feedback control device according to a third embodiment.

FIG. 16 is a block diagram illustrating a feedback control device according to a fourth embodiment.

[Explanation of symbols]

 2 Inverter 3 Transformer 4 Load 7u, 7w Current detector 10u, 10w Current detector 25 Current controller

Claims (6)

(57) [Claims] 1. A control amount v _c is the controlled object including a transformer output, Equation 1] between the input manipulated variable v _r of the controlled (Where C and L are constants indicating the capacitance and inductance of the control target, _ii is the state quantity of the control target, i _L is an arbitrary disturbance component, and K _inv is a constant indicating the gain.) an apparatus for feedback control of the controlled object which can be represented by the difference between the controlled variable v _c of the control object and the state quantity i _i the disturbance component i _L or i _i and i _L (i _i detection means for detecting as a digital amount -i _L) amounts corresponding to i _c and the predetermined sampling time intervals T _s, the control amount v command value detected value to be followed in the _c v _c ^* digital means for generating as the amount, in the control amount v the manipulated variable for the control object so as to follow the detected value of _c v _r a predetermined time interval ^{_{T s, i c * (n}} ) = K pv { ^{_{v c * (n) -v c}} (n-1)} - i _{oo (n) v r (n} ) = {P / (K n T s)} {i c * (n) -i D '(n) -i c' (n)} [ However, Here, n present time, (n-1) T _s times a time prior to the time n, i _c '(n) is _{i c (n-1, m} ) or _i i (n-
1, (m) -i _L (n-1, m), the predicted value of the state quantity _ic at the time point n, where (n-1, m) is (n-1)
The time point is a time point earlier than the time point by mT _s (where m is a coefficient satisfying 0 <m <1 for representing a time point between n−1 and n). }, I _c ^* (n) is the command value of i _c (n), K _pv is an arbitrary constant that indicates the gain, P is any constant, nominal value of K _n is _{K inv / L, i oo (} n) state DC component amounts ^{_{i i, v c * (n}} ) is v command value _{c (n), i D '} (n) is the disturbance estimated value. (1)
-M) calculated in T _s time, the feedback control system that includes a digital arithmetic means for outputting said manipulated variable v _r in the controlled object after (1-m) T _s time, said digital computing means, predicted value i _c of the state quantity i _c at time n for the dead time compensation (n) 'a _{(n), i c' (} n) = i c (n-1, m) + K n v r (n −
1) means for calculating by the equation (1), and the disturbance estimation value i _D ′ (n) is calculated as _ii ′ (n) = _ii ′ (n−1) + K _a [K _b ｛ _ic ^* (n−1) _{) -i D '(n-1} )} - i i (n-1)] i D' (n) = i c (n-1, m) -i i '(n) ( where, in this case, i _i 'is an intermediate variable, K _a is the time constant, is K _b a constant indicating a gain, a small set value than 1 for DC component removal of said control amount v _c.)
And a means for calculating the DC component i _oo (n). 2. The means for determining the DC component I _oo (n) includes: i _oo (n) = i _oo (n−1) + K _f ｛i _i (n−1,
2. The feedback control device according to claim 1, wherein the feedback control device is a unit that is obtained by calculating an expression of m) -i _oo (n-1) −１ (where k _f is a time constant). 3. The control target includes: an inverter including a conversion switch for converting a DC voltage into an AC voltage; a transformer primary winding connected to an output terminal of the inverter via an inductance; a secondary winding electromagnetically coupled to the next winding, wherein a load connected to the secondary winding consists of a capacitor which is substantially connected in parallel with the load, the control amount v _c is the load a voltage, the operation amount v _r is a signal for determining the on-off of the conversion switch of the inverter, the state quantity i _i is an output current of the inverter flowing through the inductance , an amount corresponding to the difference of the disturbance component i _L and the state quantity i _i i
3. The feedback control device according to claim 1, wherein _c is a current of the capacitor. 4. The control target includes: an inverter including a conversion switch for converting a DC voltage into an AC voltage; a transformer primary winding connected to an output terminal of the inverter via an inductance; a secondary winding electromagnetically coupled to the next winding, wherein a load connected to the secondary winding consists of a capacitor which is substantially connected in parallel with the load, the control amount v _c is the load a voltage, the operation amount v _r is a signal for determining the on-off of the conversion switch of the inverter, the state quantity i _i is an output current of the inverter flowing through the inductance the disturbance component i _L is the current of the load, the i _c is claim 1 or 2, characterized in that a value obtained by the formula of _{i c} = i i -i _L
A feedback control device as described. 5. The control object includes: an inverter including a conversion switch for converting a DC voltage into an AC voltage; a transformer primary winding connected to an output terminal of the inverter via an inductance; consists of a secondary winding which is electromagnetically coupled to the next winding, and a load connected to the secondary winding, and a capacitor which is substantially connected in parallel with the primary winding, the control amount v _c the voltage of the load, wherein the operation amount v _r is a signal for determining the on-off of the conversion switch of the inverter, wherein the state quantity i _i is the current of the primary winding capacitors the sum of the currents, the disturbance component i _L is the current of the load, the i _c is claim 1, characterized in that a value obtained by the formula of _{i c} = i i -i _L or 2
A feedback control device as described. 6. The control target includes: an inverter including a conversion switch for converting a DC voltage to an AC voltage; a transformer primary winding connected to an output terminal of the inverter via an inductance; consists of a secondary winding which is electromagnetically coupled to the next winding, and a load connected to the secondary winding, and a capacitor which is substantially connected in parallel with the primary winding, the control amount v _c the voltage of the load, wherein the operation amount v _r is a signal for determining the on-off of the conversion switch of the inverter, wherein the state quantity i _i is the current of the primary winding capacitors the sum of the currents of, claims the disturbance component i _L is the current of the primary winding, wherein i _c is characterized in that it is a value determined by the expression _{i c} = i i -i _L Item 1 or 2
A feedback control device as described.