JP3237601B2 - Memory LSI inspection apparatus and memory LSI inspection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory LSI inspection apparatus which integrates an electric address and a real object observation.

[0002]

2. Description of the Related Art Conventionally, as an apparatus for inspecting a memory LSI, a memory tester has been used to inspect an electric address. In this device, it is possible to input an electric signal to the memory LSI and inspect an electrically defective address. In addition, there is an address scramble as a function of performing an electrical test using a physical address on a memory tester.

There are optical microscopes, SEMs, FIBs, and the like as devices for observing the appearance, and can observe pattern defects or particles.

[0004]

However, the above-mentioned prior art has the following problems. First, it is difficult to observe the appearance of an electrically defective address. In other words, even if an electrically defective physical address is known, the actual location on the chip depends on the design, so that the design mask drawing or the like must be examined in detail. In addition, even when actually observing with a human hand, it is necessary to search for a location to inspect the appearance while counting the number of memory cells by the number of addresses using a microscope or the like. Similarly, it has been difficult to specify an electrical address corresponding to a portion having an abnormal appearance.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an LSI inspection apparatus capable of inspecting all at once by associating an electrically defective address with a defective portion in appearance. And

[0006]

SUMMARY OF THE INVENTION A memory LS according to the present invention
The I inspection apparatus converts a memory cell to be selected on a memory LSI into a cell logical address determined by an address pin, a cell physical address expressed in an actual array order of memory cells on a chip, and a size indicating a location. In a memory LSI inspection apparatus that expresses by coordinates and integrates an electrical address and a real object observation, a cell logical address storage unit, a cell physical address storage unit, and the cell logical address to the cell physical address An address conversion unit that performs the conversion of the cell physical address to the cell logical address, a cell block edge coordinate input unit, a cell block edge coordinate storage unit, and an observation coordinate storage unit that stores an observation point as coordinates. An observation unit for observing a coordinate position in the observation coordinate storage unit, a physical address size storage unit, and the cell From the lock edge coordinates and the physical address size of the cell block, calculate the coordinates of the location where the cell unit in the cell block is equally divided by the physical address size by the number of physical addresses, and store this in the observation coordinate storage unit. An arithmetic unit for storing and calculating a corresponding cell physical address from the observation coordinates of the observation coordinate storage unit and storing the calculated cell physical address in the cell physical address storage unit;
Means for scanning a contrast in a chip, extracting a plurality of coordinates of a sharp change point of the contrast, detecting a break in the periodicity of the coordinate interval, and automatically obtaining cell block edge coordinates. It is characterized by. Also,
Another memory LSI inspection apparatus according to the present invention includes a memory LS
A selected memory cell on I is represented by a cell logical address determined by an address pin, a cell physical address expressed in the order of arrangement of the memory cells on the actual chip, and coordinates of dimensions indicating a location. In a memory LSI inspection apparatus for inspecting an electric address and an actual object in an integrated manner, a cell logical address storage unit, a cell physical address storage unit, a conversion from the cell logical address to the cell physical address or the cell physical address An address conversion unit that converts an address to the cell logical address, a cell block edge coordinate input unit, a cell block edge coordinate storage unit, and an observation coordinate storage unit that stores observation points as coordinates.
An observation unit for observing a coordinate position in the observation coordinate storage unit, a physical address size storage unit, and the cell block edge coordinates and the physical address size of the cell block,
Calculate the coordinates of the locations where the cell units of the cell block are equally divided by the physical address size are counted by the number of physical addresses, and store the coordinates in the observation coordinate storage unit, and the observation coordinates in the observation coordinate storage unit. And a calculation unit for calculating a corresponding cell physical address from the above and storing the calculated cell physical address in the cell physical address storage unit, a list of electrically defective addresses, and a list of defective locations in appearance, to extract corresponding locations. Means. According to the memory LSI inspection method of the present invention, a memory cell to be selected on a memory LSI is converted into a cell logical address determined by an address pin, a cell physical address expressed in an actual array order of the memory cells on a chip, In a memory LSI inspection method in which an electrical address and an actual object observation are integrated and inspected by expressing the coordinates of dimensions indicating a location and integrating the electrical address and the actual observation, the conversion from a cell logical address to a cell physical address or the cell physical address to the cell logic The step of performing address conversion by the address conversion unit, and a location where the number of physical units equal to the physical unit size in the cell block is counted by the physical address size from the cell block edge coordinates and the physical address size of the cell block. Is calculated and stored in the observation coordinate storage unit. Calculating the corresponding cell physical address from the observed coordinates and storing it in the cell physical address storage unit; scanning the contrast in the chip; extracting a plurality of coordinates of a sharp change point of the contrast; And automatically calculating the cell block edge coordinates by detecting the break of the periodicity. According to another memory LSI inspection method according to the present invention, a memory LSI
The memory cell to be selected is expressed by a cell logical address determined by an address pin, a cell physical address expressed in an array order of actual memory cells on a chip, and coordinates of dimensions indicating a location, In a memory LSI inspection method for inspecting by integrating an electrical address and a real object observation, a step of performing a conversion from a cell logical address to a cell physical address or a conversion from the cell physical address to the cell logical address in an address conversion unit; From the cell block edge coordinates and the physical address size of the cell block, calculate the coordinates of the location where the cell units in the cell block are equally divided by the physical address size by the number of physical addresses, and store this in the observation coordinate storage unit. And calculate the corresponding cell physical address from the observation coordinates in the observation coordinate storage unit. A step of storing the cell physical address storage unit, a list of electrical defective address, to generate a list of the external appearance of the defect sites, and having a step of extracting the corresponding part of the cross, the.

This memory LSI inspection apparatus uses a list of appearance defect locations in a plurality of steps in an LSI manufacturing process and a list of electrical failure addresses to determine the correspondence rate between appearance defects and electrical failures in each step. It is preferable to have a means for calculating, and it is preferable to have a means for associating a continuous address among a plurality of electrically defective addresses with a single electrical defect having a size with a defective portion in appearance.

In the present invention, using the cell block edge coordinates, the cell physical address, and the physical address size, the coordinates of a location where a cell unit having a size equally divided by the physical address size in the cell block is counted by the number of physical addresses are calculated. Observed coordinates. For this reason, it is possible to easily calculate the coordinates of the memory cell without requiring detailed design data such as the size and shape of the memory cell.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of the LSI inspection system of the present embodiment.
The LSI inspection system according to the present embodiment includes a common system 1 and a product database 2. The product database 2 stores an address conversion rule 14 between a physical address and a logical address, a physical address size 13, and a cell block edge coordinate 12. In the common system 1, the address of the electrical failure is input from the address input unit 3 and stored in the logical address storage unit 4 or the physical address storage unit 5. These storage units 4 and 5 can be constituted by a hard disk or a memory, or may be temporary storage. The input unit 3 can be constituted by keyboard input, network input from a memory tester, data input from a defective address database, or the like.

The address display section 6 displays the address of the electrical failure input from the address input section 3, the logical address and the physical address stored in the storage sections 4 and 5, and comprises a CRT display or a printer. can do. The conversion from the logical address to the physical address and the conversion from the physical address to the logical address are performed by the address conversion unit 7. The conversion from the physical address to the observation coordinates and the conversion from the observation coordinates to the physical address are performed by the arithmetic unit 8.
Done by

The observation coordinates calculated by the arithmetic unit 8 are temporarily stored in the observation coordinate storage unit 9, and the observation unit 10 observes the location of the observation coordinates stored in the storage unit 9. Storage unit 9
As a specific configuration of the observation unit 10 for observing the coordinates designated by the user, there is a configuration in which the LSI to be observed is placed on an XY stage, and the observation coordinates are controlled by the stage. The observation means in the observation unit 10 includes an optical microscope or an electron microscope. Observation unit 1
The coordinates at which a pattern defect is detected by 0 are stored in the observation coordinate storage unit 9 and further converted into physical addresses by the arithmetic unit 8.

Next, address conversion in the address conversion unit 7 will be described with reference to FIG. As shown in FIG. 2A, the logical address (LX, LY, IO) is composed of a logical X address (LX), a logical Y address (LY), and IO, and is defined in the order of the actual memory cell arrangement. The physical address (PX, PY) is composed of a physical X address (PX) and a physical Y address (PY). Each coordinate value is expressed as a value of 0 or 1 in each digit when the coordinate value is represented by a binary number. Assuming that the first digit is LX0 and the second digit of LX is LX1 or the like, the conversion rule from the logical address to the physical address is as shown in FIG. 2B.

Next, a method of calculating the cell block edge coordinates from the layout of the memory LSI chip will be described with reference to FIG. FIG. 3 is a diagram for explaining a cell block arrangement in a chip and cell block edge coordinates.

In this example, there is shown a case where there are four cell blocks C1, C2, C3 and C4 in a chip. First, the edges of each cell block C1, C2, C3, C4 are detected. As a detection method, a chip is placed on an XY stage, and while observing with a microscope, a method of obtaining the coordinates from the stage coordinates of the edge portion, a method of obtaining the coordinates from the micrograph, and automatically detecting the edge as described later. And the like.

The detected edge is obtained as coordinates of the distance from the origin of the chip. That is, the cell block C1 is obtained as BX11, BX12, BY11, and BY12. As for the cell blocks C2 to C4, if the block size is the same as the cell block C1, the block edge can be specified only by obtaining one coordinate value in each of the X direction and the Y direction. That is, for the cell blocks C2 to C4, BX21, BX31, BX41, BY21,
Coordinate values are obtained as in BY31 and BY41. Even for a wafer having a plurality of chips, if the cell block edge coordinates from the chip origin are detected for only one chip, the cell block edge coordinates of all chips can be obtained from the chip repeat size. .
The coordinates of the cell block edge thus obtained are input to the common system 1 via the input unit 11. Also,
Once the cell block edge coordinates are obtained, if they are stored in the product database 2 as data unique to the LSI product, that is, as cell block edge coordinates 12,
There is no need to detect edges from next time.

Next, a method of calculating observation coordinates from physical addresses in the arithmetic section 8 will be described. FIG.
(A) shows an example of the layout of an actual memory cell.
In order to define the edge of the cell block from such a layout of the memory cells, the locations indicated by BX1 and BX2 in the X direction are edges. Particularly, the left edge is set to BX1 because the repetition period of the memory cell is taken into consideration. However, even if BX0 is the left edge, there is almost no effect if the number of memory cells is large. Observation coordinates for the cell physical address are obtained from the cell block edge coordinates and the physical address size thus detected.

FIG. 4B shows a layout of the memory cells when the memory cells in the cell block are approximated to a rectangle. By approximating with a rectangle in this way, it is possible to obtain the coordinates of the address without requiring detailed design information of the memory cell. When there are memory cells of the physical address size (Nx × Ny) in the cell block, the observation coordinates for the physical address (PX, PY) can be obtained by the following equation (1).

[0018]

## EQU1 ## When the X coordinate is BX1 + (BX2-BX1) × (P
X-PX1) / Nx Y coordinate is BY1 + (BY2-BY1) × (PY-PY
1) / Ny

Here, PX1 and PY1 are the physical addresses of the left end and the upper end in the cell block, respectively.

Since a memory cell has a size, a single coordinate alone cannot represent the entire memory cell, but a range of cell size from one reference coordinate in the cell can be regarded as a cell. . As the cell size, a value obtained by dividing the coordinate interval at both ends of the cell block by the physical address size of the cell block can be used.

The physical address size in a cell block may be specified for each cell block, but can also be calculated from the physical address size of the entire chip and the number of cell blocks. Similarly, the physical address (PX1, PY1) of the cell block end can be calculated.

Next, the operation of the LSI inspection apparatus configured as described above will be described. The address of the electrical failure is input from the address input unit 3 and is displayed on the display unit 6, and the logical addresses and the physical addresses are stored in the storage units 4 and 5, respectively. The logical addresses and physical addresses stored in the storage units 4 and 5 are mutually converted according to an address conversion rule 14 as shown in FIG. The physical address stored in the physical address storage unit 5 is converted into observation coordinates by the operation unit 8 and stored in the observation coordinate storage unit 9. The arithmetic unit 8 performs a physical address size 13 and a cell block edge coordinate 12
Alternatively, reference is made to the cell block coordinates input from the input unit 11. The observation unit 10 observes the location of the observation coordinates stored in the storage unit 9 and detects the presence or absence of a pattern defect. The coordinates of the part where the pattern defect is detected by the observation unit 10 are stored in the observation coordinate storage unit 9, further converted into physical addresses by the calculation unit 8, and then stored in the storage unit 5.
The physical address of the observation point where the pattern defect having this appearance is detected is displayed on the address display unit 6, and is displayed together with the address of the electrical failure.

The above-described address conversion rules, physical address sizes, and cell block edge coordinates are parameters unique to LSI products, which can be obstacles to the versatility of the inspection system. 14, the physical address size 13 and the cell block edge coordinates 12 are stored as the product database 2, and the other parts are set as the common system 1, so that only the product database is created for different LSI product types. Thus, the inspection can be easily performed.

The cell block edge coordinates can be automatically obtained. FIG. 5 shows a method for automatically detecting the edge of the cell block. First, the contrast in the chip is scanned to find a place where the contrast changes rapidly. There are cases where the contrast changes abruptly at the edge of the wiring in the cell block and at the edge of the cell block. In order to extract only the cell block edge, it is necessary to distinguish it from the edge of the wiring in the cell block, but since the wiring in the cell block is arranged periodically, by determining the periodicity, It is possible to distinguish between the cell block edge and the wiring in the cell block. That is, when the interval values between the target edge and the immediately preceding edge are arranged for all the target edges in the cell block, these interval values have a minimum repetition unit and are repeated in the repetition unit. . Therefore, the edge just before the edge where the repetition is not established or the last edge where the repetition is established can be obtained as the edge of the cell block.

As shown in FIG. 6, a list of electrically defective addresses and a list of defective addresses in appearance can be represented on the same coordinates by the embodiment shown in FIGS. , It is possible to check their correspondence. Electrically defective address 1 overlaps with defect 1,
The electrically defective address 2 and the electrically defective address 3 do not overlap with any of the defects. Furthermore, defect 2 does not overlap with any of the electrically defective addresses.

When these relationships are represented by numbers, three electrical defects, two appearance defects, and one overlapping one. From these, it can be seen that, for example, the electrical failure rate for appearance defects is 1/2, that is, 50%. in this case,
When determining whether or not they overlap, it is effective to set an overlap margin that includes factors such as the size of the memory cell, the size of the defect, misalignment, and overlay accuracy.

Further, as shown in FIG. 7, the appearance defect is inspected at each stage of the manufacturing process, and the electrical defect rate or the corresponding number of electrical defects is calculated for the appearance defect at each stage.
It becomes possible to extract a manufacturing process that is most likely to cause an electrical failure.

Further, as shown in FIG. 8, a plurality of physically defective electrical defective addresses have a 4-bit defective address as shown in the electrical defective address list 1. However, among the defective addresses of the electrical defects 1 to 4, it is considered that the defect 3 and the defect 4 are caused by the same defect. Therefore, when the correspondence ratio between the electrically defective address list 1 and the observed defect list is calculated,
The response rate looks lower than it really is.

As a means for solving this, a list of electrical failures such as an electrical failure address list 2 is created by regarding continuous addresses as one electrical failure having a size. By associating the thus formed electrical defect with the appearance defect, a more accurate response can be obtained.

[0030]

As described above, according to the present invention, it is possible to extract a defective portion in appearance with respect to an electrically defective address without requiring detailed design information. For this reason, while ensuring the versatility of the inspection system, individual L
Inspection of SI products is possible with minimum operations.

It is to be noted that the cell block coordinates can be automatically obtained by scanning the contrast on the chip. Further, as described in the fourth aspect, the correspondence between the electrically defective address and the appearance defect can be taken, whereby the appearance defect causing the electric failure can be extracted, which contributes to the improvement of the manufacturing yield. Furthermore, according to the fifth aspect, it becomes possible to extract a step that becomes electrically defective from a plurality of manufacturing steps, and it is possible to improve the manufacturing yield. Furthermore, according to the present invention, it is possible to accurately calculate the correspondence rate between the electrical failure and the appearance defect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a method of converting a logical address and a physical address according to the present invention.

FIG. 3 is a diagram illustrating a cell block arrangement in a chip and cell block edge coordinates.

FIG. 4 is a diagram illustrating a relationship between a cell block edge and a cell.

FIG. 5 is a diagram showing a method for automatically obtaining a cell block edge.

FIG. 6 is an explanatory diagram in a case where an electrical defect is associated with an appearance defect.

FIG. 7 is a diagram for explaining the correspondence between an electrical defect and an appearance defect in each manufacturing process.

FIG. 8 is a diagram illustrating a method for obtaining a list of electrical defects.

[Explanation of symbols]

 1: Common system 2: Product database 3: Address input unit 4: Logical address storage unit 5: Physical address storage unit 6: Address display unit 7: Address conversion unit 8: Operation unit 9: Observation coordinate storage unit 10: Observation unit 11 : Cell block edge coordinate input unit 12: Cell block edge coordinate 13: Physical address size 14: Address conversion rule

Continuation of front page (56) References JP-A-4-225252 (JP, A) JP-A-6-148283 (JP, A) JP-A-62-169342 (JP, A) JP-A-9-167500 (JP) JP-A-1-319866 (JP, A) JP-A-9-319658 (JP, A) JP-A-9-232388 (JP, A) JP-A-10-92883 (JP, A) 6-275688 (JP, A) JP-A-8-339945 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/66 G01R 31/28 G11C 29/00 655

Claims (7)

(57) [Claims] 1. A memory cell to be selected on a memory LSI has a cell logical address determined by an address pin, a cell physical address expressed in an array order of memory cells on an actual chip, and a dimension indicating a location. In a memory LSI inspection apparatus which expresses an electric address and a real object observation integrally by expressing by using coordinates, a cell logical address storage unit, a cell physical address storage unit, and from the cell logical address to the cell physical address An address conversion unit that performs the conversion of the cell physical address to the cell logical address, a cell block edge coordinate input unit, a cell block edge coordinate storage unit, and an observation coordinate storage unit that stores observation points as coordinates. An observation unit that observes a coordinate location in the observation coordinate storage unit; a physical address size storage unit; From the cell block edge coordinates and the physical address size of the cell block, the coordinates of a location where the cell unit in the cell block is equally divided by the physical address size by the number of physical addresses are calculated, and this is calculated as the observation coordinate storage unit. And an arithmetic unit for calculating a corresponding cell physical address from the observation coordinates in the observation coordinate storage unit and storing the calculated cell physical address in the cell physical address storage unit. Means for extracting a plurality of point coordinates, detecting a break in the periodicity of the coordinate interval, and automatically obtaining cell block edge coordinates. 2. A memory cell to be selected on a memory LSI is defined by a cell logical address determined by an address pin, a cell physical address expressed in an array order of memory cells on an actual chip, and a dimension indicating a location. In a memory LSI inspection apparatus which expresses an electric address and a real object observation integrally by expressing by using coordinates, a cell logical address storage unit, a cell physical address storage unit, and from the cell logical address to the cell physical address An address conversion unit that performs the conversion of the cell physical address to the cell logical address, a cell block edge coordinate input unit, a cell block edge coordinate storage unit, and an observation coordinate storage unit that stores observation points as coordinates. An observation unit that observes a coordinate location in the observation coordinate storage unit; a physical address size storage unit; From the cell block edge coordinates and the physical address size of the cell block, the coordinates of a location where the cell unit in the cell block is equally divided by the physical address size by the number of physical addresses are calculated, and this is calculated as the observation coordinate storage unit. An arithmetic unit for calculating a corresponding cell physical address from the observation coordinates of the observation coordinate storage unit and storing the calculated cell physical address in the cell physical address storage unit; a list of electrical failure addresses; And a means for generating a corresponding part and extracting a corresponding part from each other. 3. A memory cell to be selected on a memory LSI is defined by a cell logical address determined by an address pin, a cell physical address expressed in an actual array order of memory cells on a chip, and a size indicating a location. In a memory LSI inspection apparatus which expresses an electric address and a real object observation integrally by expressing by using coordinates, a cell logical address storage unit, a cell physical address storage unit, and from the cell logical address to the cell physical address An address conversion unit that performs the conversion of the cell physical address to the cell logical address, a cell block edge coordinate input unit, a cell block edge coordinate storage unit, and an observation coordinate storage unit that stores observation points as coordinates. An observation unit that observes a coordinate location in the observation coordinate storage unit; a physical address size storage unit; From the cell block edge coordinates and the physical address size of the cell block, the coordinates of a location where the cell unit in the cell block is equally divided by the physical address size by the number of physical addresses are calculated, and this is calculated as the observation coordinate storage unit. An arithmetic unit for calculating a corresponding cell physical address from the observation coordinates of the observation coordinate storage unit and storing the calculated cell physical address in the cell physical address storage unit; a list of electrical failure addresses; Means for extracting corresponding parts from each other; a list of appearance defect locations in a plurality of steps in the LSI manufacturing process; A means for calculating a response rate of a target failure. 4. A memory cell to be selected on a memory LSI is defined by a cell logical address determined by an address pin, a cell physical address expressed in an actual array order of memory cells on a chip, and a size indicating a location. In a memory LSI inspection apparatus which expresses an electric address and a real object observation integrally by expressing by using coordinates, a cell logical address storage unit, a cell physical address storage unit, and from the cell logical address to the cell physical address An address conversion unit that performs the conversion of the cell physical address to the cell logical address, a cell block edge coordinate input unit, a cell block edge coordinate storage unit, and an observation coordinate storage unit that stores observation points as coordinates. An observation unit that observes a coordinate location in the observation coordinate storage unit; a physical address size storage unit; From the cell block edge coordinates and the physical address size of the cell block, the coordinates of a location where the cell unit in the cell block is equally divided by the physical address size by the number of physical addresses are calculated, and this is calculated as the observation coordinate storage unit. An arithmetic unit for calculating a corresponding cell physical address from the observation coordinates of the observation coordinate storage unit and storing the calculated cell physical address in the cell physical address storage unit; a list of electrical failure addresses; Means for generating corresponding ones of the plurality of electrically defective addresses, and means for associating a continuous address among the plurality of electrically defective addresses with one having a size as a defective part in appearance, A memory LSI inspection device, comprising: 5. The apparatus according to claim 2, wherein an overlap margin is set when judging whether or not the electrically defective address and the appearance defect overlap. Memory LSI inspection device. 6. A memory cell to be selected on a memory LSI is defined by a cell logical address determined by an address pin, a cell physical address expressed in the order in which the memory cells are actually arranged on a chip, and a size indicating a location. In a memory LSI inspection method for expressing an electric address and a real object observation in an integrated manner by expressing by coordinates, the conversion from a cell logical address to a cell physical address or the conversion from the cell physical address to the cell logical address is performed. The process performed by the address conversion unit, and from the cell block edge coordinates and the physical address size of the cell block, the coordinates of the location where the cell unit in the cell block is equally divided by the physical address size by the number of physical addresses are calculated. Are stored in the observation coordinate storage unit, and the corresponding coordinates are stored from the observation coordinates in the observation coordinate storage unit. Calculating the cell physical address and storing it in the cell physical address storage unit; scanning the contrast in the chip to extract a plurality of coordinates of a sharp change point of the contrast; Detecting the cell block edge coordinates automatically by detecting the cell block edge coordinates. 7. A memory cell to be selected on a memory LSI is defined by a cell logical address determined by an address pin, a cell physical address expressed in an actual array order of memory cells on a chip, and a size indicating a location. In a memory LSI inspection method for expressing an electric address and a real object observation in an integrated manner by expressing by coordinates, the conversion from a cell logical address to a cell physical address or the conversion from the cell physical address to the cell logical address is performed. The process performed by the address conversion unit, and from the cell block edge coordinates and the physical address size of the cell block, the coordinates of the location where the cell unit in the cell block is equally divided by the physical address size by the number of physical addresses are calculated. Are stored in the observation coordinate storage unit, and the corresponding coordinates are stored from the observation coordinates in the observation coordinate storage unit. Calculating a cell physical address and storing the cell physical address in a cell physical address storage unit; generating a list of electrically defective addresses and a list of defective locations in appearance to extract corresponding locations from each other; A memory LSI inspection method characterized by the above-mentioned.