JP3235651B2 - Periodic signal controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a periodic signal control device suitable for controlling a frequency change rate when synchronizing a reference sine wave voltage to an AC power supply voltage such as a commercial power supply or canceling the synchronization.

[0002]

2. Description of the Related Art A power supply device including an inverter schematically shown in FIG. 1 includes a DC power supply circuit 2 connected to a commercial AC power supply 1.
And an inverter 3 for converting a DC voltage obtained from the DC power supply circuit 2 into an AC voltage, and an AC load 5 connected to the inverter 3 via a switch 4. The inverter 3 has a function of stabilizing an output voltage, converts DC to AC, and supplies a stabilized AC voltage to a load.
The DC power supply circuit 2 has a rectifier circuit and an auxiliary power supply for a storage battery or a capacitor to supply power to the inverter 3.
Meanwhile, it is required to prevent interruption of power supply to the load 5 when the inverter 3 fails. For this purpose, the circuit of FIG. 1 includes an inverter abnormality detection circuit 6 and a switch control circuit 7. The switch control circuit 7 responds to the abnormality detection of the inverter abnormality detection circuit 6 and
Is turned off to disconnect the inverter 3 from the load 5, and instead, the contact b of the switch 4 is turned on to connect the load 5 to the commercial AC power supply 1 via the contact b of the switch 4. In addition, a synchronization circuit 9 is connected between the commercial AC power supply 1 and the control circuit of the inverter 3 via the switch 8 in order to suppress frequency fluctuation and phase shift when switching between the inverter 3 and the commercial power supply.
Is connected. The switch 8 supplies a commercial AC voltage to the synchronization circuit 9 via the contact a when the commercial AC power supply is normal, and outputs a fixed frequency signal having the same frequency as the normal commercial AC voltage via the contact b when the commercial power supply is abnormal. And supplies it to the synchronization circuit 9. A commercial frequency abnormality determination circuit 11 is connected to the commercial AC power supply 1 to determine the abnormality of the commercial AC power supply 1, and when the abnormality is determined, the switch 8 is switched from the contact a to the contact b to release the synchronization. The synchronization determination circuit 12 determines whether or not the output voltage of the inverter 3 is synchronized with the commercial AC voltage based on the state of the synchronization circuit 9 when the operation of the inverter 3 is started. When the switch 4 is ON, a signal is sent to the switch control circuit 7 indicating that the contact b of the switch 4 can be switched to a.

FIG. 2 schematically shows the conventional synchronization circuit 9 and inverter 3 of FIG. Inverter 3 is a synchronization circuit 9
, And an inverter control circuit 13 and a conversion circuit 14 connected to each other. The conversion circuit 14 includes a plurality of switches S1, S2
, S3, and S4, and outputs a sine-wave AC voltage by intermittently applying the DC voltage supplied from the power supply circuit 2 shown in FIG. FIG. 2 shows a two-phase bridge inverter circuit as a conversion circuit.
It can also be a phase bridge type inverter. The inverter control circuit 13 includes switches S1 to S4 of the conversion circuit 14.
The control signal for turning on and off is formed. The control circuit 13 outputs a PWM signal whose pulse width is controlled so as to keep the output voltage of the conversion circuit 14 constant as a control signal, and outputs an AC voltage synchronized with the voltage of the commercial AC power supply 1 to the conversion circuit 14. Form the control signal as obtained from

The synchronizing circuit 9 can be called a reference sine wave generator, and is constructed by using the principle of a PLL (phase locked loop), and includes an input circuit 15 and two edges. Detecting circuits 16 and 17, a phase comparator 18, a filter 19 functioning as a proportional-integral compensator (PI compensator), a bias power supply 20, and an adding circuit 2
1, a V / F (voltage / frequency) converter 22, a counter 23, a sin (sine wave) table memory 24,
A (digital / analog) converter 25. The input circuit 15 is a circuit for inputting a sine wave AC voltage Vs (t) represented by a waveform A of the commercial AC power supply 1. The first edge detection circuit 16 shapes the sine wave AC voltage Vs (t) into a square wave or detects a zero point to obtain a waveform B indicating a phase. Second edge detection circuit 17
Is for shaping the output sine wave C of the reference sine wave generator into a square wave or detecting a zero point to obtain a waveform D indicating a phase. The phase comparator 18 has two input waveforms B,
This is a circuit for forming a pulse-like waveform E corresponding to the phase difference of D. The filter 19 smoothes the waveform E to obtain an output as shown by a waveform F1 or F2, and is called a PI (proportional-integral) compensator. The adding circuit 21 adds the bias voltage V2 to the DC voltage V1 indicating the phase difference obtained from the filter 19, and supplies this to the V / F converter 22. The V / F converter 22 includes, for example, a VCO (Voltage Controlled Oscillator) and outputs a frequency signal G corresponding to an input voltage. The counter 23 is reset in response to the output of the first edge detection circuit 16 or the second edge detection circuit 17, counts the frequency signal G, and generates an output H similar to an analog signal. It works. The sin table memory 24 is a memory in which sine wave data is stored,
The sine wave data is sequentially output as addressed by the output of the counter 23. The D / A converter 25 converts the output of the memory 24 into an analog signal to obtain a reference sine wave C. This output is sent to the inverter control circuit 13 and to the second edge detector 17.

[0005]

When an abnormality occurs in the commercial AC power supply 1 during operation of the inverter 3 in synchronization with the commercial AC power supply 1, the contact a of the switch 8 in FIG. The contact b is turned on, the synchronization circuit 9 is disconnected from the commercial AC power supply 1, and the fixed oscillator 10 is connected to the synchronization circuit 9. At this time, if there is a difference between the frequency of the commercial AC voltage before the stop of the synchronous operation and the output frequency (self-running frequency) of the fixed oscillator 10 after the stop of the synchronous operation, the output waveform F1 of the filter 19 in FIG. The output frequency of the synchronization circuit 9 (inverter reference frequency) changes according to F2, and the output frequency of the inverter 3 changes accordingly. The output waveform of the filter 19 changes with this gain, and the waveform F1
Or F2 and does not rise linearly. As a result, the output frequency of the synchronization circuit 9 and the output frequency of the inverter 3 do not change linearly. Therefore, the inverter 3
Even if it is required that the rate of change of the output frequency be 0.5 Hz / sec, for example, this cannot be satisfied exactly. The above-described problem also occurs when synchronous operation is started. That is, in FIG. 1, when switching from the output of the fixed oscillator 10 to the voltage of the commercial AC power supply 1 by the switch 8, if there is a frequency difference between the two, the same problem as in the synchronous operation stop occurs. If the output frequency of the synchronizing circuit 9 jumps abruptly to the target frequency in steps, it becomes impossible to obtain a sine wave output voltage from the inverter 3 during the transition period. In the synchronization circuit 9 shown in FIG.
Since a pulse was input to the input, it was easy to malfunction due to noise. In addition, synchronized output (reference waveform) cannot be obtained by software, which increases the cost as a whole,
Moreover, it has been difficult to achieve high precision.

Accordingly, an object of the present invention is to provide a control device capable of eliminating a difference between a frequency of an input signal and a fixed frequency at a substantially constant frequency change rate when the difference is large. .

[0007]

In order to solve the above problems and to achieve the above object, the present invention provides an output signal having a periodicity synchronized with an input signal having a periodicity and an asynchronous output signal. A device that is formed so as to be able to generate in a controlled manner and that is configured to be able to control the rate of change of the frequency of the output signal, wherein the difference between the frequency of the input signal and the frequency of the output signal is determined. corresponding frequency correction and frequency correction command signal generating means for generating a command signal, said frequency correction command signal the frequency accessory <br/> positive command obtained from the creation means when synchronizing the output signal to the input signal A signal, a switch for stopping the supply of the frequency correction command signal when releasing the synchronization between the output signal and the input signal, a subtraction unit, a limiter unit, an integration unit, and a delay unit. Wherein the subtraction means subtracts the output of the delay means from the output of the switch, the limiter means limits the output of the subtraction means to a predetermined level or less, and the integration means integrates the output of the limiter means The delay means delays the output of the integrating means, and outputs a corrected frequency correction command signal from the integrating means. The corrected frequency correction command signal creating means is configured to reference the frequency of the output signal. A reference frequency command signal generating means for generating a reference frequency command signal for setting a value, an adding means for adding the corrected frequency correction command signal to the reference frequency command signal, and the reference obtained from the adding means. Output signal generating means for generating the output signal having a frequency corresponding to the sum of the frequency command signal and the corrected frequency correction command signal; The present invention relates to a periodic signal control device characterized by comprising: In addition,
It is desirable that the frequency correction command signal generating means is formed as described in claim 2. The input signal may be a commercial AC voltage or a signal synchronized with the commercial AC voltage,
The output signal can be used as a reference signal for inverter control. Further, at least a part of the periodic signal control device can be formed by a digital processing circuit. Further, the frequency abnormality determination according to claim 5 can be performed using the output of the second integration means. In addition, the synchronization can be determined based on the input of the limiter and the output of the third integrator.

[0008]

According to the invention of each claim, since the limiter means is provided, if the frequency correction command signal is large when the switch is turned on, the correction is not executed as it is, and the limiter means is not used. It is limited and corrected.
That is, if the limit value in the limiter is kept constant, one correction operation (correction operation for one sampling period)
, The correction amount becomes constant, and the correction operation of the constant correction amount occurs a plurality of times by a plurality of correction operations, and the output frequency changes with a constant slope. As a result, the frequency change speed can be accurately made constant by the limit value of the limiter means whose physical meaning is clear. When the switch is turned off and the frequency correction command signal is cut off, the signal held in the integrating means and the delay means circulates, the corrected correction command value gradually decreases at a constant speed, and the output frequency becomes the reference frequency. (Free-running frequency) at a constant rate of change. Further, the frequency change speed can be easily changed by changing the limit value in the limiter means. According to the invention of each claim, a frequency signal synchronized by the subtracting means and the integrating means or the multiplying means, the adding means, the subtracting means and the integrating means is formed, so that the conventional edge detector and comparator can be used. Less interference due to noise compared to the one used. According to the third aspect, the synchronous operation of the inverter with respect to the commercial AC power supply and the release thereof can be smoothly achieved.
Further, according to the invention of claim 4, synchronization and release of synchronization can be easily achieved by software processing.
Further, according to the invention of claim 5, it is possible to easily determine the frequency abnormality. Further, according to the invention of claim 6, the synchronization determination can be easily performed.

[0009]

Next, a power supply device including an inverter according to an embodiment of the present invention and a synchronizing circuit thereof will be described with reference to FIGS. However, in FIG. 3, substantially the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 3, the synchronization circuit 9a and the commercial frequency abnormality determination circuit 1
1a and the synchronization determination circuit 12a are the synchronization circuit 9 of FIG.
Although they are used for the same purpose as the commercial frequency abnormality determination circuit 11 and the synchronization determination circuit 12, their configurations are different from those in FIG. 1 correspond to the switch 8 and the fixed oscillator 10 shown in FIG.
a. Therefore, in FIG. 3, the synchronization circuit 9a is directly connected to the commercial AC power supply 1.
The commercial frequency abnormality determination circuit 11a is provided with a synchronization circuit 9a.
Is determined based on the signal in the above, and the output is sent to the synchronization circuit 9a.

FIG. 4 shows the synchronization circuit 9a of FIG. 3 in detail. This synchronizing circuit 9a is similar to the conventional synchronizing circuit 9 of FIG.
4 to form a sine wave signal for use in the present embodiment, and comprises a cos controller in the upper half and a sin controller in the lower half of FIG. The cos controller is for forming a cos signal synchronized with the input signal.
Table memory 31 consisting of a first multiplier 3
2, a first integrator 33, a second integrator 34, a second
, A first adder 36, and a second adder 3
7, a first reference signal generator 38, and a first address integrator (integrating means) 39. The sin controller is
a line 40 for forming a sin signal synchronized with the cos signal and receiving the output of the cos table memory 31 of the cos controller;
A table memory 41, a third multiplier 42, a third integrator 43, a fourth multiplier 44, and a third adder 45
And a pull-in / trip-off controller 46, a fourth adder 47, a second reference frequency signal generator 48, a second address integrator 49, and an output D / A conversion circuit 55. The pull-in and trip-out controller 46 includes a switch 50, a subtractor 51, a limiter 52, a fourth integrator 53,
And a one-sample delay circuit 54. The synchronizing circuit 9a composed of a cos controller and a sin controller has a CPU, RA
M and a microcomputer including a ROM. Therefore, FIG. 3 is an equivalent circuit diagram or a functional block diagram of the microcomputer.

The outline of the operation of the cos controller is as follows. Address integrator 39 and cos table memory 31
Generates a cos signal. The frequency α of the cos signal is proportional to the input α ′ of the address integrator 39. A first multiplier 32 and a first integrator 33 obtain a cosine term first coefficient a ₁ of a Fourier series using an input signal and a cos signal input from the input circuit 30. Since a ₁ is a function of the phase difference between the cos signal and the input signal, the frequency of the cos signal is automatically adjusted using a proportional-integral compensator used in linear control theory so that a ₁ converges to zero. I do. This compensator includes a second integrator 34 and a second multiplier 35. The outputs (a _1p and Δf) of these compensators are added by a first adder 36, and a second adder 37 is added to this output.
, The reference frequency signal f0 is added, and α '(n) = Δf +
a _1p + f0 is input to the first address integrator 39.
The address integrator 39 outputs an address signal θ (n) for reading data from the cos table memory 31 at a speed according to the frequency command α ′ (n). The cos signal read from the cos table memory 31 is supplied to the first multiplier 3
2 and the third multiplier 4 of the sine controller at the same time.
Enter 2 Next, each block of the cos controller will be described in more detail.

The input circuit 30 has a periodic input signal Vs (t) = Vmsin 2πft (for example, a 50 Hz sine wave AC voltage (commercial AC voltage)), where Vm is the maximum amplitude, f is the frequency, and t is shows the time.) was sampled at a predetermined sampling period Ts, which was analog-to-digital conversion _{Vs (n) = Vmsin ω f} n Ts ( where _{ω f = 2πf, n = 0,1,2} , · ..). Here, the input signal Vs (t) is shown only by a fundamental wave composed of a sine wave, but in practice, a distorted wave AC may occur due to mixing of noise and harmonic components.

The cos (cosine wave) table memory 31
A read-only memory (ROM) in which a table of cosine wave data is stored, and a read address θ (n)
Cos signal Vr (n) = cos ω _α n Ts
(Here, ω _α = 2πα, α is the frequency of the cos signal) and outputs data of cos θ (n). The read address θ (n) corresponds to the phase amount, and its change amount (differential amount)
Is the frequency of the cos signal. Here, instead of the cos data, the data of the sine wave sin θ corresponding to the waveform obtained by shifting the sine wave by 90 degrees may be stored in the ROM. In this embodiment, the 360-degree section of the cosine wave is divided into 2048 parts,
2048 samples (data) are stored in the ROM. For example, if address θ (n) = 0 is specified, cos 0 °
= 1 is output from the ROM, and if an address θ (n) = 512 is specified, data indicating cos 90 ° = 0 is output. Note that data corresponding to 90 to 450 degrees of the cosine wave, that is, data of a sine wave (sin) can be stored in the ROM. In this case, when address 0 is specified, data of sin 0 ° = 0 is output from the ROM, and when address 512 is specified, data of sin 90 ° = 1 is output. The address integrator 39 as address means is equivalent to an integrator represented by a pulse transfer function K ₃ Z / (Z−1), and converts α ′ (n) input as a frequency amount into a phase amount θ ( n). As described above, since the derivative of the phase is the frequency, the integral of the frequency becomes the phase. Therefore, θ (n) can be obtained by integrating α ′ (n). As the value of α '(n) increases (the frequency increases), the slope of θ (n) becomes steeper. By adjusting the value of α '(n), the frequency of the cos signal Vr (n) can be changed. In fact, the address integrator 39
Then, the address θ (n) is expressed by the following equation, Ts = 256 μsec
It is calculated every time. θ (n) = θ (n−1) + α ′ Here, n is an ordinal number indicating the sampling time. θ
(N-1) indicates the address at the previous sampling point. When it is desired to set the frequency α of the cos signal to 50 Hz, α ′ can be calculated as follows. α '= 2048Ts 50 = 26.44 By adding 26.44 to θ (n−1) every Ts cycle according to the above-described equation of θ (n), 20 msec (1/50 Hz)
Later, θ (n-1) becomes 2048 which is the address of one cycle of the cosine wave data. If α ′ is larger than 26.44, θ becomes 2048 before 20 msec, and the frequency becomes higher. If α ′ is smaller than 26.44, 2
Since θ = 2048 after 0 msec, the frequency decreases.

A first multiplier 32 as first multiplying means
Is to multiply the input signal Vs (n) by the cos signal Vr (n) to obtain an output V0 (n) of Vs (n) .Vr (n).

The integrator 33 as the first integrating means is for integrating the output of the first multiplier 32 in a fixed manner to obtain the following equation (1).

[0016]

(Equation 1)

This equation (1) corresponds to the case where _k of a k is set to 1 in the equation for calculating the coefficient a _k of the cosine term of the Fourier series. The expression for the cosine term and coefficient a _k is shown below.

[0018]

(Equation 2)

If the first integrator 33 is represented as a pulse by a transfer function, it becomes K ₁ Z (Z−1). The value of a ₁ is the input signal Vs
And the cos signal Vr. here,
Vs = the _{Vmsin (ω α t + φ)} , which upon calculated by substituting the equation (1), next to a ₁ = Vmcos φ, a ₁ is found to be a cosine function of the phase difference. Hereinafter, a ₁ when the phase difference is 90 °, 0 °, and 180 °
The following shows an example of the waveform.

When the input signal Vs (t) shown in FIG. 6A and the cos signal Vr (t) shown in FIG. 6B have the same frequency and a phase difference of 90 degrees, the first multiplier 32 the output of V0 (t) is a sine wave of frequency 2 [omega _alpha as shown in FIG. 6 (C), output a ₁ multiplication output V0 (t) is the definite integral from 0 to 2π shown in FIG. 6 (C) is zero and Become.

The input signal Vs (t) and the cos signal Vr
(T) has the same frequency and the same phase as shown in FIGS. 7A and 7B, the output V0 of the first multiplier 32 is output.
(T) has a frequency 2 [omega _alpha as shown in FIG. 7 (C),
The minimum value becomes a sine wave of zero, and this is the first sine wave in the interval of 0 to 2π.
Output a ₁ was constant integrated by the integrator 33 is a positive value (if the maximum value of the cos signal is 1 maximum value Vm of the input signal) as shown in FIG. 7 (D) becomes.

The input signal Vs (t) and the cos signal Vr
8 (A) and 8 (B), when the frequencies are the same and opposite phases, as shown in FIGS.
(t) has a frequency 2 [omega _alpha as shown in FIG. 8 (C), the maximum value of a sine wave of zero. Therefore, when the waveform of FIG. 8C is definitely integrated by the first integrator 33 in the interval of 0 to 2π, FIG.
Output a ₁ a negative value as shown in (D) is obtained. When there is a difference in frequency between the input signal Vs and the cos signal Vr, that is, when the phase difference between the two changes with time,
The output of the first integrator 33 is a ₁ (n) Vmcos (2πΔ
ft) and changes with time.

The input signal Vs (n) and the cos signal Vr (n)
Preparative to converge to zero the value of a ₁ as the synchronization status of the phase difference of 90 degrees as shown in FIG. 6 (A) (B) is required to operate the reading speed (frequency) of the cos table memory 31. In the present embodiment proportional often used in feedback automatic control of the linear control system to automatically zero a ₁ -
Use an integral (PI) compensator. The second integrator 34 as a second integrating means is a pulse transfer function _KipZ / (Z−
This is an integral compensator shown in 1) for compensating for a frequency difference. The second multiplier 35 is a proportional compensator and compensates for a phase difference.

The integrator 34 as a second integrating means is a ₁
There is in order to converge to zero a ₁ even when the time varying (if there is a frequency difference and Vr and Vs), is intended to obtain an output Δf indicating the amount of frequency compensation. When it is made by software, it is made to execute a process according to the following equation (2). Δf (n) = Δf (n−1) + _Kip · a ₁ (n) (2) In this equation (2), Δf (n−1) is the output of the second integrator 34 at the immediately preceding sampling point. And K _ip · a
₁ (n) is obtained by multiplying the current value of a _{1 by} the gain K _ip . Therefore, even if the state shown in FIG. 6 is established at some point and a ₁ becomes zero, Δf (n), that is, Δf does not become zero but becomes a constant value. When a ₁ is zero, the output Δf of the second integrator 34 is a value proportional to the difference between the fundamental frequency f of the input signal Vs (n) and the reference frequency signal f 0.

A multiplier 35 as a second multiplication means obtains an output a _1p indicating the amount of phase compensation, and has a gain of K
It can also be called a pp amplifier, and is formed to execute the operation of the following equation (3). a _1p (n) = Kpp · a ₁ (n) That is, the second multiplier 35 outputs the output a ₁ of the first integrator 33.
Is multiplied by a coefficient Kpp. Accordingly, in the case of the state shown in FIG. 4, the output a _1p of the second multiplier 35 becomes zero.
Like a linear control system, this proportional compensator serves to improve the stability and responsiveness of the feedback system. In the state shown in FIG. 6, a _1p becomes zero. cos
The frequency and phase of the signal Vr (t) are controlled by the output Δf of the second integrator 34 and the output a _1p of the gain multiplier 35 described above. When the sum of Δf and a _1p is 1, 1 /
2048Ts = 1.9073 Hz, the frequency increases,
α becomes 51.9073 Hz. When the added value of Δf and a _1p is negative, the frequency α decreases by 1.9073 Hz and becomes 48.0.
927 Hz. In addition, 1 / 2048Υs = 1.907
3 is obtained as follows. Δf + a _1p = 1 Since a _1p = 0 during synchronization, Δf = 1 Δf / (2048.Ts) = (2048.Ts) As is clear from the above, co is centered on the fundamental frequency 50 Hz.
The frequency α of the s signal Vr (t) can be increased or decreased.

First and second adders 36 and 37 are provided as first adding means. The first adder 36 adds the output Δf of the integrator 34 and the output a _1p of the integrator 35,
This is to obtain a correction command signal. The second adder 37 adds the output of the first adder 36 and the output f0 of the reference frequency signal generator 38 to obtain a frequency command signal of the following equation (4). α ′ (n) = Δf (n) + a _1p (n) + f0 (n) (4) α ′ (n) in the expression (4) is sent to the address integrator 39 as a frequency command value, 39 outputs an address signal θ (n) at a speed corresponding to the frequency command value.

The reference frequency signal generator 38 receives the input signal V
A signal indicating a reference frequency (for example, 50 Hz) f0 which is the same as or close to the fundamental frequency f of s (t) is generated.

The si in the sine controller in the lower half of FIG.
n table memory 41, third multiplier 42, third integrator 43, fourth multiplier 44, third adder 45, fourth adder 47, reference frequency signal generator 48, and second Are the cos table memory 31, the first multiplier 32, the first integrator 33, the second multiplier 35, the first adder 36, and the second Adder 37, reference frequency signal generator 38, and first
Has the same function as the address integrator 39 of FIG. That is, the lower half of the sine controller uses one input of the third multiplier 42 as the output of the cos table memory 31, and makes the output of the second integrator 34 input to the third adder 45. It differs from the cos controller in the upper half in that a point, pull-in and trip controller 46 is provided, and the others are substantially the same as the cos controller. Therefore, si
A detailed description of substantially the same parts of the n controller as the cos controller will be omitted.

A sin table memory 41 as an output frequency signal generating means stores a sine wave signal (data) and outputs a sine wave signal sin2πβ ₁ t in accordance with the address designation of the second address integrator 49. to output the result as a signal, is formed so as to be able to change the frequency beta ₁ of the output signal by varying the speed of addressing (sine wave signal).

The multiplier 42 as the third multiplying means includes co
The reference signal of the line 40 obtained from the s table memory 31 is multiplied by the output signal obtained from the sine table memory 41 to obtain an output including the same contents as the output of the first multiplier 32. The reference signal on the line 40 is a signal synchronized with the input signal (commercial AC voltage).

The integrator 43 as the third integrating means performs the same integration processing as that of the first integrator 33 on the output of the multiplier 42.

A multiplier 44 as a fourth multiplying means obtains the amount of phase compensation based on the output of the integrator 43, similarly to the multiplier 35.

An adder 45 as a second adding means adds the output Δf of the second integrator 34 and the output (phase compensation amount) of the multiplier 44 to a frequency correction command value, that is, a frequency adjustment amount a _1i. Is what you get. Therefore, the third adder 45 and the circuit means on the input side can be called a frequency correction command signal creating means.

In the synchronizing circuit 9a shown in FIG. 4, the frequency correction command value a _1i obtained from the third adder 45 is not supplied to the fourth adder 47 as it is, but is controlled by the pull-in / trip-off controller 46. Correct and supply. The contact a of the switch 50 of the pull-in / trip-off controller 46 is connected to the adder 45, the contact b is connected to the ground, and the common output terminal is connected to a subtractor 51 as a subtraction means. The switch 50 is controlled by the output of the commercial frequency abnormality determination circuit 11a in FIG. 3, and when the output frequency signal output from the sine table memory 41 is synchronized with the input frequency signal (commercial AC voltage), the contact a is turned on, and the output frequency is The contact b is turned on when the synchronization between the signal and the input frequency signal is released. The commercial frequency abnormality determination circuit 11a for determining whether to synchronize the output frequency signal with the input frequency signal includes an absolute value circuit 60, a reference voltage source 61, and a voltage comparator 62 as shown in FIG. The absolute value circuit 60 is connected to the second integration circuit 34 in FIG. 4, and detects the absolute value of the frequency correction command value Δf. The comparator 62 compares the output of the absolute value circuit 60 with the voltage of the reference voltage source 61, and when the absolute value becomes larger than the reference voltage, generates an output indicating the cancellation of synchronization.
Is turned off and the contact b is turned on. When the absolute value is smaller than the reference voltage, an output indicating synchronization is generated,
The contact a of the switch 50 in FIG. 4 is turned on, and the contact b is turned off. The frequency correction command value is supplied to the reference frequency signal generator 38.
Since the reference frequency f0 corresponds to the difference between the fixed free-running frequency and the input frequency, the comparator 62 monitors the change in the input frequency.

The subtraction circuit 51 in FIG. 4 subtracts the corrected frequency correction command value (frequency correction operation amount) obtained from the integrator 53 one sampling period Ts earlier from the frequency correction command value to obtain a value indicating the remaining correction amount. Is output.

The limiter 52 limits the frequency correction command value (correction frequency amount f) with a positive limit value + fa and a negative limit value -fa as shown in FIG. Therefore, when the frequency correction command value is large, it is not output as it is, but a value of the limit level fa or -fa is output. The integrator 53 integrates the output of the limiter 52, and this output is used by the fourth adder 4 as a third adding means.
7 The limiter 52 is configured so that the limit values fa and -fa can be changed. Details of the operation of the pull-in and trip-out controller 46 will be described later.

The corrected frequency correction command value β obtained from the pull-in / trip-off controller 46 is input to a fourth adder 47 as a third adding means, and a second reference frequency signal generator 48 It is added to the obtained reference frequency signal f0. Since the second reference frequency signal generator 48 generates a command signal of the same frequency f0 (50 Hz) as the first reference frequency signal generator 38, the first and second reference frequency generators 48 are used. One of them can be omitted and shared. The output of the adder 47 is the sin table memory 4
This is information for determining the frequency of the frequency signal output from 1. The second address integrator 49 has a function similar to that of the first address integrator 39.
7, the address of the sin table memory 41 is specified.

Next, the operation of the pull-in / trip-off controller 46 will be described with reference to FIGS. FIG. 9 shows an ideal change of the correction correction command value (frequency operation amount) β corresponding to the frequency correction command value a _1i when a relatively large frequency difference between the input frequency signal and the output frequency signal is eliminated. Thus, when the frequency manipulated variable β gradually changes linearly,
Since a constant frequency change speed can be accurately obtained and the output frequency changes smoothly, the output frequency of the inverter 3 also changes smoothly, and the output waveform of the inverter 3 can be maintained as an approximate sine wave.

As a modification of the pull-in and trip-off controller 46 in FIG. 4, if a controller 46a having only the switch 50 is provided as shown in FIG. 10, the frequency operation amount β changes stepwise as shown in FIG. However, smooth control becomes impossible.

When a pull-in / trip-off controller 46b provided with a low-pass filter (LPF) at the output stage of the switch 50 as shown in FIG. 12 is provided with a time constant as shown in FIG. The frequency manipulated variable β is obtained. However, not only does the time required to obtain the predetermined frequency become long, but also the frequency manipulated variable β cannot be changed linearly as shown in FIG.

FIG. 14 shows a pull-in / trip-off controller 46c having a filter 56a obtained by modifying the low-pass filter 56 of FIG. Low pass filter 56a here
Are first and second multiplying gains K1 and K2 in addition to the adder 51, the integrator 53, and the delay circuit 54 according to the present embodiment.
Are provided. In the controller 46c of FIG. 14, the process is executed for each sampling period Ts, so that the characteristic of increasing β in FIG. 13 step by step is obtained. However, also in FIG. 14, β does not increase linearly.

FIG. 15 is obtained by adding a limiter 52 to FIG. 14 similarly to the present embodiment. In the pull-in and trip-off controller 46d of FIG. 15, β changes according to the following equation. β (n) = K1 · a _1i (n) −K2 · β (n−1) + β
(N-1) the limiter 52 in FIG. 15 is the β equation K1 · a _1i of (n)
The magnitude of (n) -K2.beta. (N-1) is represented by fa and -fa.
Restrict with. In the controller 46d of FIG.
When No. 2 is not performing the limiting operation, β changes with a delay of the filter constant. When the frequency of the input signal changes within prescribed change rate, although the synchronization of the input signal and the sine wave signal is required to be maintained, for the filter delay, a _1i
The change of (△ f) is not quickly transmitted to β, and synchronization is not maintained.

Therefore, in the controller 46 of the present embodiment, the gains K1 and K2 in FIG. 15 are set to 1 as shown in FIGS. Accordingly, in FIG. 16, when the limiter 52 is not operating, a _1i = β, and the frequency correction command value a _1i is output as the frequency operation amount β without delay.

FIG. 17 shows a switch 5 for synchronization pull-in.
The operation when the input frequency signal is higher than the output frequency signal when the contact a of 0 is turned on is shown. When the frequency difference between the two frequency signals when the contact a of the switch 50 is on, that is, the frequency correction command value a1i is larger than the limit value fa of the limiter 52, one sampling period Ts of t0 to t1, t1 to t2, and t2 to t3. The frequency manipulated variable β changes by fa every time. That is, an output of β (n) = fa + β (n−1) is obtained. Since the change width of each stage during the limiter operation period t0 to t3 is fa, the envelope of the period t0 to t3 is a straight line similarly to the ideal characteristic of FIG. During the limiter non-operation period after t3, the correction command value _a1i is immediately output as the operation amount β.

FIG. 18 shows that the input frequency is
The operation when the contact a of the switch 50 of the controller 46 is turned off and the contact b is turned on (in the case of synchronization release) because the output frequency has risen greatly from the output frequency of the controller 46 is shown. In this case, during the limiter operation period from t0 to t3, the frequency manipulated variable β decreases fa for each sampling period Ts, and β = −fa +
The output according to β (n-1) is obtained, and the reference frequency generator 3
It gradually approaches the reference frequency (free-running frequency) determined in steps 8 and 48. In the limiter non-operation period, β (n) = −
β (n−1) + β (n−1), the trip is completed when β (n) = 0, and the state becomes the free-running frequency state.

Limiter limit value fa for frequency variation
Can be determined, for example, as follows. When β is 1, the frequency change amount is equivalent to the calculation period T in the address circuit 49 composed of an integrator represented by Tse / (Z-1).
When se is 256 μsec and the number of data of sin is 2048, 1 / (2048 Tse) = 1.9073 Hz. When the calculation cycle Ts of the integrator 53 is 20 msec, β
Changes by 1, the rate of change is (1.9073 Hz) /
20 msec = 95.365 Hz / sec. Therefore, when the frequency change rate is desired to be 0.5 Hz / sec, fa is set to the following value. fa = [desired frequency change amount / ｛1 / (sin data number · T
se · Ts)｝] · [0.5 / 95.365] = 52.4
3 × 10 ^-3 Hz / sec

FIG. 19 shows steps in the case where the synchronization determination circuit 12a of FIG. 3 is constituted by software. First, as shown in step 71, it is determined whether or not the absolute value of the input of the limiter 52 is equal to or larger than the limit value fa. YES at step 71
Is obtained in step 72, the output of the limiter 52 is set to fa. In step 73, a signal indicating asynchronous is generated, and the switching of the switch 4 in FIG. 3 is prohibited. When the output of step 71 is NO, in step 74 a value indicating the phase shift between the input signal and the output signal, that is, the output b of the integrator 43
It is determined whether or not 1 is smaller than a predetermined allowable value △ φ _1im , and when an output of YES indicating that the value is smaller is obtained, a signal indicating synchronization is output as shown in step 55. . The signal indicating synchronization in step 55 is used, for example, as a switching permission signal for the switch 4 in FIG. When a NO output indicating that the phase shift is large is obtained in step 74, a signal indicating asynchronous is generated in step 73.

As is clear from the above, this embodiment has the following advantages. (B) Limit value fa of the limiter 52 whose physical meaning is clear
Can be obtained by calculation, and the output frequency change speed can be made exactly constant at the time of frequency pull-in and trip-off. (B) The frequency change speed can be easily changed by changing the limit value fa of the limiter 52. (C) Since only multiplication, addition, and subtraction are used, software realization is simplified. (D) Since an edge detector or the like becomes unnecessary, malfunction due to noise is reduced.

[0049]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) Forming output frequency signal by digital processing
Instead of performing the / A conversion, a part or the whole of FIG. 4 can be an analog circuit. (2) In the embodiment, the arithmetic units shown in FIG. 4 are not provided individually but are subjected to time-division processing by one microcomputer, but these may be provided individually. (3) When the inverter control circuit 13 of FIG. 2 is formed by a digital circuit, the D / A converter 55 of FIG. 4 can be omitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional power supply device.

FIG. 2 is a block diagram illustrating a synchronization circuit of FIG. 1;

FIG. 3 is a block diagram illustrating a power supply device according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a synchronization circuit of FIG. 3;

FIG. 5 is a block diagram illustrating a frequency abnormality determination circuit of FIG. 3;

[6] when the input signal and the reference signal has a phase difference of 90 degrees Vs (t), Vr (t ) V0 (t), is a waveform diagram illustrating a ₁ in an analog state.

FIG. 7 shows Vs when the input signal and the reference signal are in phase.
(T), Vr (t) , V0 (t), is a waveform diagram showing an analog state _{a 1.}

FIG. 8 shows Vs when the input signal and the reference signal are out of phase.
(T), Vr (t) , V0 (t), is a waveform diagram showing an analog state a _1.

FIG. 9 is a diagram showing a change in an ideal frequency manipulated variable β.

FIG. 10 is a circuit diagram showing a controller including only switches.

FIG. 11 is a waveform chart showing an output of the controller of FIG. 10;

FIG. 12 is a block diagram showing a controller of a switch and a filter.

FIG. 13 is a waveform chart showing an output of the controller of FIG.

FIG. 14 is a block diagram showing a controller in which the filter of FIG. 12 is modified.

FIG. 15 is a block diagram showing another controller in which the filter of FIG. 12 is modified.

FIG. 16 is a block diagram showing a controller of the embodiment.

FIG. 17 is a waveform chart showing an output of the controller of FIG. 16;

FIG. 18 is a waveform diagram showing an output of the controller of FIG. 16 in another state.

FIG. 19 is a flowchart showing the operation of the synchronization determination circuit of FIG. 3;

[Explanation of symbols]

 41 sine table memory 46 pull-in and trip-out controller 52 limiter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 7/48 H03L 7/14

Claims (6)

(57) [Claims] An output signal having a periodicity synchronized with an input signal having a periodicity and an asynchronous output signal are generated, and a rate of frequency change of the output signal is controlled. A frequency correction command signal generating means for generating a frequency correction command signal corresponding to a difference between the frequency of the input signal and the frequency of the output signal; and Supplying the frequency correction command signal obtained from the frequency correction command signal creating means when synchronizing a signal with the input signal, and supplying the frequency correction command signal when releasing the synchronization between the output signal and the input signal. A switch for stopping the operation, a subtraction unit, a limiter unit, an integration unit, and a delay unit. The subtraction unit subtracts the output of the delay unit from the output of the switch. The limiter means limits the output of the subtraction means to a predetermined level or less, the integration means integrates the output of the limiter means, the delay means delays the output of the integration means, and corrects the output from the integration means. Corrected frequency correction command signal generating means configured to output the corrected frequency correction command signal, reference frequency command signal generating means for generating a reference frequency command signal for setting the frequency of the output signal to a reference value, Adding means for adding the corrected frequency correction command signal to the reference frequency command signal; and a frequency corresponding to an added value of the reference frequency command signal and the corrected frequency correction command signal obtained from the adding means. Output signal generating means for generating the output signal having the following. 2. An output signal having a periodicity synchronized with an input signal having a periodicity and an asynchronous output signal are selectively generated, and a rate of frequency change of the output signal is controlled. An input means for inputting a periodic input signal (Vmsin 2πft); and a periodic reference signal (cos) consisting of a sine wave or a cosine wave.
s 2παt), and a first address integrating means for outputting an address of the reference signal from the reference signal memory to the reference signal (cos 2).
παt), and the reference signal (cos
Reference signal generating means configured to be able to change the frequency (α) of 2παt) by the input (α ′) of the first address integration means; and the input signal (Vmsin 2πft) and the reference signal (α). cos
2παt), and an output (Vmsin 2πft) obtained from the first multiplication means.
.Cos 2παt)) to obtain an output (a ₁ ) corresponding to a first coefficient of a cosine term or a sine term of a Fourier series, and an output (a) obtained from the first integration means. a ₁ ) is integrated to obtain an output (Δf) indicating the frequency compensation amount, and the output (a ₁ ) obtained from the first integration means is multiplied by a coefficient (Kpp). Second multiplying means for obtaining an output (a _1p ) indicating phase compensation; reference frequency signal generating means for generating a reference frequency command signal for obtaining a constant reference frequency (f0); A first address output (α ′ = corresponding to the sum of the output (Δf), the output (a _1p ) of the second multiplying means, and the output (f0) of the reference frequency command signal generating means. f0 + △ f + a _1p) give the output for this first address (alpha ') of the first Output signal having a first adding means for supplying the integrating means for dresses, the periodicity consisting sine wave or cosine wave (si
n 2πβ ₁ t), and an output memory for generating the output signal from the output memory, including a second address integrator for outputting an address of the memory. Output signal generation means formed so that the frequency (β ₁ ) of the reference signal generation means can be changed by the input (β ′) of the second address integration means; and the output of the reference signal generation means and the output signal A third multiplying means for multiplying, and an output obtained from the third multiplying means,
A third integrating means for performing the same integration processing as the integrating means, and a coefficient (Kpp1) added to the output obtained from the third integrating means.
A fourth multiplication means for obtaining an output indicating the phase compensation by multiplying the output of the second multiplication means and a third correction means for obtaining a frequency correction command signal by adding the output of the second integration means and the output of the fourth multiplication means.
And the third means for synchronizing the output signal with the input signal.
A switch for supplying the frequency correction command signal obtained from the adding means, and for stopping the supply of the frequency correction command signal when releasing the synchronization between the output signal and the input signal; a subtracting means, a limiter means, 4) integrating means and delay means, wherein the subtracting means subtracts the output of the delay means from the output of the switch, and the limiter means limits the output of the subtracting means to a predetermined level or less; The fourth integrating means integrates the output of the limiter means, the delay means delays the output of the fourth integrating means, and outputs a corrected frequency correction command signal from the fourth integrating means. Corrected frequency correction command signal creating means, and the corrected reference frequency command signal obtained from the reference frequency command signal generating means or a separately provided reference frequency command signal generating means. A second address output (β ′) by adding the frequency correction command signal to the second address integrating means for supplying the second address output (β ′) to the second address integrating means. And a periodic signal control device. 3. The input signal is a commercial AC power supply voltage or a signal synchronized therewith, and the output signal is an inverter control reference signal for determining an output voltage waveform of the inverter. 3. The periodic signal control device according to 1 or 2. 4. The periodic signal control device according to claim 1, wherein at least a part of the periodic signal control device is formed by a digital processing circuit. 5. A frequency abnormality determining means for controlling the switch, the frequency abnormality determining means comparing an absolute value of an output of the second integrating means with a reference voltage, and 3. The periodic signal control device according to claim 2, wherein the switch is controlled so that synchronization is released when a value becomes higher than the reference voltage. 6. A commercial AC power supply for providing the input signal, and an inverter controlled by the output signal.
A switch for selectively connecting the commercial AC power supply and the inverter to a load, and determining whether or not the output voltage of the inverter is synchronized with the voltage of the commercial AC power supply. And a synchronization judging means for controlling the switch so that the inverter is connected to the load when the operation is being performed. The synchronization judging means judges that the absolute value of the input of the limiter is a limit value of the limiter ( fa) a limiter input determining means for determining whether or not the output signal is equal to or greater than an output (b1) of the third integrating means (43) indicating a phase shift between the input signal and the output signal.
_φ1im ) to determine whether the absolute value is smaller than the limit value (fa) or when the output (b1) of the third integration means (43) is larger than the limit value (fa). When the value is not smaller than the predetermined allowable value (△ φ _1im ), an output indicating asynchronous is generated.
6. The periodic signal control device according to claim 2, wherein an output indicating synchronization is generated when is smaller than the predetermined allowable value (△ φ _1im ).