JP3235418B2 - Storage controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage control device for controlling data transfer between a processing device and a storage device, and more particularly to a storage control device for temporarily storing data related to data transfer and preventing data access failure. The present invention relates to a storage control device having a cache memory capable of performing a closing operation.

2. Description of the Related Art Conventionally, in a storage control device for controlling data transfer between a processing device and a storage device, a cache memory for temporarily storing data relating to the data transfer is provided to facilitate the above data transfer. That is being done. In a storage control device having a cache memory, some countermeasures must be taken when an error such as an access error occurs in the cache memory. As an example of such a measure, a technique called blockage has been proposed. Blocking means prohibiting use of a portion of the cache memory where failures frequently occur. On the other hand, regarding the improvement of data reliability in cache memory,
Japanese Unexamined Patent Publication No. Hei 5-189314 describes a cache memory control method for a storage control device having a plurality of cache memories backed up by a battery. In this method, data read from the storage device is stored in any one of the plurality of cache memories, and data to be written to the storage device is stored in any two of the plurality of cache memories, thereby preventing failure. Improves data assurance. In this method, since data is protected from a failure by selectively using a plurality of cache memories as described above, when a failure occurs in the cache memory, the cache operation is continued using a non-failed cache memory. However, in order to recover the failed cache memory, the storage control device and the storage device are temporarily stopped, and the cache memory is entirely closed together with the cache memory.

The above-mentioned prior art does not take into account the above-described recovery processing when a cache memory failure occurs. When a failure occurs in the cache memory, it is necessary to close the failed part in order to avoid data loss. However, in the above-described conventional technique, the failed part to be blocked is excluded from the cache memory configuration of the storage control device. When executing the closing process, there is a problem that the storage control device and the storage device must be stopped. Further, in the above-mentioned conventional technology, since the inside of each cache memory is not divided and managed, even if the faulty part is a part in the cache memory, the part closed at a time is the same as the entire cache memory. turn into. For this reason, the use of even the available portion in the cache memory is prohibited by the closing process, and there is a problem that the process is wasteful and inefficient. SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a method of reading / writing data from a processing device without stopping a storage control device and a storage device.
It is an object of the present invention to provide a storage control device capable of closing a cache memory in a state where a write request can be accepted. Still another object of the present invention is to provide a storage control device capable of partially closing only a failed part in a cache memory.

In order to achieve the above object, the present invention resides between a processing device and a storage device for storing data used by the processing device. A storage control device that controls data transfer between the storage device and a cache memory configured to include a plurality of blocks, and that holds a part of data to be stored in the storage device; Control information for managing a corresponding block, and control information corresponding to a block in use and reserved for data used by the processing device, and data used by the processing device. Memory that stores management information that is managed separately from control information corresponding to unused blocks that have not been reserved for operation, and failures caused by operating the management information Characterized in that a control means for performing a blocking process of the block in the cache memory with. In the above configuration, the cache memory is divided into a plurality of unit memories each including a plurality of blocks, and the control unit executes the block closing process by a unit including a block in which a failure is detected. You may make it implement for all the blocks in a memory. Here, triggered by the frequent occurrence of cache access errors, a cache closing process is started in order to close the unit memory including the portion where the access errors frequently occur. In the cache closing process, the used or unused cache management table is prohibited from being used for the read / write process. As a method of prohibiting use, when the unused cache management table is managed by a queue using bidirectional pointers, the cache management table in the unit memory to be closed is referenced in address order, and the cache management table is locked. While being acquired, use of unused / unused cache management tables is prohibited. Also,
As another method, when the unused cache management table is managed by a queue using a unidirectional pointer, the cache management table in the unit memory to be closed is referred to in order of address, and the cache management table lock is acquired. However, only the cache management table in use is prohibited. Next, the unused cache management table queue
After the lock of the queue is obtained, the cache management table is referred to from the beginning, and the use of the unused cache management table is prohibited. In addition, during the cache closing process, in the cache allocation process, new allocation of the cache management table in the unit memory to be closed to read / write processing is prohibited.
As still another method, when there are two cache memories each including a plurality of blockable unit memories, if both cache memories are normal immediately before the failure occurs, the failed cache memory is deleted. If one of the cache memories is normal just before the failure occurs and one of the two cache memories is normal immediately before the failure occurs, one of the above two types of the closure processing is performed according to the structure of the unused cache management table queue. Or do.

According to the present invention, it is possible to close a cache memory for each unit memory which is a component thereof.
Therefore, there is no need to block the entire cache memory for a local failure, and the cache memory can be used effectively. Also, even during the closing process of the unit memory constituting the cache memory, the control information of the storage control device is excluded, so that the read / write from the processing device is performed.
A write request can be accepted.

Embodiments of the present invention will be described below with reference to the drawings.
You. <Embodiment 1> FIG. 1 is a diagram showing a system configuration of this embodiment.
is there. This information processing system includes a processing device (CPU) 1,
Storage device 2 and connection to processing device 1 and storage device 2
The storage control device 3 is configured to include the storage control device 3. Processing device 1
The storage device 2 can use a known technique.
The storage controller 3 performs processing via the channel adapter 31.
Connected to the device 1 and via the drive adapter 32
Connected to the storage device 2. Channel adapter 31 and
And the drive adapter 32 are provided in the storage controller 3 respectively.
Are provided in plurality. The storage controller 3 includes a plurality of channels.
Panel adapter 31, a plurality of drive adapters 32,
A flash memory 37 and a control memory 38 via a bus 39.
It has a connected configuration. The channel adapter 31
Channel control unit 33, read / write control unit 35-1,
It has a closing control unit 36. Read / write control unit 35-
1 is a resource from the processing device 1 via the channel control unit 33.
Accepting read / write requests, and processing unit 1 and storage system
Control of data transfer with the control device 3 is performed. Closed system
The control unit 36 is a cache for closing the cache memory 37.
It has a queue closing process 361. The drive adapter 32
Drive control unit 34 and read / write control unit 35
2 The read / write control unit 35-2 has a dry
Data input / output to / from the storage device 2 via the
And so on. The cache memory 37 transfers
The data is divided into blocks with the capacity of one data length.
You. The size of the block is determined by the storage device 2 and the cache memory.
It is unique to the moat 37. The unit memory 371 stores the block
Are grouped by collecting an appropriate number of
You. If the number of groups reaches N,
The cache memory 37 is composed of N unit memories 371.
Will be done. The cache memory 37 uses this unit memory.
It is possible to close each of the moles 371. Control memory
38 is a blockage process control information 381, a cache configuration state
Information 382 and cache management information 383
You. The read / write control units 35-1 and 35-2 are:
In any case, the cache allocation processing 351 and the cache
Access processing 352. Cache allocation processing
The processing 351 is a cache memory required for read / write processing.
An area in the memory 37 is secured. Cache access processing
The processing 352 is a cache memory in read / write processing.
Writes and reads data to and from memory 37
U. The read / write processing is performed as follows. Lee
In read processing, a read request from the processing device 1 is read /
Received by the site control unit 35-1 and read / write this
The data is transferred to the control unit 35-2. Read / write control unit 35
-2 is from the storage device 2 according to the transferred read request.
The data is stored in the cache memory 37. Stored
Data is processed by the read / write control unit 35-1.
The data is transferred to the device 1. On the other hand, in the write processing, the processing device
Read / write control unit that receives a write request from
35-1 temporarily stores the write data from the processing device 1.
Store on cache memory 37 and write to processing device 1
Reports the end of processing. The stored write data is processed.
Read asynchronously with the read / write request from the logical device 1
/ Write to storage device 2 by write control unit 35-2
It is. FIG. 2 is a diagram showing details of the cache management information 383.
It is. The cache management information 383 includes a cache memo.
A cache management table 3831 for managing the
I do. The cache management table 3831 has a cache
Exists for each block 3711 that is a memory allocation unit
And the unit memory 371 constituting the cache memory 37
Control memory 3 according to the arrangement order of the blocks 3711
8 lined up. Also, the cache management table 38
31 indicates that the cache management table 3831
Lock information indicating whether or not the lock
Information 38311 for storing information, unused / used
State information 3 indicating one of three states of medium / use prohibited
8312, corresponding block address 38313, arrangement
Key to manage the management table by queue.
Forward pointer 3 pointing to the management table one ahead on the menu
8314 and a backward point to the next management table
The center 38315. Status information is unused
On the block corresponding to the cache management table 3831
Has no data. Unused cache management
Table 3831 is based on queues with bidirectional pointers.
Is managed. This queue is an unused cache
Specified by the management table queue header 3832.
Unused cache management table queue header 3832
Indicates that the unused cache management table queue is
Lock information indicating whether or not it has been locked by processing
Lock information area 38321 to be stored, key at the top of the queue
Area for storing the address of the cache management table 3831
Area 38322 and the cache management data at the end of the queue.
Area 38323 for storing the address of the
Have. This queue is used for read / write processing.
Is referred to when writing data to the cache memory 37.
You. Cache management table whose status information is in use
Data exists on the block corresponding to the
You. The cache management table 3831 in the used state is
Disk associated with address in storage device 2
It is connected to the address table 3833,
It has been removed from the cache management table queue. Day
The disk address table 3833 stores the disk address table.
Cable 3833 is locked by any process.
Lock information area 3 for storing lock information indicating whether or not
8331 and the cache management table 3831
It has a pointer 38332. The above connection is free
Using the area of the queue forward pointer 38314
Disk address table from the
Pointer to disk 3833 and disk address table
To the cache management table 3831 on the
This is realized by the interface 38332. Use state information
The cache management table 3831 in the prohibited state is
Use of the corresponding block of the cache memory 37 is prohibited.
And is not connected anywhere. Figure 3 shows the cache
FIG. 14 is a diagram showing details of the menu configuration state information 382. Cash
The cache configuration status information 382 includes a cache memory for each unit memory.
Unit memory error count for storing the number of memory access errors
Counter 3821, indicating a normal / blocked state for each unit memory
Unit memory block status information 3822,
Cache management table upper / lower limit address 3823, unit
Stipulates the number of access errors to execute memory block
The unit memory closing threshold 3824 is held. FIG.
FIG. 7 is a diagram showing details of the logical control information 381. Blocking process control
The information 381 is used when closing the cache memory 37.
Is the information to be used, and the block processing control information 381
Cache indicating whether or not it has been locked by processing
Lock processing lock information 3811, cache close processing
Cache close processing flag 3812 indicating the row status, closed
Cache management table 3 for managing block target unit memory
Stores the address of the table that is the upper limit in 831
Block unit memory cache management table upper limit address
3813 and a blockage unit method for storing the lower limit address.
With memory cache management table lower limit address 3814
I do. Here, the unused cache management table is “Both
Cache when managed by a “pointer” pointer
An outline of the closing process of the memory 37 will be described. processing
When a request for read / write processing is received from the device 1,
Channel adapter 31 that executes read / write processing
Or, the drive adapter 32 is
Execute the access process. Cache access processing
Access at a specific part of the cache memory 37
If an error occurs frequently, the unit memory (
(Referred to as “blocked unit memory”).
Separate channel adapter 31 or drive adapter 32
Of the block controller 36 of the channel adapter 31 of FIG.
Activate the closing process 361, and make the cache access
The processing ends. Activated channel adapter
In the cache closing process 361 in FIG.
Cache of all blocks belonging to block target unit memory
Refers to the queue management table 3831 in order of address, and is in use.
State or unused state cache management table 383
Change 1 to the use prohibited state. Next, the closed unit memo
The status information 3822 is changed to the closed state. Below
Describes the details of the closing process of the cache memory 37.
I will tell. First, the premise of the closing process of the cache memory 37
Cache access processing 352 will be described.
You. FIG. 5 is a processing flow of the cache access processing 352.
FIG. First, a read / write from the processing device 1 is performed.
Channel that is performing read / write processing according to the
Adapter 31 or drive adapter 32 continues
Execute cache memory access (step 352)
01). Thereafter, the access result is referred to (step 35).
202), and confirm whether or not an access error has occurred (step 202).
35203). If no access error has occurred
In this case, the cache access process ends without doing anything. A
If an access error has occurred,
To execute exclusively, lock the cache lock process
It is acquired (step 35204). After lock acquisition,
Unit memory error error of the unit memory including the accessed part
Counter 3821 is incremented (step 352).
05). Next, the value of the unit memory error counter 3821
Is compared with the unit memory block threshold 3824, and
The determination of the flag 3812 during the cache closing process is performed (step
35206). When the value of the unit memory error counter is
Is less than or equal to the memory blockage threshold or cache blockage
If the processing in progress flag is ON, the cache closing process
(Step 35207), and the cache access is released.
The access process ends. When the value of the unit memory error counter is
Larger than the unit memory blockage threshold and cache blockage
If the processing flag is OFF, first close the cache.
The closing flag is set to ON (step 35208).
Next, on the cache management table of the block target unit memory
Referring to the limit / lower limit address 3823 (step 3520)
9), these addresses are stored in the block
Memory cache management table upper limit address 3813
And the lower limit address 3814 (step 35).
210). Finally, start the cache closing process (the
Step 35211). Start of the cache closing process
Up to this point
Different from the channel adapter 31 or the drive adapter 32
It is applied to the channel adapter 31. Launch
Original channel adapter 31 or drive adapter 3
2 releases the cache lock processing lock immediately afterwards
Then, the cache access processing ends. Fragmentation
The channel adapter 31 that has been activated is
Independent of the drive adapter 31 or drive adapter 32
The cache closing process 361 is performed asynchronously. Figure 6
Cache closing process 36 related to step 35211 of 5
FIG. Cache closing process 361
The cache closing process F1 (step 3611) and
And cache closing process B1 (step 3612).
You. The cache closing process F1 is performed in the closing target unit memory.
Cache management table 3 that manages each block to which it belongs
831 is referred to in the order of the address of the control memory and used.
In-use / unused cache management table 3831
This is a process of setting the use prohibited state. This process is a read /
This is performed independently of the cache access processing associated with the write processing.
Is Therefore, during the execution of this process, the cache configuration
Access to the state information 382 is executed exclusively.
No other cache access unrelated to the process
Processing may be performed in parallel. This means that the process is blocked
Using the processing control information 381, the cache configuration state information 3
82, without being used. Cache closed
The closing process B1 is performed for all the caches related to the closing target unit memory.
The cache management table 3831 has been disabled.
And the unit memory closed state information on the control memory 38
This is a process of recording a blockage at 3822. This process is key
Access to the cache configuration status information 382 exclusively
Now. FIG. 7 shows a processing flow of the cache closing processing F1.
FIG. First, the cache memory closing process 361 is executed.
Set in step 35210 before starting
Also, the upper limit address of the block unit memory cache management table
313 and the lower limit address 3814 (see
Step 361101). Then, the currently processed ad
Blocking unit memory cache at the address being processed indicating address
Set the management table lower limit address 3814 (step
361102). The address during processing is on the control memory 38
Is stored in the area secured. Next, the address being processed
And block unit memory cache management table upper limit address
3813 (step 361103). processing
The middle address is on the blockage unit memory cache management table
If the address is larger than the limit address, the cache closing process F1 is performed.
finish. The address being processed is the block unit memory cache
If the address is less than the management table upper limit address,
Status information of the cache management table 3831 indicated by the host
38312 (step 361104). Cap
If the cache management table 3831 is in use
First, in order to execute the subsequent processing exclusively,
Locking of the disk address table 3833, and
Acquire the lock of the cache management table 3831
(Step 361105). Next, the cache management data
Bull 3831 from disk address table 3833
It is removed and the use is prohibited (step 361106).
Here, the management of the cache management table 3831 is performed.
Data in the block is not reflected in the storage device 2.
If the data is
Normal memory, that is, unit memory
Write it on the moly. And the cache management table
Bull 3831 and disk address table 38
Release the lock of 33 (step 361107). Ki
If the cache management table 3831 is unused
First, in order to execute the subsequent processing exclusively,
Acquire unused cache management table queue lock
(Step 361108). Next, the cache management data
Is the table 3831 an unused cache management table queue?
To be in the use prohibited state (step 36110)
9). And the unused cache management table queue
The lock is released (step 361110). Finally,
The management address is stored in the next cache management table 3831.
Address (step 361111), and
Dress and block unit memory cache management table upper limit
The process returns to the comparison with the dress (step 361103). processing
Processing ends when the middle address exceeds the upper limit address
You. FIG. 8 shows the cache closing process B1 (step 361).
It is a figure which shows the process flow of 2). First,
In order to execute processing exclusively,
A lock is acquired (step 36121). Next, the cache
Unit memory corresponding to the unit memory that is executing the process block processing
The blockage is recorded in the blockage state information 3822 (step 36).
122). Then, the cache blocking processing flag 381 is displayed.
2 is turned off (step 36123). Finally,
The cache closing lock is released (step 3612)
4). According to the present embodiment, cache management in an unused state
Table 3831 is managed by a bidirectional pointer
Effective when the cache memory is closed
It is possible to provide a storage control device that can be executed in an efficient manner.
In particular, a plurality of channel adapters 31 are provided,
Channel adapter 31 and cache closed
To separate from the channel adapter 31 that performs blockage processing.
The cache closing process related to failure recovery and its original function
Simultaneously and concurrently perform read / write processing related to provision
Can be In this embodiment, the closing control unit
36 is provided on the channel adapter 31, the present invention
However, the present invention is not limited to this.
Or on the channel adapter 32
On the drive 31 and on the drive adapter 32
You may. <Embodiment 2> Next, in Embodiment 1, a key in an unused state is used.
The cache management table 3831 uses a unidirectional pointer
Describe an embodiment managed by a queue
You. Hereafter, the parts that have not been changed from the first embodiment are actually
The same reference numerals as in the first embodiment denote the same parts, and a description thereof will be omitted. Figure 9
FIG. 3 is a diagram illustrating a control configuration according to the embodiment. This control configuration
This is almost the same as the control configuration of the first embodiment shown in FIG. However,
The cache of the control memory 38 and the read / write control unit 35
Queue allocation process 353 and the cache
The contents of the shuffling process 362 are different. Other parts
This is the same as FIG. FIG. 10 shows cache management information.
FIG. 383 is a diagram showing the details of 383. In this embodiment,
The cache management table used can be
Queue pointer 3834
No. 4 is set only one for each table. Ma
The table corresponding to the end of the queue contains the end of the queue.
A queue end value indicating that it is the end is set. So
The other parts are the same as those in FIG. Figure 11 is the real
FIG. 14 is a diagram illustrating blocking processing control information 381 according to the embodiment.
The difference from the blocking processing control information 381 in the first embodiment is as follows.
Holds the cache management table reference threshold 3815
It is a point. Other parts are the same as in FIG.
You. Here, the unused cache management table is
Cache when managed by a "pointer" pointer
An outline of the closing process of the memory 37 will be described. Processing equipment
When a request for read / write processing is issued from the
Channel adapter 31 for executing read / write processing or
The drive adapter 32 is a cache
Execute the access process. For cache access processing
This is the same as in the first embodiment shown in FIG.
You. In the cache closing process, first,
Cache management tables for all blocks belonging to the
3834 by address, and the cache in use
Only the menu management table is disabled for use. That
Later, refer to the unused cache management table queue from the top.
The cache management table 38 in an unused state
34 is set to the use prohibited state. And the closed unit memo
The state information 3822 is changed to the closed state. In addition,
Cache allocation processing 353 during execution of cache closing processing
, Cache management related to block target unit memory
Assignment for read / write processing of table 3834
Prohibit. The following is a description of the cache memory in this embodiment.
The details of the closing process of the memory 37 will be described. Cash
The access process is the same as in the first embodiment.
Therefore, the cache closing process 362 will be described. FIG.
Is a diagram showing an overview processing flow of the cache closing processing 362
It is. The cache closing process 362 includes a cache closing
Process F2 (step 3621) and cache closing process
The process B2 (step 3622). FIG.
The process flow of the cache closing process F2 of the cache closing process 362
FIG. In the cache closing process F2
The difference from the first embodiment is that the key in step 36214
Uses the result of status judgment in cache management table 3834
If it is not in the middle state, do nothing and the next cache management table
This is the point that the process shifts to processing for the file 3834. Cash tube
If the management table 3834 is in an unused state, this key
The cache management table 3834 indicates unused cache management.
Connected to the table queue. Unused cache
To set the cache management table 3834 to the use prohibited state
Removes this from the unused cache management table queue.
Need to be However, this queue is
It is composed of
Cache management table because search can only be performed in the direction
To remove the file 3834 from the queue, be sure to
38322 must be searched in order. The present invention
Of the cache memory in the target storage controller
In general, the amount of data to be held is large, and
The flash memory is composed of thousands to tens of thousands of blocks. the above
The cache management table 3834 constituting the queue of
Since the number is about the same as the above number,
From the specified cache management table 3834
This process of disabling the use of the queue
The occupation time of the queue becomes extremely long as compared with the processing. There
In the present embodiment, first, an unused state with a queue operation
In use state management table without management table
Separate so that they can be processed separately. Next,
About the management table of the use state, the management of the use state
Batch and intermittent after processing the table
Perform the closing process. Specifically, the unused capacity per time
Cache management table queue lock acquisition time
Cache management table reference threshold 3815
Limit the time to refer to the cache management table 3834,
Execute the process in multiple parts. Figure 14 shows the cache closed
It is a figure showing the processing flow of blockage processing B2. First,
Representing the address on the control memory 38 where the
Substituting the initial value for the processing address (step 36220)
1). As an initial value, the cache management table 384
3, an address value outside the storage area, for example, cache management
When the storage area of table 3843 starts from address 1001
Is decided by choosing address 1000 etc. Address in process
Is stored in a predetermined area on the control memory 38. Next
Is a key that is a constant that indicates the address being processed and the end of the queue.
It is compared with the queue end value (step 362202). place
If the current address does not match the queue end value,
Acquisition of cache management table queue lock for
Step 362203). After that, address initialization during processing
The processing is executed (step 362204). FIG.
It is a figure which shows the processing flow of a process address initialization processing.
First, the contents of the address being processed are determined (step 36).
22041). The address being processed is not the initial value, and
Cache management table in which the address being processed is unused
If it is 3834, do nothing. Address in process
Is the initial value, or the address being processed is unused.
If it is not the cache management table 3834 of
Head of unused cache management table queue for address
Set cache management table address 38322
(Step 362022). Address initialization during processing
After executing the management, the number of referenced cache management tables becomes zero.
It is cleared (step 362205). Next, during processing
Address and the queue end value, and
Cache management table number and cache management table reference
The threshold value is compared with the threshold value 3815 (step 362206).
The address being processed matches the queue end value, or
Indicates that the number of referenced cache management tables is greater than the reference threshold
If it is large, the unused cache management table queue lock
Is released (step 362207), and the address being processed
And return to the comparison of the queue end value (step 362202)
You. If the address being processed does not match the queue end value,
The number of referenced cache management tables is less than or equal to the reference threshold
, A use prohibition process is executed (step 36).
2208). FIG. 16 shows a processing flow of the use prohibition processing.
FIG. First, the processing address and the block unit memory key
Cache management table upper limit address 3813 and lower limit
The address is compared with the address 3814 (step 362208).
1) If the address being processed is a closed unit memory cache
Is not less than the lower limit address of the
Is it below the upper limit address of the memory cache management table
Judge whether or not. Otherwise, do nothing and use
The prohibition processing ends. If so, the address being processed
The cache management table 3834 pointed to by the
Remove from the cache management table queue and disable use
(Step 3620222). Execute use prohibition processing
After that, the number of referenced cache management tables is incremented.
(Step 362209). Finally, the processing ad
Address of the next cache management table on the queue
(Step 362210), the address being processed and the queue
-Comparison with terminal value, and reference cache management data
To the comparison between the number of bulls and the reference threshold (step 362206).
Return. Processing address and unused cache management table
If the end value of the queue matches, the cache
Acquires the logical lock (step 362211) and performs the closing process
Is blocked in the block status information 3822 of the unit memory that executed
Recording (step 362212), and
Turn off the processing flag 3812 (step 3622)
13). Then, release the cache lock processing lock.
Step 362214) and ends the cache closing process B2.
Complete. Next, the cache allocation processing 353
explain. In the cache allocation process, the cache close
During execution of the closing process, the cache tube related to the block target unit memory
The assignment of the management table 3834 is prohibited. FIG.
FIG. 14 is a diagram showing a processing flow of cache allocation processing 353.
You. First, a cache lock processing lock is acquired (step
35301). And during the cache closing process
Referring to the log 3812 (step 35302), the cache
The content of the flag 3812 during the process closing process is determined (step
35303). Cache blocking processing flag 3812
Is OFF, first, the disk address table 38
33 locks, unused cache management table queue
A lock is obtained (step 35304). Then, unused
Only the required number from the top of the cache management table queue
Allocate cache management table 3834 (step
35305). And the unused cache management table
Queue lock, disk address table 3833
The lock is released (step 35306). cache
When the closing process flag 3812 is ON, first, the control menu
Blocked unit memory cache management table on the memory 38
The upper limit address 3813 and the lower limit address 3814
Reference is made (step 35307). Next, add the disk
Lock of unused table 3833, unused cache management
Acquire a table queue lock (step 3530)
8). And whether it is an unused cache management table queue
When assigning the cache management table 3834 from the
The address of the allocation target cache management table is closed only
Lower than the lower limit address of the memory cache management table
Squid or closed unit memory cache management table
Cache management table for which the upper limit address is assigned
Cache management table 38 smaller than the address of
34 (step 35309). After that,
Used cache management table queue lock, disk pool
The lock on the dress table 3833 is released. (Step
35351) Finally, release the cache lock processing lock.
Release (step 35311) and cache allocation processing
To end. According to this embodiment, the unused cache
The table management table 3834 is managed by a unidirectional pointer.
The cache memory blocking process
Storage control device that can effectively execute
Can be provided. Specifically, an unused cache management
In the cache closing process related to the
Use cache management table queue lock at acquisition time
By setting a limit, cache close processing can take a long time
The queue is no longer occupied, and the cache is closed
Processing and read / write processing in parallel.
It becomes possible. As a result, systems centered on storage devices
This has the effect of suppressing performance degradation for the entire system.
In this embodiment, refer to the cache management table.
A threshold value 3815 is provided, and an unused cache management table key is set.
Cache acquisition time set in advance
The number of tables 3834 was specified.
The light is not limited to this,
A timer is provided for the lock acquisition time and the
May be set and managed. <Embodiment 3> Next, in Embodiment 1, the cache memo
An embodiment in which the rib 37 is duplicated will be described. This embodiment
Cache memory is composed of multiple unit memories.
It consists of two cache memories. It
Each cache memory is called a plane, two planes are called plane A,
Called side B. Cache memory per unit memory or
Can be closed for each surface. FIG. 18 shows the control of this embodiment.
FIG. 3 is a diagram illustrating a configuration. This control configuration is similar to that of the embodiment shown in FIG.
For the control configuration of Example 1, the cache memory is
Flash memory 372 and B-side cache memory 373
That the control memory 38 has a double key.
A as cache management information of each cache memory
Side cache management information 384 and B side cache management
The information 385 is provided, and both sides are normal in the closing control unit 36.
-Time cache closing process 363 and single-sided closing cache
The point that the program closing process 364 is provided, and the read / write
Cache allocation processing 354 of the
The contents of the cache access processing 355 have been changed
The points are different. Other parts are the same as in FIG.
You. The closing control unit 36 is configured to close the cache memory.
As the stages, the double-sided normal state cache closing process 363 and
And a one-side closed cache closing process 364. Real truth
In the embodiment, the cache closing process 364 when the one side is closed is performed.
The contents are the same as the cache closing process 361 in Example 1.
You. FIG. 19 shows the details of the A-side cache management information 384.
FIG. The cache management information for the A side and the B side is shown in FIG.
Same as the cache management information 383 of the first embodiment shown in FIG.
Structure. Cache of read / write control unit 35
Duplicated cache in allocation process 355
The memory allocation processing is performed as follows. Storage device 2
The data whose contents are reflected in the
Store in either one. The contents are reflected in the storage device
Missing data is stored on both sides. FIG. 20 illustrates this embodiment.
FIG. 8 is a diagram showing details of blockage processing control information 381 in FIG.
In addition to the contents of the block processing control information 381 in the first embodiment,
The status of the cache memory (hereinafter referred to as "cache
State)), the cache state information 3
816 are provided. Cache status is at least double-sided
Normal state, and pieces for each of A side and B side
Including 5 states of surface closed state and temporary single side closed state
No. Both sides normal state means that both A and B sides can be used
It is a state. One-sided closed state means all units on one side
If the memory is closed and the other side is normal,
In other words, there is a unit memory that is not blocked.
It is such a state. A temporary one-sided occlusion condition is
Lock processing to eliminate the need for exclusive processing such as
One side closed temporarily and fakely until the process is completed
It is in the closed state, unlike the one-sided closed state
If all of the unit memories included in the
That is not to say. Here, the duplicated cache
The outline of the memory blockage processing will be described. Processing unit 1
When a request for read / write processing is issued from the
Channel adapter 31 or driver
The Eve adapter 32 has a cache access
Perform access processing. In cache access processing
Access to a specific part of the cache memory 372 or 373
If access errors occur frequently, the block target unit that includes the site
To close the memory, start the cache closing process
Execute 3548. Cache closing process activation process 35
At 48, the cache status is referred to, and if both sides are normal,
If the surface to be closed is temporarily closed on one side,
Cache processing when both sides are normal after disabling write processing
363 is started. If one side is closed,
The cache closing process 364 is started. Also cache
In the cache allocation process during the closing process
Is the cache management table related to the
Allocation for read / write processing of cable 3841
Ban. Below, the duplicated cache memory
Will be described in detail. First, the cache
Cache access processing that is a prerequisite for memory block processing
354 will be described. Figure 21 shows cache access
It is a figure showing the processing flow of processing 354. First, the processing equipment
Read / write according to read / write request from device 1
Channel adapter 31 or drive that is processing
Adapter 32 continues to perform cache memory access.
(Step 3541). Then, access results
Refer to (step 3542) and check for the occurrence of an access error.
Confirm (step 3543). Access error occurred
If not, do nothing and perform cache access processing.
finish. If an access error has occurred,
Cache blockage to execute the subsequent processing exclusively
A processing lock is acquired (step 3544). Lock take
After the acquisition, the unit memo of the unit memory including the part that has just been accessed
The re-error counter 3821 is incremented (step
3545). Next, the unit memory error counter 38
21 is compared with the unit memory blockage threshold 3824
(Step 3546). Unit memory error counter 38
21 is less than the unit memory blockage threshold 3824
In this case, the cache lock processing lock is released (step 35).
47), terminate the cache access process. Unit memo
The value of the re-error counter 3821 is the unit memory blockage threshold 3
If the value is larger than 824, the cache closing process is started.
To execute the cache closing process start process which is the pre-process for
(Step 3548). Cache shutdown processing start processing
After executing the management, the cache lock processing lock is released and the cache
The cache memory access processing ends. FIG. 22 shows FIG.
Of the cache closing process starting process in step 3548
It is a figure which shows a management flow. First, the cache state information 3
816 (step 354801) and cache
It is determined whether the state is a normal state on both sides (step 35).
4802). If both sides are normal, cache status information
Is changed to the X-side temporary one-side closed state (step 354).
803). Here, the X surface indicates a surface to be closed. Next
In addition, the unit memory cache management
Cable upper / lower limit address 3823 (step
354804), these values are stored in the closing process control information 38.
Blocked unit memory cache management table upper limit address within 1
Address 3813 and lower limit address 3814
(Step 354805). Then, when both sides are normal
The shuffling process 363 is started (step 35480).
6). Activation of the cache closing process 363 when both sides are normal is as follows.
The cache access processing and cache
Channel adapter 31 that has executed the shutdown processing activation processing
Or a channel adapter different from the drive adapter 32
It is applied to 31. The original channel
The adapter 31 or the drive adapter 32 is
Finishes the cache closing process activation process
Return to access processing. And cache lock processing lock
Is released, and the cache access processing ends. Start up
The activated channel adapter 31 is the original
What is channel adapter 31 or drive adapter 32
Independently and asynchronously, the cache closing process 363 when both sides are normal
Do. On the other hand, if both sides are not normal, the cache is closed
Referring to the processing flag 3812 (step 35480)
7) The status of the cache and the cache closing process
In step 354808, a judgment is made. Cap
Is in the X'-plane one-side closed state and the cache
If the cache shutdown processing flag is OFF, the cache shutdown processing
The processing flag is set to ON (step 354809).
Here, the X ′ plane indicates the opposite side of the surface to be closed. Next
In addition, the unit memory cache management
Cable upper / lower limit address 3823 (step
354810), these values are stored in the closing process control information 38.
Blocked unit memory cache management table upper limit address within 1
Address 3813 and lower limit address 3814
(Step 354811). Finally, when the one-sided
The shuffling process 364 is started (step 35481)
2). The activation of the one-sided normal time cache closing process 364 is as follows.
The cache access processing and cache
Channel adapter 31 that has executed the shutdown processing activation processing
Or a channel adapter different from the drive adapter 32
It is applied to 31. The original channel
The adapter 31 or the drive adapter 32 is
Finishes the cache closing process activation process
Return to access processing. And cache lock processing lock
Is released, and the cache access processing ends. Start up
The activated channel adapter 31 is the original
What is channel adapter 31 or drive adapter 32
One-sided normal-time cache closing process 364 is performed independently and asynchronously.
Do. On the other hand, if the cache state is X 'plane
Or if the cache closing flag is ON.
If the cache closing process activation process ends,
Return to access processing. Here, the X 'plane is the target of the block processing.
Refers to the opposite side of the surface. Next, the cache closing process when both sides are normal
An outline of the process 363 will be described. This processing is
Writes data whose contents are not reflected in the storage device to the storage device
After initializing cache management information,
The cache management table 3841 related to the unit memory is used.
This is a process of setting the use prohibition state. Prior to performing this processing
In other words, the cache status of the side that executes the
Although the surface is in the closed state, it is necessary to
-Based read / write processing using normal opposite surface
To run. Therefore, the two-sided normal cache
The blockage processing 363 is a read / write operation from the processing apparatus 1.
It can be executed without being aware of the request. Fig. 23 shows both sides normal
Is a diagram showing a processing flow of a time cache closing process 363.
You. First, all the disk addresses on sides A and B
Referring to the table 3843, the data is reflected in the storage device 2.
Cache management table 3841 that has no data
While writing the data to the storage device 2,
All the cache management tables 3841 are stored in the A side and the B side.
Open to each unused cache management table queue
Release (step 3548061). Next, unused
Cache management released to the cache management table queue
The table 3841 is re-chained in the order of addresses (s
Step 3548062). Re-chaining means that
Cache management table queue
Cache management table 3841 and newly released to the queue.
Cache management table 3841
Re-arranging the queue and re-arranging the queue.
You. Furthermore, on the block unit memory cache management table
Use the lower limit address 3813 and the lower limit address 3814
Then, the caches related to all unit memories to be blocked
Cache management table 3841 to the unused cache management table.
It is removed from the bull queue (step 3548063). last
The unit memory block status information 38 of the block target block unit memory
22 is recorded and the cache status information 3816 is changed.
(Step 3548064). Cache status information
The report is X-plane if all unit memories in the plane are closed
Change to single-sided closed state, otherwise change to double-sided normal state
I do. Here, the X plane refers to the plane on which the closing process has been performed.
Next, the cache allocation processing 354 in the present embodiment.
Will be described. Ratio of duplicated cache memory
During the allocation, the cache memory status is not normal.
Allocation of the cache management table 3841
Perform prohibition processing. FIG. 24 shows cache allocation processing.
FIG. 354 is a diagram showing a processing flow of 354. First,
In order to execute processing exclusively,
A lock is acquired (step 35501). Next,
With reference to the cache state information 3816 (step 3550)
2) Trying to secure cache memory
It is determined whether the surface is normal (step 35503).
If not, try to allocate cache memory
Is changed to the opposite surface (step 3550)
4). If normal, cache memory with original side
Proceed to the next step as a surface to be secured. Then the disk
Lock and unused cache of address table 3843
Acquire the management table queue lock (Step 3
5505). And the unused cache management table key
Cache management table 3 as many as necessary from the top of the queue
841 is assigned (step 35506). Finally,
Unused cache management table queue lock, disk
Release the lock of the address table 3843 (step
35507), release the cache lock processing lock
(Step 35508), end the cache allocation process
Complete. According to the present embodiment, the cache in the first embodiment is used.
When the memory 37 is duplicated, take advantage of the feature of duplication.
Storage controller capable of effective cache blocking processing
Can be provided. Specifically, when both sides are normal,
In case of harm, the entire surface including the obstacle is temporarily closed.
State to eliminate lock acquisition for execution of shutdown processing
Therefore, the blocking process is affected by other processes.
Conscious of read / write requests from the processing device 1
The cache closing process can be executed without performing. this child
Is to suppress the performance degradation of the entire system due to exclusive processing
It has the effect of. Note that, in this embodiment, the
The cache closing process 364 is the cache in the first embodiment.
Although the contents are the same as the closing processing 361, the present invention is not limited to this.
Is not specified, and the cache is closed in the second embodiment.
The content may be the same as the closing process 362.

According to the present invention, the cache memory can be closed for each unit memory as a constituent element, so that the cache memory can be effectively used for a local failure. In addition, since the control information of the storage control device is excluded during the closing process, a read / write request from the central processing unit can be accepted.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a system configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating detailed contents of cache management information according to the first embodiment.

FIG. 3 is a diagram illustrating detailed contents of cache configuration state information according to the first embodiment.

FIG. 4 is a diagram illustrating detailed contents of block processing control information according to the first embodiment.

FIG. 5 is a flowchart illustrating a cache access process according to the first embodiment.

FIG. 6 is a flowchart illustrating an outline of a cache closing process according to the first embodiment.

FIG. 7 is a flowchart illustrating a first half of a cache closing process according to the first embodiment;

FIG. 8 is a flowchart illustrating the latter half of the cache closing process according to the first embodiment.

FIG. 9 is a diagram illustrating a system configuration according to a second embodiment of the present invention.

FIG. 10 is a diagram illustrating details of cache management information according to the second embodiment.

FIG. 11 is a diagram illustrating detailed contents of block processing control information according to the second embodiment.

FIG. 12 is a flowchart illustrating an outline of a cache closing process according to the second embodiment.

FIG. 13 is a flowchart illustrating the first half of the cache closing process according to the second embodiment.

FIG. 14 is a flowchart illustrating the latter half of the cache closing process according to the second embodiment.

FIG. 15 is a flowchart illustrating a part of the latter half of the cache closing process according to the second embodiment.

FIG. 16 is a flowchart illustrating a part of the latter half of the cache closing process according to the second embodiment.

FIG. 17 is a flowchart illustrating cache allocation processing according to the second embodiment.

FIG. 18 is a diagram illustrating a system configuration according to a third embodiment of the present invention.

FIG. 19 is a diagram illustrating detailed contents of cache management information according to the third embodiment.

FIG. 20 is a diagram illustrating detailed contents of block processing control information according to the third embodiment.

FIG. 21 is a flowchart illustrating a cache access process according to the third embodiment.

FIG. 22 is a flowchart illustrating a cache closing process activation process according to the third embodiment.

FIG. 23 is a flowchart illustrating a normal both-side cache blocking process according to the third embodiment.

FIG. 24 is a flowchart illustrating cache allocation processing according to the third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processing device 2 Storage device 3 Storage control device 35 Read / write control unit 351 Cache allocation process 352 Cache access process 36 Blocking processing unit 361 Cache blocking process 37 Cache memory 371 Unit memory 38 Control memory 381 Blocking process control information 382 Cache configuration status Information 383 Cache management information 3831 Cache management table

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Ichinomiya 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer Systems Co., Ltd. (72) Inventor Akira Yamamoto 1099 Ozenji, Aso-ku, Aso-ku, Kawasaki City, Kanagawa Stock (56) References JP-A-5-12122 (JP, A) JP-A-3-164844 (JP, A) JP-A-4-44141 (JP, A) JP-A-6-164 180671 (JP, A) JP-A-8-221326 (JP, A) JP-A-7-20994 (JP, A) JP-A-6-35802 (JP, A) JP-A-64-7143 (JP, A) JP-A-62-182853 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/08-12/12 G06F 3/06-3/08

Claims (5)

(57) [Claims] 1. A storage device connected between a processing device and a storage device.
A storage control device that controls data transfer between the processing device and the storage device; a first and a second channel controller connected to the processing device; a cache memory having a plurality of unit memories; A control memory having a first storage area for storing control information for managing the address of the unit memory in the memory and a second storage area for storing information of the address of the unit memory in the cache memory; The first channel controller has means for copying address information of a first unit memory in the cache memory satisfying a predetermined condition from the first storage area to the second storage area. The second channel controller uses information on an address of the first unit memory stored in the second storage area. And a closing processing means for performing closing processing of the first unit memory. 2. The apparatus according to claim 1, wherein the predetermined condition is a condition that the number of times that the processing device has failed to access the first unit memory exceeds a predetermined threshold. Storage controller. 3. The control memory includes: a third storage area for storing information regarding blocks not used by the processing device among blocks included in the plurality of unit memories; and a control memory included in the plurality of unit memories . And a fourth storage area for storing information on blocks used by the processing device among the blocks to be processed, wherein the closing processing means stores information on the blocks included in the first unit memory in the fourth unit. determination means for determining whether stored in a third storage area and said fourth storage area, included in the first unit memory in said determination means
When it is determined that the information regarding the block is stored in the third storage area or the fourth storage area, the information regarding the block included in the first unit memory is stored in the third storage area or the fourth storage area. 3. The storage control device according to claim 2, further comprising a deletion unit that deletes from the four storage areas. 4. The system according to claim 1, wherein the block processing unit copies the data stored in the first unit memory to a second unit memory of the plurality of unit memories before executing the deleting unit. The storage control device according to claim 3, comprising: 5. A device connected between the processing device and the storage device,
What is claimed is: 1. A closing control method for closing a cache memory of a storage control device in a storage control device that controls data transfer between the processing device and the storage device, comprising: a first channel controller included in the storage control device. Determines that the unit memory of the cache memory is unusable, stores the address information of the unit memory in the control memory, and stores the address information of the unit memory in the control memory by the second channel controller of the storage controller. A method of blocking processing of a cache memory, wherein the unit memory to be blocked is specified based on the specified address information, and the specified unit memory is made unusable by the processing device.