JP3234723B2 - Design method of semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit device required to operate at high speed.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit device realized by arranging a plurality of logic cells on a semiconductor chip and connecting the logic cells, circuit operation is guaranteed. In order to achieve this, a signal propagating along all signal paths of a circuit, that is, a path from a signal input terminal (hereinafter, also referred to as a source) to a signal output terminal (hereinafter, also referred to as a sink) of a path may be transmitted within a required time. is necessary. A conventional design method of such a semiconductor integrated circuit device will be described with reference to FIG. In FIG. 10, START indicates the start of the process, and END indicates the end of the process. First, for each connection information (hereinafter, referred to as a net) between terminals of a logic cell before placement, a virtual wiring length (wiring capacitance) is added, a delay of the net is calculated, and a path analysis is performed (step S1). F51).

At this time, the time required for a signal to propagate on a wiring (called a wiring RC delay, which is individually calculated between individual terminals of a net) is not taken into consideration. Next, a net constraint is generated for the path extracted in step F51 (see step F52). Then step F
The general arrangement is performed in consideration of the constraint generated in step 52 (see step F53). Then, the general arrangement result created in step F53 is improved by successively moving and exchanging cells (see step F54). This step F5
In 4, the timing and the like are improved in consideration of the same restrictions as in step F53. Then, a wiring process is performed in step F55, and a delay calculation is performed on the wiring result in consideration of the wiring RC delay to verify whether there is a violation path (see step F56). If there is no path that does not satisfy the required time in step F56, the process ends. If a violating path is found in step F56, the flow returns to step F51, and the path analysis is performed again.

In the above-described conventional design procedure in consideration of timing, net delay prediction is performed based on a statistically or empirically predicted value of a wiring length before placement. Therefore, the wiring RC delay is taken into consideration. No
The predicted value of the delay contained a large error. If the delay of each net includes a large error, the reliability of the path extracted by the path analysis is doubtful. That is, when the path analysis result in step F51 is compared with the path analysis in step F56, problems such as incorrect extraction of a path that is not violated in step F51 and failure to extract a violating path to be extracted occur. This problem also has a significant effect when generating timing constraints in step F52, and causes problems such as generation of unnecessary constraints and lack of necessary constraints. That is, the optimization in the placement processing steps F53 and F54 is insufficient, so that the placement and wiring may be repeated many times in the conventional design method. For large-scale data, the calculation time required for wiring processing is enormous, and it takes tens of hours to several days for the CPU to complete all connections, so that a layout that satisfies the given required time is completed. Obviously, this requires a great deal of time.

In particular, in a chip layout under a submicron design rule, the wiring RC delay is comparable to or even exceeds the internal delay of a cell. There is a problem that the reliability of the analysis is extremely low, which leads to a decrease in the performance of the entire layout.

Next, a conventional way of giving a timing constraint will be described. As a conventional timing constraint generation method, there is a method of imposing a time constraint on the entire net chain (a complete path) constituting a path as the entire path. This method is described, for example, in Wilm E. Donath et al., "Timi
ng Driven Placement Using Complete Path Delay ", Pro
c. of 27th DAC 1990. Since this is the most restrictive form of solution space when searching for a solution that satisfies the requirements, if a solution exists, the possibility of obtaining that solution Is the highest. However, on the other hand, when designing a large-scale circuit, the number of critical paths (paths with the longest signal propagation times) is enormous. Has a problem that a large amount of storage space is required to hold the constraints. Further, in the layout processing performed in consideration of such constraints, it takes a lot of time to evaluate a constraint violation in the processing, and therefore, it takes a very large amount of time until the result finally satisfies the constraints. Takes time. For this reason, it is impossible to apply it to actual large-scale data.

As another conventional method, there is a method of decomposing a path into net units to create a constraint. (For example,
Yasushi Ogawa et al. "Efficient Placement Algorith
ms Optimizing Delay for High-Spced ECL Masterslice
LSI's ", Proc. Of 23rd DAC1986.).

In this method, a required time for a path is distributed to individual nets constituting a path by an appropriate method (for example, by an even distribution). In this method, the number of constraints is only one for nets that appear in multiple paths.
Since there is only one, there is an advantage that the number of constraints is at most about the number of nets. However, depending on how the delay is allocated to the net, there is a possibility that the constraint may not always exist. Therefore, if any one of the nets cannot satisfy the constraint value, many paths passing through the net violate the constraint. That is, in the timing optimization based on the net constraint, the solution space of the solution satisfying the request is highly likely to be extremely narrowed because the constraint is decomposed. Also,
Since it is a constraint on a net basis, it is not possible to define a delay constraint between terminals constituting the net, so that it cannot be applied to optimization in consideration of the wiring RC delay. That is,
It cannot be applied to the LSI design under the sub-micron rule where the problem of the wiring RC delay appears remarkably.

As an attempt to solve the above-described problem of the net restriction, Japanese Patent Application No. Hei.
There is one. In this method, a path is divided by branch points of all paths, a partial path is formed, and a constraint is generated for the partial path. If this method is used, constraints are generated in units of partial chains of the net from the branch point of the path to the branch point, so in principle the solution space is wider than the net constraint, and the solution is obtained. There is an advantage that it becomes easy. However, in a normal circuit design, the path branches are complicated and many, so that the constraint form is almost the same as the net constraint, and the same problem as the net constraint occurs. Also,
Since the critical path with the longest delay is also a subdivided restriction, the restriction is not always easy to satisfy. That is, the effectiveness was small.

As described above, when the conventional timing optimization technique is used for the design of a large-scale integrated circuit using a submicron design rule, the arrangement is performed in consideration of a memory to be used and timing constraints. Not only is there a difficult problem in the time required, etc., but also it is difficult to obtain a solution that satisfies the constraints.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide a method of designing a semiconductor circuit device capable of reducing processing time and memory usage.

[0012]

According to the method of designing a semiconductor integrated circuit device of the first invention, a desired circuit is arranged by arranging a plurality of logic cells on a semiconductor chip and connecting between the logic cells. In a semiconductor integrated circuit device that realizes
With respect to connection information called a net between cell terminals before arrangement, an average net predicted wire length for each number obtained by subtracting 1 from the number of terminals connected to the net is given to all nets, and propagated through the circuit. A path analysis of the signal path is performed, and for all paths that do not satisfy the requirement of the signal propagation time, a time constraint that satisfies the requirement is changed from a signal input terminal called a source of the path to a signal output terminal called a sink. , Or based on the first step and the set constraints that are allocated and distributed from the source to the sink of each net constituting the path, and the initial placement state is determined in consideration of the time constraints. And performing virtual wiring from the arrangement position information of each cell with respect to the initial arrangement state, and calculating and calculating delay based on the obtained virtual interconnection information. For the extracted critical path, a timing constraint that satisfies the requirements is distributed and given from the path source to the sink or from the source to the sink of each net constituting the path. A third step, and a fourth step of improving a placement state by successively moving / exchanging cells under a set time constraint so that the placement state satisfies all timing constraints. It is characterized by being.

Further, according to the method of designing a semiconductor integrated circuit device according to the second aspect of the present invention, a semiconductor which arranges a plurality of logic cells on a semiconductor chip and connects each logic cell to realize a desired circuit. In the integrated circuit device, a first step of arranging all cells to be mounted on the chip or a part thereof on the chip by appropriate means, and performing virtual wiring based on the arrangement result, are obtained. Perform delay calculation and path analysis using virtual routing information
For the extracted critical path, a constraint that satisfies the requirement of the signal propagation time is given from the source of the path to the sink or distributed from the source to the sink of each net constituting the path. Step 2, a third step of generating an initial arrangement state based on the set constraints in consideration of the restrictions, and arrangement position information of individual cells with respect to the initial arrangement state. From the virtual wiring, using the obtained virtual wiring information,
Performs delay calculation and path analysis, and distributes constraints that satisfy requirements to the extracted critical path from the source to the sink of the path or from the source to the sink of each net constituting the path And a fifth step of improving the arrangement state by successively moving and exchanging cells under the set constraints to achieve an arrangement state satisfying all timing constraints. It is characterized by having.

According to the third aspect of the present invention, there is provided a semiconductor integrated circuit device designing method, wherein a plurality of logic cells are arranged on a semiconductor chip and a desired circuit is realized by connecting the logic cells. In the integrated circuit device, for generating a constraint that satisfies the signal propagation time requirement for the critical path set obtained by the path analysis, a path that is expected to require the most time in signal propagation, Alternatively, for a path corresponding to the path or a path of interest for which delay is to be reduced, restrictions on the source and sink of the path are given in the form of a complete path. , Take a path with the same source and sink, or a path related to the path of interest, in an appropriate order,
A timing constraint for satisfying a request is generated for a partial path of a path excluding a common part on a path with a path taken out to a higher order.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device designing method, comprising arranging a plurality of logic cells on a semiconductor chip and connecting each logic cell to realize a desired circuit. When generating a constraint that satisfies the signal propagation time requirement for a critical path set obtained by path analysis in an integrated circuit device, when allocating the required time to each net, Using the net delay calculated based on the virtual wiring route information or the net delay that can be improved and achieved by the placement improvement process, predicting the net with respect to the delay of the entire path Request time is allocated to each net according to the delay ratio.

Further, according to the method of designing a semiconductor integrated circuit device according to the fifth aspect of the present invention, a plurality of logic cells are arranged on a semiconductor chip and a desired circuit is realized by connecting the logic cells. In the integrated circuit device, when a constraint that satisfies the signal propagation time requirement is generated for the critical path obtained by the path analysis, a set of critical paths extracted by the path analysis is input to each cell in the circuit. The output terminal is a node, the signal propagation path in the cell connected from the input terminal to the output terminal and the net are each an edge, and a start node connecting the source of each path and an end node connecting the sink of each path are generated, and a critical path is generated. Graphically represents the partial circuit formed by, and calculates the delay from the branch point node of each edge to the end node of the path. To to have a calculated value as a weight to each edge, rearrange all edges in descending order of weight attached to the edge, each edge of order and without,
For the path with the longest delay (referred to as the longest path), a time constraint that the delay from the start point to the end point is equal to or less than the required time is generated for the edge set constituting the longest path. For the paths other than the path, the delay from each edge to the end node is equal to or less than the delay of the edge in the higher order so that the order of the edges is maintained before and after the arrangement processing for the edges constituting the path. The constraint is imposed so that

[0017]

According to the design method of the first invention configured as described above, highly accurate delay prediction can be performed using virtual wiring information executed in the placement processing. Since the accuracy of timing constraint values is dramatically increased, extremely reasonable constraint values are added to the minimum necessary paths, and timing can be optimized more efficiently in the placement process with fewer constraints than in the past. become able to. Furthermore, the restriction form in the placement improvement is devised so that the path path with the longest path delay, which is difficult to achieve, takes a wide solution space as a complete path form from the path source to the sink, making it easy to search for a solution. ing. As a result, it is possible to achieve a qualitative improvement in arrangement improvement, a reduction in processing time, and a reduction in memory used.

According to the design method of the second aspect of the present invention, a temporary arrangement state is created before an initial arrangement state is created in consideration of timing, and the temporary arrangement state is created. By performing virtual wiring on the placement result and performing highly accurate delay prediction, the accuracy of path analysis and constraint generation is improved. As a result, the timing quality of the initial arrangement state can be improved, and the processing time of the fourth and fifth steps can be further reduced as compared with the first invention.

Further, the third to fifth components configured as described above are used.
According to the design method of the invention, the delay of the child path after the branch point is smaller than the delay from the branch point of the child path branching to the end point of the path from the parent path constraint in the complete path format. Since restrictions are imposed, it is possible to satisfy timing requirements for all paths, and it is possible to achieve a reduction in processing time and a reduction in memory used.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a method for designing a semiconductor integrated circuit device according to the present invention will be described with reference to FIGS. FIG. 1 is a flowchart showing the design procedure of the first embodiment.

Step F1 is a critical path analysis process before the placement is executed, step F2 is a process of generating a timing constraint on the critical path obtained by the path analysis of step F1, and step F3 is an initial process. This is an initial arrangement process for creating an arrangement state. Step F4 is a critical path analysis process for the initial placement result created in step F3.
Reference numeral 5 denotes a timing constraint generation process for the initial placement result. Step F6 is a placement improvement process for improving the initial placement result. Step F7 is a verification of the path analysis result after the placement improvement. If no violation path with respect to the required time is detected in step F7, the design stage shifts to wiring processing F8. On the other hand, if a violating path is detected, the process returns to step F4, performs path analysis and adds a constraint again (see step F5), and executes a placement improvement process (see step F6).

Next, the processing contents of each step will be described in detail. First, in step F1, a path analysis is performed based on a file (called a netlist) in which connection information of the entire circuit is described, and a violation path is extracted. At this time, the library to be used (design rules, maternal scale)
For each net, a predicted value of the wiring capacity for each fan-out obtained statistically or empirically is given to each net, and a net delay in consideration of the wiring volume load is used.

Next, in step F2, a timing constraint is generated for each net, in which all the extracted paths satisfy the constraint. Here, the difference between the conventional net constraint and the constraint in the unit of net of the present invention will be clarified.

FIG. 2 shows the difference between the conventional net constraint and the net-based constraint of the present invention. The conventional net constraint has dealt with the delay caused by the wiring of the net considering only the wiring capacitance. In this case, the time required for a signal to be transmitted from the input terminal S of the net to each of the fan-out terminals OA and OB is not treated separately.
It has been assumed that a signal is transmitted to A and OB. This is exactly the same as imposing a restriction on the wiring length for each net. However, when the delay is calculated in consideration of the wiring resistance, the delays S → OA and S → OB are not the same. Therefore, if a conventional net constraint is applied to a submicron generation LSI design in which delay due to wiring resistance is important as described above, a large error occurs. Therefore, in the present invention, restrictions are distinguished and handled for each set of terminals even in the same net. In other words, S → OA and S → OB are treated as different even if they are in the same net.
In order to distinguish the conventional net constraint from the net-based constraint according to the present invention, the net-based constraint according to the present invention will be hereinafter referred to as an intra-net terminal-to-terminal constraint.

The generation of the intra-net terminal constraint before the cell placement in step F2 is achieved by reducing the delay that can be achieved in the driving force (gate resistance), the number of fan-outs, and the placement of the cells as the signal input of each net constituting the path. Determined in consideration of the amount and the like. First, a value obtained by reducing the delay of the net calculated at the time of the above-mentioned path analysis by about several tens of percent (for example, 20%) is set as a target net delay, and the target net delay is added to the nets constituting the path to obtain a target path. Delay. The distribution ratio of the required time to the net is given by target net delay / target path delay, and the constraint between terminals in the net is determined as (target net delay / target path delay) · required time. Now, when you take one pass,
The constraint between the terminals in the net satisfying the required time of the path can be generated. Next, an intra-net terminal constraint is generated such that all paths satisfy the constraint. In this case, the intra-net terminal constraints are obtained for all paths, and the minimum intra-net terminal constraint for each inter-terminal route in each net may be adopted as the time constraint of the inter-terminal route in the net.

FIG. 3 shows a process of creating a constraint between terminals in a net. Now, as shown in FIG. 3A, two paths, PATH1 and PA, exceeding the required time 5
It is assumed that TH2 is extracted. Then, PATH1,
The constraint between the terminals in the net created for each of PATH2 is calculated as shown in FIG.
As shown in FIG. 3 (c), a minimum value of 1 is adopted as a restriction between terminals in the net between the common parts AB of the PATH2 and PATH2. For the route AB, the intra-net terminal constraint has been determined so far, and for the other parts, the value 4 obtained by subtracting the determined intra-net terminal terminal constraint between the AB from the required time 5 is B.
Redistribute among C, CD, BE and EF. FIG. 3 (d)
A state is shown in which restrictions between terminals within a net are created for all routes.

Using the timing constraints created as described above, an initial placement process is executed in step F3. As the initial arrangement processing, a min-cut method, a wiring length minimizing method, or the like may be used. Further, when performing the rough placement, the timing constraint may be handled after being converted into a unit of length (such as a half circumference of the net). After the initial placement process, the process proceeds to the next stage regardless of the timing constraint violation.

In step F4, a path analysis is performed again based on the obtained initial arrangement result. At this time, the delay of each net is obtained by executing virtual wiring for the arrangement positions of cells and terminals and performing highly accurate delay calculation according to the virtual wiring path. However, the virtual wiring in step F4 does not need to be the same as the wiring after the completion of the placement processing. Wiring of different nets may overlap (short) or may exceed the number of wirings that can be laid on the chip. Is allowed. Here, it is a temporary wiring process, and is executed at extremely high speed.

FIG. 4 explains a procedure for creating a virtual wiring route. First, adjacent terminals are grouped to form some terminal sets (called clusters). The cells that are the core of clustering (called seeds)
Select some cells far from the center of the net rectangle. As the cells to be grouped with the seed, a cell located near the seed is selected. The determination of whether it is in the vicinity is
Use the distance from the seed. In the present invention, a circle having an area equivalent to 1/4 of the minimum rectangle of a net is used as a criterion for grouping. In FIG. 4A, C1, C2, C3, and C4 are clusters created by the above procedure. Next, virtual wiring is performed for each cluster. Virtual wiring is created by extending a Single Trunk Steiner Tree between terminals in a cluster. W1, W2, W3, and W4 in FIG. 4B are intra-cluster wiring paths for the clusters C1, C2, C3, and C4, respectively. Next, as shown in FIG. 4 (c), a Single Trunk Steiner Tree is extended between the clusters to complete the net wiring prediction path. At this time, by selecting a point closest to the center G of the rectangular shape of the net as a connection point of the cluster on the wiring route in the cluster, a wiring route can be created without generating a redundant wiring route. As can be seen from the above configuration, in the procedure for creating a virtual wiring path used in the present embodiment, first, a connection is made between adjacent terminals to form a partial wiring predicted path, and then,
Since the wiring paths connecting the respective partial wiring paths are created, the number of redundant wiring paths is small, and a result similar to the usual shortest path search and wiring method can be realized. For this reason, if the RC delay of the net is calculated using the wiring prediction route of the present embodiment, a highly accurate predicted value of the delay can be obtained.

FIG. 5 shows a wiring route prediction method (called the MTST method) used in the present embodiment and a conventional wiring length prediction method (Half method).
Perimeter method: HP) and wiring route prediction method (Sing
5 is a graph comparing the prediction accuracy of the path delay when using the Le Trunk Steiner Tree method (STST method). We performed delay prediction and path analysis on the placement results, and compared them with the results after detailed routing. The horizontal axis shows the path system, which is a system path having different sources and sinks. In the experiment, the path with the longest delay was extracted from the paths of each system. The vertical axis indicates the absolute value of the error with respect to the longest path of each system after the detailed wiring, which is assumed to be true. According to this experiment, in the conventional prediction method, the path delay prediction error at the time of cell arrangement was 35% at the maximum, but in the method used in the present embodiment, it was extremely small at 6% at the maximum. It can be seen that the accuracy is high.

Next, step F5 is a process for generating a timing constraint on the extracted path. FIG.
9 illustrates the constraint generation process of this embodiment. FIG. 6A shows a network to be subjected to path analysis, in which a white circle corresponds to a terminal (node), and a straight line connecting the nodes is a wiring or a signal path in one cell. Is shown. FIG. 6B shows a state of a path extracted by performing a path analysis on the network of FIG. 6A. In FIG. 6B, PATH1, PATH
2 shows a state where three violation paths of PATH3 are extracted. For all the nets that constitute the violation path, a constraint between the terminals in the net is calculated such that all the violation paths satisfy the required time. According to the present invention, paths extracted by path analysis are sequentially extracted in descending order of path delay, and a constraint is generated for a partial path excluding a common part on a path with a higher-order extracted path. For example, it is assumed that the path delays have a relationship of PATH1>PATH2> PATH3. At this time, PATH1 is firstly extracted, and since there is no path (upper path) with a delay larger than itself, PATH1 is the unit of the restriction as it is. Then, a timing constraint having a required time as a constraint value is generated for the entire path from the source to the sink of PATH1. 6B is a timing constraint on PATH1.
As for PATH2, PATH1 exists as an upper path, so that a constraint is generated for other parts except for the common part with PATH1. That is, the restriction on PATH2 is restriction 2 in FIG. At this time, the value of the constraint is the sum of the constraints between the terminals in each net excluding the common part with PATH1. Further, for PATH3, since PATH1 and PATH2 exist as upper paths, a constraint is generated for a partial path excluding a common part with these upper paths. That is, if constraint 3 is PA
This is the timing constraint of TH3.

However, the restriction between the terminals in the net at this time is different from the calculation method when no arrangement is made in step F2, and a wiring RC delay is newly added. For example, with respect to the calculated net delay, a value obtained by reducing the predicted value of the wiring capacity and the wiring RC delay by about several tens percent (for example, 20%) is set as a target net delay, and the target net delay constitutes a path. The sum of the nets is defined as a target path delay. The delay of the entire path is recalculated to be the target path delay. The distribution ratio of the required time to the net is given by target net delay / target path delay, and the constraint between terminals in the net is determined as (target net delay / target path delay) · required time. Now, when you take one pass,
The constraint between the terminals in the net that satisfies the required time of the path can be generated. Next, an intra-net terminal constraint is generated such that all paths satisfy the constraint. In this case, the intra-net terminal constraint is obtained for all paths, and the minimum intra-net terminal constraint for each inter-terminal route in each net may be adopted as the time constraint of the inter-terminal route in the net. The constraint generation for the path or the partial path described with reference to FIG. 6 is executed by using the intra-net terminal constraint determined for each net as described above.

FIG. 7 shows the form of a constraint when the path is analyzed again based on the result of the placement improvement after the placement improvement and the constraint is reconstructed. At this time, the existing constraint is not deleted, and a path constraint or a partial path constraint is added to the newly extracted path route. In FIG. 7, PATH4 is shown as a newly extracted path. PATH4
Are already extracted paths PATH1, PATH2, and PAT.
Since it has a common part with H3, a timing constraint on PATH4 is generated for a partial path excluding this common part. That is, the timing constraint generated for PATH4 is constraint 4.

Next, a second embodiment of the method for designing a semiconductor integrated circuit device according to the present invention will be described with reference to FIG. FIG.
9 is a flowchart showing a design procedure of the second embodiment. In FIG. 8, step F21 is a placement process for creating a temporary placement state, and step F22 is a critical path analysis process for this placement result.
Step F23 is processing for generating a timing constraint on the critical path obtained by the path analysis in step F22, step F24 is initial placement processing for creating an initial placement state, and step F25 is critical processing for the initial placement state. In the path analysis processing, step F26 is a timing constraint generation processing for the initial arrangement state, and step F27 is an arrangement improvement processing for improving the initial arrangement state. Step F28 is a verification of the path analysis result after the placement improvement. If no violation path for the required time is detected in step F29, the process proceeds to the wiring process (step F30) in the design stage. On the other hand, if a violating path is detected, step F
25, the path is analyzed again (see step F25),
A constraint is added (see step F26), and a placement improvement process (see step F27) is executed. In the present embodiment, a temporary placement state is created before an initial placement state is created in consideration of timing, and virtual wiring is performed on the temporary placement result, thereby achieving high-precision placement. Path analysis is performed by performing delay prediction (see step F22).
And the accuracy of constraint generation (see step F23).

As a result, the timing quality of the initial arrangement state can be improved.
The number of repetitions of the processing from Step 5 to Step F29 can be reduced. That is, it is possible to further reduce the design period of the entire layout in consideration of the timing. In addition, the details of each process constituting the flow conform to the contents of the design procedure of the first embodiment.

The worst-path delay between registers when a gate array is actually designed and manufactured using each of the design method of the second embodiment, the conventional net weight method, and the conventional net delay constraint method. Are shown in Table 1.

[0037]

[Table 1] From this experimental result, it can be seen that in the present embodiment, the path delay can be significantly reduced in comparison with the conventional wiring capacity constraint method for each net and the net weight method for adding a weight for each net. I understand.

As described above, according to the design method of the first or second embodiment, when the initial arrangement state is generated, or when the initial arrangement state is improved, the final arrangement state is improved. Since the virtual routing process is performed on the placement results when creating a layout result, highly accurate delay prediction using virtual routing information is possible, and the accuracy of path analysis and the validity of constraint values are Since it is dramatically increased, higher quality of the arrangement result can be expected. In addition, it is clear that constraints are added to the minimum necessary paths. As a restriction in improving the layout, the path with the longest signal propagation time is a complete path from the path source to the sink. The other paths are devised so as to facilitate the search for a solution by using a partial constraint having no common part on the path of the path. For this reason, an arrangement result that satisfies the request can be obtained at a high speed with a smaller number of constraints than in the past, and the reduction of the memory used can be achieved at the same time.

Next, step F4 of the first embodiment (FIG. 1)
Another specific example of the constraint generation processing in step F25 (see FIG. 8) of the second embodiment will be described with reference to FIG.

First, terminals and nets constituting a path extracted by the path analysis (see step F4 or step F25) are extracted from the entire circuit, and FIG.
The partial circuit is configured as shown in FIG. In FIG. 9A, white circles indicate terminals, and straight lines indicate wirings connecting the terminals or signal propagation paths in the cell. FIG. 9B is a diagram showing FIG. 9A as a graph. In FIG. 9B, the terminal is represented as a node, and the signal propagation path or net in the cell is represented as an edge. In addition, a start node common to all paths is created at the signal entry side end point of the graph, and an edge is set between the source node of each path. Similarly, an end point node common to all paths is also created at the signal exit side end point of the graph, and an edge is set between the end point node and the sink of each path. For this graph, the maximum value of the delay is determined for all the paths from each node to the end node. Since this is the same as extracting the longest path starting from the node, it can be realized by the same method as calculating the critical path in step F1 or F22. T _{i, j} in FIG. 9B indicates the maximum value of the delay from the node j of PATHi to the end node. Next, the edges branching from the extracted node are rearranged in descending order of the sum of the delay required for a signal to propagate through the edge and the maximum delay from the destination node to the end point of the edge. When viewed from an arbitrary path, a path having the next largest delay after this path is called a parent path of this path, and this path viewed from the parent path is called a child path. By the above-described rearrangement, the parent-child relationship of the paths is represented in a graph, and all the paths branching from the parent path can be rearranged in order from the path with the largest delay.

Next, a timing constraint is imposed on the longest path such that the required time is less than the required time from the start point to the end point of the path in the form of a complete path, and other paths are attached to each edge. A constraint that defines a magnitude relation such that the sum of the delays of the edges after the branch point is equal to or less than the sum of the delays of the edges after the branch point of the parent path is generated so that the obtained order relation is maintained. For example, it is assumed that the path delays have a relationship of PATH1>PATH2> PATH3. In FIG. 9C, the required time is directly generated as a time constraint for the path PATH1 having the longest delay. For PATH2 having the second largest delay after PATH1, a magnitude constraint, T _2,2 ≦ T _1,2, is generated for the branch point node of PATH ₁ . This is because the maximum delay from the node 2 of PATH2 to the destination node is the node 2 of PATH1.
This means that it must be less than the maximum delay from to the destination node. Similarly, PA
For TH3, a magnitude constraint of T _3,3 ≦ T _2,3 is generated for the maximum delay after the branch point from the upper path of PATH3. It should be noted that the size constraints of the edges created as described above can be efficiently referred to in the arrangement processing if they are represented by a constraint graph as shown in FIG. 9D.

Finally, if the delay of the longest path satisfies the requirement and all the child paths of the longest path satisfy the delay constraint, all paths must be shorter than the required time. Is guaranteed, so that the circuit operation is guaranteed.

As described above, according to the above-described specific example, regarding the child path branched from the parent path constraint of the complete path format, the branch point of the parent path must always be greater than the delay of reaching the end point of the branch point transition path. Since the size constraint is defined so that the delay of the subsequent child paths is reduced, timing requirements can be satisfied for all paths, and circuit operation can be guaranteed.

[0044]

As described above, according to the present invention, it is possible to increase the accuracy of delay prediction in critical path analysis and timing constraint generation in placement processing, and to easily optimize timing in placement processing. It is possible to reduce the processing time and the memory used.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure of a first embodiment of a design method according to the present invention.

FIG. 2 is a schematic diagram illustrating terminal restrictions in a net according to the present invention and conventional net restrictions.

FIG. 3 is a schematic diagram illustrating a process of creating a constraint between terminals in a net according to the present invention.

FIG. 4 is a schematic diagram illustrating virtual wiring processing according to the present invention.

FIG. 5 is a graph showing path delay prediction accuracy when delay prediction is performed based on virtual wiring processing according to the present invention.

FIG. 6 is a schematic diagram illustrating a first specific example of a constraint generation process according to the present invention.

FIG. 7 is a schematic diagram illustrating a second specific example of the constraint generation processing according to the present invention.

FIG. 8 is a flowchart showing a processing procedure of a second embodiment of the design method according to the present invention.

FIG. 9 is a schematic diagram illustrating a third specific example of the constraint generation processing according to the present invention.

FIG. 10 is a flowchart illustrating a processing procedure of a conventional design method.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-343522 (JP, A) JP-A-6-232263 (JP, A) JP-A-6-76020 (JP, A) 151303 (JP, A) JP-A-5-120378 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 H01L 21/82

Claims (4)

(57) [Claims] In a semiconductor integrated circuit device in which a plurality of logic cells are arranged on a semiconductor chip and a desired circuit is realized by connecting the logic cells, a connection called a net between cell terminals before arrangement is provided. For information, the average wiring length of each net obtained by subtracting 1 from the number of terminals connected to the net, called the fanout number of the net, is given to all nets, and the path of the signal path propagating through the circuit is given. The analysis is performed, and for all paths that do not satisfy the requirement of the signal propagation time, the time constraint that satisfies the requirement is set from the signal input terminal called the source of the path to the signal output terminal called the sink of the path. Alternatively, based on the first step to be distributed and provided from the source to the sink of each net constituting the path and the set constraints,
A second step of generating an initial arrangement state in consideration of the time constraint; and performing virtual wiring from the arrangement position information of each cell with respect to the initial arrangement state. Based on virtual routing information, delay calculation and path analysis are performed, and for the extracted critical path, timing constraints that satisfy the requirements from the path source to the sink are
Alternatively, the third step of allocating and providing from the source to the sink of each net constituting the path, and, under the set time constraint, improving the arrangement state by successively moving and replacing cells, A fourth step of setting an arrangement state that satisfies all timing constraints. A method for designing a semiconductor integrated circuit device, comprising: 2. A semiconductor integrated circuit device in which a plurality of logic cells are arranged on a semiconductor chip and a desired circuit is realized by connecting the logic cells to each other. A first step of arranging a part thereof on a chip by appropriate means, performing virtual wiring based on the placement result, and performing delay calculation and path analysis using the obtained virtual wiring information. For the extracted critical path, a constraint that satisfies the requirement of the signal propagation time is given from the source of the path to the sink or distributed from the source to the sink of each net constituting the path. A second step, a third step of generating, based on the set constraints, an initial arrangement state in consideration of the constraints, Virtual routing is performed based on the cell placement position information, delay calculation and path analysis are performed using the obtained virtual routing information, and constraints that satisfy the requirements for the extracted critical paths are defined for the paths. A fourth step of providing a distribution from the source to the sink or from the source to the sink of each net constituting the path, and a placement state by successively moving and exchanging cells under set constraints. And a fifth step of improving the above condition so that the arrangement state satisfies all timing constraints. The method for designing a semiconductor integrated circuit device, comprising: 3. A semiconductor integrated circuit device in which a plurality of logic cells are arranged on a semiconductor chip and a desired circuit is realized by connecting the logic cells to each other. When generating a constraint that satisfies the requirement for signal propagation time, when allocating the required time to each net, virtual routing is performed on the placement result, and based on this virtual routing information. Using the calculated net delay or the net delay that can be improved and achieved by the placement improvement processing, a required time is allocated to each net according to the ratio of the predicted delay of the net to the delay of the entire path. A method of designing a semiconductor integrated circuit device. 4. A semiconductor integrated circuit device in which a plurality of logic cells are arranged on a semiconductor chip and a desired circuit is realized by connecting the logic cells to each other. ,
When generating constraints that satisfy the requirements for signal propagation time, the critical path set extracted by path analysis is
The input / output terminal of each cell in the circuit is a node, the signal propagation path and the net in the cell from the input terminal to the output terminal are each an edge, and the start node that connects the source of each path and the end node that connects the sink of each path Is generated, a partial circuit formed by the critical path is represented in a graph, a delay from the branch point node of each edge to the end node of the path is calculated, and the calculated value is assigned to each edge as a weight, All the edges are rearranged in the order of the weight given to the edge, and the order of each edge is determined. For the path with the longest delay (called the longest path), for the edge set constituting the longest path, Generates a time constraint that the delay from the start point to the end point is equal to or less than the required time. For paths other than the longest delay path, the edges that make up the path The constraint is imposed so that the delay from each edge to the end node is less than or equal to the delay of the edge in the higher order so that the order of the edges is maintained before and after the placement processing. Design method for semiconductor integrated circuit devices.