JP3231912B2 - Nonvolatile semiconductor memory device and program method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of electrically writing / erasing data.

[0002]

2. Description of the Related Art FIG. 12 is a sectional view of a typical memory cell of a nonvolatile semiconductor memory device capable of electrically writing / erasing data. FIG. 12 shows a cross section of the memory cell along the channel length direction. As shown in FIG. 12, an N-type source is provided in a P-type silicon substrate 1.
A drain region 2 and an N-type drain region 3 are formed. In the silicon substrate 1 between the source region 2 and the drain region 3, there is provided an electrical connection between the source region 2 and the drain region 3 according to the gate voltage. A channel region 4 is defined. Channel area 4
A first gate insulating film 5 made of a silicon oxide film (SiO ₂ ) is formed thereon, and a floating gate 6 made of conductive polysilicon is formed on the first gate insulating film 5. Have been. On the floating gate 6, a silicon oxide film (SiO ₂ )
Is formed, and a control gate 8 made of low-resistance polysilicon is formed on the second gate insulating film 7.

This type of memory cell is known as an ETOX (Erasable
This is called a Tunnel OXide type, and data is written by injecting channel hot electrons, and data is erased by a first gate between the source region 2 and the floating gate 6. This is performed by flowing an FN tunnel current through the insulating film 5. This is a cell that is often used mainly in NOR-type batch erase EEPROMs.

When data "0" is written into the memory cell having the above structure, that is, when electrons are injected into the floating gate,
Typically, it is performed by the following method. 6V is applied to the drain region 3, and the source region 2 is grounded. In this state, the control gate 8 is normally set at 10 μsec.
The pulse between them is defined as one unit, and the program voltage Vpp (1
2V). As a result, the memory cell becomes conductive, and electrons e move from the source region 2 to the drain region 3 in the channel region 4. At this time, some of the electrons e gain energy by being accelerated near the drain region in the channel region 4 and are then hot electrons (hot electrons) he.
Becomes These thermoelectrons he are drawn into the floating gate 6 by the potential of the control gate 8, so that the floating gate
Electrons e are injected into the gate 6. Such a write operation,
This is performed for each cell.

Further, at present, the following write sequence is adopted. First, for 10 μsec,
After applying the program voltage Vpp to the control gate 8, write verification (verification operation) is subsequently performed to check whether or not the cell has reached a desired threshold value. If it has reached, the write operation is terminated.
The above write / verify is repeated until a desired threshold is reached.

The first reason that such a write sequence is employed is that the above-mentioned memory cells are integrated in an enormous amount in one array, and the program characteristics of each memory cell vary. Secondly, in the batch erasing type EEPROM, since data writing / erasing is repeated, there is a change in program characteristics due to this.

However, in a device that performs a writing operation using 10 μsec as one unit as described above, by repeating writing / erasing, as shown in FIG.
Insufficiency of writing and "1" writing, that is, deterioration of cell threshold voltage is observed. Generally, this is a phenomenon called window narrow wing.

As shown in FIG. 13, electrons are injected during "0" writing, that is, during the floating gate, and the threshold Vt is set to 8V.
For cells distributed in the vicinity, the number of rewrites (P / E cycle)
Exceeds 10 ⁵ times, the threshold voltage Vt drops to about 7V, while on the other hand, writing "1", that is, electrons are extracted from the floating gate, and 2.5V is applied to the cell where the threshold voltage Vt is distributed around 2V. Rise to the extent. As described above, as the number of times of rewriting increases, the intensity of “0” writing and “1” writing each become insufficient.

[0009] Further come beyond the number of times of rewriting 10 ⁵ times, de - so lowering phenomenon of cell current data "1" can be flushed is written cells is observed. This is because by repeating rewriting, the transconductance of the cell becomes small, and it becomes difficult for the cell to flow current. FIG.
This phenomenon will be described with reference to FIG.

FIG. 14 is a diagram showing a relationship between a cell current and a threshold value of a memory cell. The horizontal axis of FIG. 14 shows the distribution of the threshold value Vt of the cell to which the data "1" is written. In the cell to which the data "1" is written, the threshold value Vt is about Distributed over a range of 1-3V. The vertical axis indicates the cell current Icell.

As shown in FIG. 14, the threshold value Vt is about 1
In cells distributed in V, the average is 210 μm in the initial state.
Although A more cell current Icell is obtained, de - in after the number of times of rewriting data (P / E cycles) 10 ⁵ times, are no longer obtained only cell current Icell of about average 190Myuei. Similarly, in the cell in which the threshold value Vt is distributed at about 3 V, the cell current Icell having an average of 100 μA in the initial state
Although is obtained, in the after the number of times of rewriting ¹⁰⁵ times, not only obtained cell current Icell of about an average 80 .mu.A.

[0012]

As described above, in the conventional device, the amount of cell current that can flow through the cell in which data "1" is written gradually decreases as the number of rewrites increases. There was a problem.

When the amount of cell current decreases, the data reading speed slows down and the operation of the device slows down. Yet another problem is that
The cell in which the data "1" is written does not reach the reference current amount due to a decrease in the cell current amount, and the data "0" is not reached.
Is written. this is,
Invert the read data. That is, there is a problem of erroneous reading.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to prevent a deterioration in cell transconductance due to an increase in the number of times of rewriting and to provide a highly reliable nonvolatile semiconductor memory device. And a programming method therefor.

[0015]

In order to achieve the above object, a nonvolatile semiconductor memory device and a method of programming the same according to the present invention include a semiconductor substrate of a first conductivity type and a second semiconductor substrate formed in the substrate. First and second semiconductor regions of a conductivity type, a channel region defined in the base between the first and second semiconductor regions, and a first region on the channel region.
The first semiconductor region for a memory cell composed of a charge storage layer formed with an insulating layer interposed therebetween and an electrode layer formed on the charge storage layer with a second insulating layer interposed By applying a first potential to the second semiconductor region, applying a second potential lower than the first potential to the second semiconductor region, and applying a third potential higher than the second potential to the electrode layer. The cell is made conductive, and the injection of the charge is completed in a state where the potential of the charge storage layer is equal to or higher than the first potential.

In another aspect, a semiconductor substrate of a first conductivity type, and first and second semiconductor substrates of a second conductivity type formed in the substrate.
Semiconductor region, a channel region defined in the base between the first and second semiconductor regions, a charge storage layer formed on the channel region via a first insulating layer, and the charge storage A memory cell composed of an electrode layer formed on a layer with a second insulating layer interposed therebetween,
Applying a first potential to the semiconductor region, applying a second potential lower than the first potential to the second semiconductor region, and applying a third potential higher than the second potential to the electrode layer. And the first charge injection is performed in a state where the potential of the charge storage layer is equal to or higher than the first potential, and the first semiconductor region is lower than the first potential. It is characterized in that the second charge injection is performed by applying a fourth potential to complete the charge injection.

[0017]

According to the nonvolatile semiconductor memory device and the programming method thereof, the injection of the electric charge is completed while the electric potential of the electric charge storage layer is equal to or higher than the first electric potential. The interface state generated between the layer and the surface of the channel region can be suppressed, and the deterioration of the transconductance of the cell caused by this kind of interface state can be improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. In this description, common portions will be denoted by common reference symbols throughout the drawings to avoid redundant description.

FIGS. 1A and 1B are views for explaining a first embodiment of the present invention. FIG. 1A is a sectional view of a memory cell, and FIG.
The figure shows the relationship between the potential of the floating gate and the floating gate current.

FIG. 1A shows a cross section of the memory cell along the channel length direction. As shown in FIG. 1A, in a P-type silicon substrate 1, an N-type source region 2 and an N-type drain region 3 are formed. In the silicon substrate 1 between the source region 2 and the drain region 3, there is provided an electrical connection between the source region 2 and the drain region 3 according to the gate voltage. A channel region 4 is defined. First gate insulating film 5 made of a silicon oxide film (SiO ₂ ) on channel region 4
Are formed. The first gate insulating film 5 has portions overlapping the source region 2 and the drain region 3, respectively. On the first gate insulating film 5, a floating gate 6 made of conductive polysilicon is formed. A silicon oxide film (SiO 2) is formed on the floating gate 6.
_{A second} gate insulating film 7 of ₂ ) is formed, and a control gate 8 made of low-resistance polysilicon is formed on the second gate insulating film 7.

This type of memory cell is an ETOX (Erasable
It is called Tunnel OXide type. Data "0" is written by injecting channel hot electrons, and data is erased or data "1" is written to source region 2 and floating. The first gate insulating film 5 between the gate 6 and
This is performed by flowing an FN tunnel current. Mainly NOR type E
This is a cell often used in EPROM.

In this embodiment, a Vpp voltage is generated to the control gate 8 of the memory cell having the above configuration, and a Vpp voltage generation / supply circuit 10 for limiting the supply time to the control gate 8 is connected. ing. In the Vpp voltage generation / supply circuit 10 in this embodiment, a program voltage Vpp of, for example, 12 V is generated, and this voltage Vpp is controlled by the control gate 8.
In addition, less than a typical supply time of 10 μsec,
For example, supply is performed for 1 μsec to 2 μsec. The supply time is appropriately adjusted depending on the cell structure, particularly the difference in the coupling ratio between the control gate and the floating gate, but is set to be relatively short as compared with the conventional case.

Next, the phenomenon that occurs in the device according to the present invention will be described in detail. FIG. 2 is a diagram showing program characteristics, showing the relationship between the pulse width of the program voltage and the threshold value Vth of one cell.

As shown in FIG. 2, the program voltage Vpp
If the pulse width, that is, the supply time of the voltage Vpp to the control gate is short, the threshold voltage Vth of the cell does not increase so much. There is a tendency that the threshold value Vth of the cell increases as the time becomes longer.

In FIG. 2, an inflection point A where the program characteristic changes is observed at about 1.5 μsec. In a graph in which the horizontal axis is a natural logarithm, if the pulse width is longer than the inflection point A, the pulse becomes longer. The relationship between the width and the threshold value Vth of the cell changes almost linearly, while if the pulse width is shorter than the inflection point A, the above relationship tends to deviate from the straight line.

The inventor of the present application has analyzed and clarified such a difference in change as follows. When electrons are injected into the floating gate, the cell is turned on to generate channel hot electrons. At this time, in a region where the relationship between the pulse width and the threshold value of the cell changes linearly, the relationship between the gate voltage and the cell current (drain current) in the cell corresponds to the pentode region, and the voltage − Hot electrons are generated in a state where the current characteristics are saturated. On the other hand, a region deviating from the straight line corresponds to a triode region, and hot electrons are generated in a state where the voltage-current characteristics increase linearly.

The present inventor has found the following differences between the case where the cell operates in the pentode region and the case where the cell operates in the triode region. 4A and 4B are diagrams showing interface states in a memory cell. FIG. 4A shows a state where the cell operates in a pentode region, and FIG. 4B shows a state where the cell operates in a triode region. FIG.

As shown in FIG. 4A, when electrons are injected while the cell operates in the pentode region, that is, when writing of data "0" is completed, the interface state 9 is changed to the channel region 4. Occurs frequently at the interface between the substrate 1 and the first gate insulating film 5 in a state of contact with the substrate. When the interface state 9 frequently occurs in a state where the interface state 9 is in contact with the channel region 4, the interface state directly acts on the channel current and significantly reduces the cell current.

However, as shown in FIG.
When writing of data "0" is completed in a state where the cell operates in the triode region, the interface state 9 does not contact the channel region 4, and the drain region 3 and the first gate insulating film 5 Occurs at the interface. That is, the generation point of the interface state 9 is the channel region 4
To the drain region 3. The drain region 3 has a lower resistance than the channel region 4. Therefore, the decrease amount of the cell current caused by the interface state 9 is smaller than that in the case where the interface state 9 is generated in the channel region 4.
The effect is reduced.

FIG. 3 is a diagram showing the relationship between the program voltage pulse width and the amount of decrease in cell current. 3, the horizontal axis represents the pulse width of the program voltage Vpp, and the vertical axis represents the cell current flowing in the initial state and the P / E cycle 10 ^5.
The difference ΔIcell from the cell current flowing after the current is shown.

A cell having the program characteristics shown in FIG. 2 and having a threshold value Vt distributed at 3 V is selected for this monitor. The voltage Vcg is applied to the control gate of such a cell.
= 5V and the voltage Vd = 1V to the drain,
Data "1" was read, and the cell current was measured.

As shown in FIG. 3, the pulse width is set to 10 μs
When “0” is completed and rewriting is repeated while the cell is operating in the pentode region with the cell set to c, the cell current decreases by about 16 μA.

On the other hand, when the pulse width is set to 1.5 μsec and the cell is operating in the triode region, “0” is set.
When the writing is completed and the rewriting is repeated, the amount of decrease is about 8 μA, which is a half of the conventional case.

The point A in FIG. 3 corresponds to the inflection point A in FIG. Therefore, to suppress the decrease in cell current,
It is effective to avoid writing "0" as much as possible after the inflection point A in FIG. 2, that is, while the cell is operating as a pentode.
As a means for achieving this, the length of a pulse used when writing / verifying is made shorter than the inflection point A in FIG. As a result, it is possible to prevent “0” writing from being performed after the inflection point A.

As described above, by writing "0" with the pulse width shorter than the inflection point A in FIG. 2, the generation point of the interface state is shifted to the area where the influence is minimized. As a result, deterioration of the transconductance of the cell accompanying an increase in the number of rewrites can be prevented, and a decrease in the cell current can be prevented.

Next, another example of the specific conditions under which the "0" write operation can be completed while the cell is operating in the triode region will be described. In the above example, the program characteristic diagram as shown in FIG. 2 is created, the inflection point A is specified from the characteristics shown in this diagram, and the pulse width is made shorter than the inflection point A, thereby changing the cell to a triode. It has been described that “0” writing can be completed while operating in the region. This can be realized by the method described below.

First, when there is a cell having a program characteristic as shown in FIG. 2, a floating gate current Ifg is obtained from the following equation (1). Ifg = Cpp × ΔVth / t (1) In the above equation (1), Cpp is the capacitive coupling between the floating gate and the control gate, Vth is the threshold value of the cell, and t is the time indicating the pulse width. It is.

By calculating the floating gate current Ifg based on the above equation (1) and calculating the floating gate potential Vfg in consideration of the coupling ratio and the charge in the floating gate, FIG. The relationship shown in (b) can be obtained.

The point A shown in FIG. 1B corresponds to the inflection point A shown in FIG. The region a shown in FIG.
The FET is a triode region, and the region b is a pentode region. As described above, by determining the “0” write pulse width so that the floating gate potential Vfg becomes equal to or higher than the drain voltage Vd, “0” write similar to the above-described example can be achieved. Effects can be obtained.

Next, an example of a nonvolatile semiconductor memory device suitable for embodying the present invention will be described. FIG. 5 is a block diagram schematically showing a first example of a nonvolatile semiconductor memory device suitable for carrying out the present invention.

As shown in FIG. 5, the memory cell array 11
There are a plurality of erase blocks E1 in the array 11.
To E1024. In each erase block, memory cells MC are arranged in a matrix or array, and erasing / writing can be performed independently for each erase block. Among the memory cells, those having the same row have their control gates connected to the same word line WL. Among the memory cells, those in the same column have drains connected to the same bit line BL.
The plurality of erase blocks share a bit line and are connected to one sense amplifier 12 which is shared by each bit line. The sources of the memory cells are connected in common for each erase block, and the common source line CSL specified by the source decoder 14 can apply a potential independently.

In an apparatus in which an erase block is divided into a plurality of pieces, as in the apparatus having the above configuration, data rewriting frequently concentrates only on a specific erase block, and the number of rewrites tends to be biased on a specific erase block. Can be seen. This is because data is not uniformly stored in the entire memory cell array, and some frequently used cells and some rarely used cells are generated.

As described above, when the number of times of rewriting is biased for a specific erase block, the cell current of only the erase block significantly deteriorates. Eventually, the level of degradation
When the difference from the level of deterioration in the other erase blocks increases, the risk of erroneous reading increases. Particularly, as shown in FIG. 5, the possibility is high when each erase block shares a sense amplifier.

In such an apparatus, if "0" is written as described above, the cell current can be prevented from deteriorating even if the number of times of rewriting increases, and erroneous reading due to uneven distribution of the number of times of data rewriting can be prevented. The danger can be very low.

FIG. 6 is a block diagram schematically showing a second example of a nonvolatile semiconductor memory device suitable for embodying the present invention. As shown in FIG. 6, the basic configuration of this device is the same as that of the device shown in FIG. 5, except that electrons escape from the drain and the stored data is lost over time. Refresh circuit 2 for refreshing stored data in order to solve the problem of
0 is provided. That is, in the case where the data is not rewritten and the data is subsequently stored, the address data of the "0" write cell among the data is temporarily stored.
The data is stored in a storage unit such as a latch circuit provided in the refresh circuit 20. Subsequently, based on the stored data, the same "0" data is written again to refresh the data.

With the above device, the problem of drain disturb can be solved. However, the number of "0" write operations is significantly increased due to data refresh.
There is a concern.

In such an apparatus, by performing the above-mentioned "0" writing, it is possible to prevent a decrease in cell current due to an increase in the number of times of data rewriting, and to maintain high reliability while maintaining high reliability. Life can be extended.

Next, a second embodiment of the present invention will be described. FIG. 7 is a diagram showing the deterioration of the program characteristics as the number of rewrites increases. Deterioration of program characteristics is shown in FIG.
It occurs like At this time, the inflection point A in the initial state moves to the point A 'by repeating data rewriting. For this reason, in order to realize a program as fast as possible, it is preferable to gradually increase the length of the pulse used for writing “0” when performing write / verify as the number of rewrites increases.

FIG. 8 shows a typical flow for realizing the second embodiment. First, st. In step 1, it is determined whether the number of rewrites (the number of P / E cycles) is equal to or greater than a reference number. If the number is equal to or less than the reference number (No), st. Proceeding to step 2, write "0" to all the cells in the batch erase block or only the cells in which "1" data is stored. This is a step called a pre-program performed to solve the problem of over-erasure.

When the number is equal to or larger than the reference number (YES), s
t. Proceeding to 3, the operation of increasing the pulse width used for writing "0", that is, the supply time of the program voltage Vpp to the control gate by a predetermined amount is performed. This change in the supply time can be realized by, for example, changing the count number of a counter that measures the supply time by counting the number of system clocks. After this, the pre-program step (s
t. Proceed to 2).

The writing of data "0" performed in the pre-program is performed in the same manner as the above-described "0" writing. Next, when data "0" is written to all cells in the batch erase block and the pre-program step is completed, st. The process proceeds to step 4, and data "1" is sequentially written to all the cells in the batch erase block. That is, the operation of extracting electrons from the floating gate is equivalent to the operation of erasing data. Then, st. 5
Then, data is read from the cell in which "1" has been written, and it is verified whether the threshold value of the cell has dropped to a desired value. This is a step generally called erase verify. If the data does not reach the desired value (NG), the flow returns to the data erasing operation (st. 4) again, and data "1" is written again. Such an operation is repeated until the desired value is reached.
When the threshold values of all the cells have reached the desired values at which the data should be "1" (OK), the erase operation ends.

Next, at st. Proceed to 6. st. Numeral 6 is a data writing operation, based on the data to be stored.
Data "0" or data "1" is written to the cell. Here, the above-mentioned "0" writing is used for writing the data "0". Then, st. In step 7, data is read from the written cell, and it is verified whether the threshold value of the cell has decreased or increased to a desired value. This is a step generally called write verify.
If the data does not reach the desired value (NG), the flow returns to the data writing operation (st. 6) again, and data "0" or "1" is written again. Such an operation is repeated until the desired value is reached. When the threshold values of all cells have reached the desired values (OK), the write operation ends.

Next, st. Proceed to 8. st. At step 8, the number of data rewrites (the number of P / E cycles) is incremented by one to update the number of rewrites. Thereafter, st. 9 and go to st. In step 8, the updated number of rewrites (the number of P / E cycles) is stored. The number of rewrites stored here is the value of st. In the next data rewriting step. It is used as the number of rewrites in 1. s
t. After storing the updated number of rewrites in step 8, the data rewrite process is completed.

Next, a third embodiment of the present invention will be described. 9A and 9B are diagrams showing the relationship between program characteristics and program points. FIG. 9A shows a case where the drain voltage is 6V, and FIG. 9B shows a case where the drain voltage is 6V.
It is a figure which shows the case of V.

As shown in FIG. 9A, when the desired cell threshold Vth level of data "0", that is, the program point B is located higher than the inflection point A, for example, the drain voltage Vd = 6 V, writing may be performed with two 5 μsec pulses.

Further, as another example, as shown in FIG. 9B, the first operation may be performed with the drain voltage Vd = 6V, and the second operation may be performed with the drain voltage Vd = 5V. In this way, "0" writing in the pentode region can be further reduced, which is more effective in suppressing a decrease in cell current. The reason will be described below.

As shown by the line I in FIG. 9B, in the program characteristics at the drain voltage Vd = 6 V, the inflection point A is located below the program point B. For this reason, in order to increase the cell threshold value Vth to the program point B, "0" writing in the pentode region is necessary especially at the time of the second "0" writing.

However, as shown by the line II, in the program characteristics at the drain voltage Vd = 5 V, the inflection point A is located above the program point B. Therefore, even if the cell threshold value Vth is increased up to the program point B, "0" writing can always be performed in the triode region.

In order to increase the cell threshold value Vth up to the program point B, the drain voltage Vd may be set to 5 V and the pulse may be performed only once, since "0" can be written in the triode region. .

However, if "0" writing is performed once,
A pulse supply time of 10 μsec or more is required, which takes time. Therefore, "0" write is divided into two times and
The second drain voltage Vd is increased to 6 V, and the cell threshold value Vth in the range of the triode region is increased, for example, to the last.
By performing the “0” writing by lowering the second drain voltage Vd to 5 V, the time required for writing can be reduced.

FIG. 10 shows a typical flow for realizing the third embodiment. First, st. In step 1, "0" is written into all cells in the batch erase block or only cells in which "1" data is stored (preprogramming). Data "0" performed in this pre-program
Is performed by setting the drain voltage Vd to 6 V, for example, and is performed in the same manner as the above-described “0” writing.

In the preprogramming, "0" writing may be divided into two times and the second drain voltage Vd may be set lower than that in the first time, but it is not always necessary to do so. . This is because preprogramming is a method for preventing over-erasing, and in particular, electrons are further extracted (in other words, holes are injected) from a floating gate which originally has no electrons, and thus strong pre-programming is performed. This is because it is a technique for preventing the toner from being charged. That is, the above object can be achieved by eliminating the floating gate without electrons.

Next, when data "0" is written to all cells in the batch erase block and the pre-program step is completed, st. The program proceeds to step 2, and data "1" is sequentially written to all the cells in the batch erase block (erase operation).

Next, st. Proceeding to 3, the data is read from the cell in which "1" has been written, and it is verified whether the threshold value of the cell has dropped to a desired value (erase verify). If the data does not reach the desired value (NG), the flow returns to the data erasing operation (st. 2) again, and data "1" is written again. Such an operation is repeated until the desired value is reached.
When the threshold values of all the cells have reached the desired values at which the data should be "1" (OK), the erase operation ends.

Next, at st. Proceed to 4. st. 4 is a data write operation. Based on the data you want to store,
Data "0" or data "1" is written to the cell. Here, the above-mentioned "0" writing is used for writing the data "0". Then, st. Proceeding to step 5, data is read from the cell in which the writing has been performed, and it is verified whether the threshold value of the cell has decreased or increased to a desired value (write verification). If it does not reach the desired value (NG), the data
Data write operation (st. 4). 6
In particular, when data "0" is being written, an operation of lowering the drain voltage is performed. For example, if the first “0” write is performed with the drain voltage Vd being 6 V, for example, the drain voltage Vd is set to 5 in the second write
V. After lowering the drain voltage Vd in this way,
Data "0" is written again. Such an operation is repeated until the desired value is reached. When the threshold values of all cells have reached the desired values (OK), the write operation ends.

If the threshold value does not reach the desired value even in the second "0" write, the third "0" write is started. At this time, as the drain voltage Vd used for the third “0” writing, the drain voltage Vd used for the second “0” writing may be used as it is. Such a cell is a cell whose program characteristic is slightly shifted from an initial design value due to a variation at the time of manufacturing. At the time of the third “0” writing, “0” writing is performed in the pentode region. Have the potential to be However, by estimating the threshold value Vth at which "0" is to be written and considering a variation at the time of manufacture, and setting a certain margin, almost no cells having such a possibility can be obtained. In addition, "0" in the first, second and triode regions
Since writing is performed, "0" writing in the pentode region, which will occur at the third time, can significantly reduce the amount of injected electrons. Thereby, the generation of the interface state is suppressed. From such a viewpoint, it is considered that there is no problem in ignoring "0" writing in the pentode region which would occur in the third and subsequent times from a practical viewpoint.

However, it is conceivable that the necessity of the above-mentioned margin compression or the like may be considered as the technology advances in the future, for example, as the operation at a lower voltage is performed. Therefore, the third operation is performed after the drain voltage Vd is further lowered than that in the second operation. In this way, the number of cells to which “0” is likely to be written in the pentode region can be further reduced.

When the threshold values of all the cells reach the desired values through the above-described write verification (OK),
The write operation ends. Next, a fourth embodiment of the present invention will be described.

FIG. 11 is a diagram showing the relationship between program characteristics and program points, and shows a case where the control gate voltage Vcg is increased from 12 V to 13 V while the drain voltage Vd is kept at 6 V.

The control gate voltage Vcg is changed from 12 V to 13 V
When the voltage is boosted to
It is possible to shift to the higher th direction. From this, by increasing the control gate voltage Vcg, the program point B can be set to the inflection point A or lower, and "0" writing in the pentode region can be prevented.

As described above, without changing the structure of the device itself, for example, the coupling ratio between the control gate and the floating gate, the supply voltage to the control gate at the time of writing "0" can be reduced. By changing it, the program characteristics can be changed.

As another example, the program characteristics can be changed by changing the amount of channel dove (for example, boron) of the cell. For example, if the amount of the channel dove is increased, a program characteristic having a tendency similar to that of FIG. 11 can be obtained, and the program point B can be set to the inflection point A or lower.

According to the present invention which has been described with reference to the plurality of embodiments, the "0" writing in the pentode region, that is, the injection of electrons into the floating gate is minimized, and the "0" writing in the triode region is minimized. To solve the problems of deterioration of cell conductance due to increase in the number of times of rewriting and reduction of cell current by completing "0" writing and completing injection of electrons into the floating gate in the triode region. Can be. Therefore, stable data reading can be performed without causing a problem of erroneous reading for a long period, and a nonvolatile semiconductor memory device having high reliability and long life can be obtained.

Further, with respect to the window narrow wing phenomenon, the point that the threshold value of the "0" write cell is lowered can be particularly improved. In a device in which an erase block is divided into a plurality of blocks, by applying the present invention, even if the number of times of data rewriting is unevenly distributed between erase blocks, the characteristics between cells due to the uneven distribution can be improved. The variation amount can be reduced, and the effect can be more remarkably obtained.

In an apparatus in which an erase block is divided into a plurality of pieces and data is refreshed, first,
As described above, the amount of variation in characteristics between cells due to uneven distribution of the number of times of data rewriting can be reduced. Even if the number of times of “0” writing is increased by performing further refreshing,
The problem of deterioration of cell conductance and reduction of cell current can be solved, and the life of the device can be extended.

As described in the second embodiment, the desired cell is increased by increasing the "0" write pulse width in accordance with the deterioration of the program characteristic of the cell as the number of rewrites increases. The threshold value Vth can be reached as quickly as possible. For this reason, in addition to the above effects, it is possible to prevent the writing time from being prolonged due to the increase in the number of rewrites, and to operate at high speed over a long period.

Further, as described in the third embodiment, when the desired cell threshold is higher than the cell threshold at the inflection point of the program characteristic found by the present inventor, "0" is set. By dividing the writing, 5
"0" writing in the arc tube region can be reduced as much as possible, and as described above, a nonvolatile semiconductor memory device having high reliability and long life can be obtained.

Further, the third embodiment is modified to make the drain voltage Vd used for the second "0" write lower than that of the first "0" write, thereby further writing the "0" in the pentode region. And the effects of improving reliability and extending the life can be more remarkably obtained.

Further, as described in the fourth embodiment, the amount of the control gate voltage used for writing "0"
Alternatively, the program characteristic can be adjusted by changing the channel drop amount of the cell, and the desired cell threshold can be made lower than the threshold at the inflection point. Techniques like these can be used for cells of various structures,
This is useful as a method for constantly performing “0” writing in the triode region.

[0080]

As described above, according to the present invention, it is possible to prevent the deterioration of the transconductance of the cell due to the increase in the number of rewrites, and to provide a highly reliable nonvolatile semiconductor memory device and its programming method. .

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams for explaining a first embodiment of the present invention. FIG. 1A is a sectional view of a memory cell, and FIG. 1B is a diagram showing the potential and the floating gate of a floating gate. The figure which shows the relationship with an electric current.

FIG. 2 is a diagram showing a relationship between a program voltage pulse width and a cell threshold Vth.

FIG. 3 is a diagram illustrating a relationship between a program voltage pulse width and a decrease amount of a cell current;

4A and 4B are diagrams showing an interface state in a memory cell. FIG. 4A is a diagram showing a case where the cell operates in a pentode region, and FIG. 4B is a diagram showing that the cell is in a triode region. FIG.

FIG. 5 is a block diagram schematically showing a first example of a nonvolatile semiconductor memory device suitable for carrying out the present invention;

FIG. 6 is a block diagram schematically showing a second example of a nonvolatile semiconductor memory device suitable for carrying out the present invention;

FIG. 7 is a diagram showing a relationship between a program voltage pulse width and a cell threshold Vth for explaining a second embodiment of the present invention;

FIG. 8 is a flowchart according to a second embodiment of the present invention.

FIGS. 9A and 9B are diagrams for explaining a third embodiment of the present invention. FIG. 9A is a diagram illustrating a “0” write threshold point B.
FIG. 4B is a diagram showing the relationship between the inflection point A and the inflection point A. FIG.

FIG. 10 is a flow chart according to a third embodiment of the present invention.
Chart.

FIG. 11 is a diagram illustrating a relationship between a program voltage pulse width and a cell threshold value Vth for explaining a fourth embodiment of the present invention;

FIG. 12 is a cross-sectional view of a typical memory cell of a nonvolatile semiconductor memory device capable of writing / erasing data.

FIG. 13 is a view showing a window narrow wing.

FIG. 14 is a diagram showing a decrease in cell current.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P type silicon substrate, 2 ... N type source region, 3 ... N type drain region, 4 ... channel region, 5 ... 1st gate insulating film, 6 ... floating gate, 7 ... 2nd gate -Gate insulating film, 8 ... control gate, 9 ... interface state, 10 ... Vpp voltage generation / supply circuit.

Claims (6)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, first and second semiconductor regions of a second conductivity type formed in the substrate, and the substrate between the first and second semiconductor regions. A charge storage layer formed on the channel region via a first insulating layer, and an electrode layer formed on the charge storage layer via a second insulating layer. A memory cell, a circuit for applying a first potential to the first semiconductor region, and a second cell lower than the first potential to the second semiconductor region.
A circuit for applying a potential, the first potential and the second potential to the first semiconductor region.
With the second potential applied to the semiconductor region of
Applying a third potential higher than the second potential to the pole layer; and
The potential of the charge storage layer is equal to or higher than the first potential;
Complete the injection of charges into the charge storage layer
And a circuit . 2. A semiconductor substrate of a first conductivity type, first and second semiconductor regions of a second conductivity type formed in the substrate, and a semiconductor substrate between the first and second semiconductor regions. A charge storage layer formed on the channel region via a first insulating layer, and an electrode layer formed on the charge storage layer via a second insulating layer. A method for programming a nonvolatile semiconductor memory device having memory cells, comprising: applying a first potential to the first semiconductor region; and applying a second potential lower than the first potential to the second semiconductor region. the memory cell is conductive, while the potential of the charge storage layer is equal to or greater than the first potential, said charge storage by providing higher third potential than the second potential to the electrode layer JP to complete the injection of charges into the layer Programming method of a nonvolatile semiconductor memory device according to. 3. A semiconductor substrate of a first conductivity type, first and second semiconductor regions of a second conductivity type formed in the substrate, and a semiconductor substrate between the first and second semiconductor regions. A charge storage layer formed on the channel region via a first insulating layer, and an electrode layer formed on the charge storage layer via a second insulating layer. A memory cell, a circuit for applying a first potential to the first semiconductor region, and a second cell lower than the first potential to the second semiconductor region.
A circuit for applying a potential, the first potential to the first semiconductor region,
In a state where the second potential is applied to the second semiconductor region,
Applying a third potential higher than the second potential to the electrode layer;
When the potential of the charge storage layer is higher than the first potential,
The first charge injection is performed in the state where
Applying a fourth potential lower than the first potential to the conductor region;
The second charge injection is performed in
A circuit for completing injection of electric charge . 4. A semiconductor substrate of a first conductivity type, wherein
Formed first and second semiconductor regions of second conductivity type,
Defined in the substrate between the first and second semiconductor regions.
Channel region, a first insulating layer on the channel region
Charge storage layer formed through
And an electrode layer formed thereon with a second insulating layer interposed therebetween.
Memory cell array in which memory cells to be arranged are arranged , and addresses of memory cells in which electric charges are injected into the electric charge storage layer.
A storage unit for storing the
Based on the dress, the charge is injected into the charge storage layer.
The charge is injected again into the memory cell to refresh the data.
And a refresh circuit for switching
Nonvolatile semiconductor memory device. 5. The program voltage, main in erase block
It is supplied to the control gate of the memory cell for a predetermined time to
For pre-programming data into memory cells in a memory block
When, data from a memory cell in which the data has been pre-programmed
Erasing the data, and the memory cell from which the data has been erased.
Writing the data to be stored in the memory cell, and after writing the data to be stored in the memory cell,
Updating the number of times data is rewritten , and
The predetermined time supplied to the control gate is determined by rewriting the data.
Depending on the number of nonvolatile half, characterized in that the increased
A method for programming a conductor storage device. 6. Data is stored in a memory cell in an erase block.
Pre-programming the data from a memory cell in which the data is pre-programmed.
Erasing the data, and the memory cell from which the data has been erased.
The drain voltage of this memory cell as the first voltage.
Writing data to be stored, and reading data from the memory cells to which the data has been written.
And the data to be stored is normally written
Whether or not the data to be stored is written correctly.
If it is determined that the memory cell is not
A second voltage lower than the first voltage;
And writing the data to be stored again.
A nonvolatile semiconductor memory device
Program method.