JP3230662B2 - Multi-channel echo canceller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an echo canceller for processing an echo generated by an increase in line delay in a communication line for transmitting a multiplex signal.

[0002]

2. Description of the Related Art Conventionally, an adaptive filter used in this type of echo canceller is realized mainly by an algorithm called a learning identification method. The calculation by this algorithm mainly includes an estimation operation (update of a filter coefficient) and generation of a pseudo echo signal (convolution integration of a filter coefficient and a reference signal). These processes require a calculation amount proportional to the number of filter coefficients (hereinafter referred to as the number of taps) corresponding to the length (time) of the echo path to be estimated. For example, in the case of an adaptive filter having the number of taps N, the calculation processing amount can be roughly indicated by 2N times of estimation operation + 1N times of pseudo echo generation = 3N times.

FIG. 3 is a block diagram showing a configuration of such a conventional echo canceller corresponding to a multiplex signal.
In FIG. 1, an input signal Sin (Mux) including an echo component obtained by multiplexing a plurality of channels is input to a demultiplexer circuit 10 and is divided into signals of respective channels. On the other hand, the reference signal Rin (Mux) is
0 and is divided into signals of each channel. Then, the input signal y (t) and the reference signal x (t) divided into each channel are supplied to the echo canceller circuit 30 corresponding to each channel.

Each echo canceller circuit 30 has an adaptive FI for performing the above-described estimation operation and generating a pseudo echo signal.
R (finite impulse response) filter 32, estimation operation determination circuit (DT Det) 34 for determining the timing of echo estimation, and subtraction for subtracting the input signal of each channel from the pseudo echo signal. And a vessel 36. Then, the output signal d of each channel from which the echo has been removed by each echo canceller circuit 30
(T) is input to the multiplexer circuit 40, multiplexed, and output as an output signal Sout (Mux).

[0005]

However, in the above-described conventional multi-channel echo canceller, as shown in FIG. 3, adaptive FIR filters corresponding to the respective channels individually perform processing. There is a problem in that an arithmetic processing amount of 3N times is required, an arithmetic mechanism (hardware) required for the processing is required, and the circuit scale is enlarged.

However, the actual echo estimation operation does not need to be performed almost in a single call as shown in the following non-estimation operation conditions (a) to (c). (Non-estimating operation conditions) (a) When the estimation of the echo path is completed (b) When the reference signal is small and is not suitable for the estimation (c) When in a two-way communication state and it is desirable to stop the estimation

That is, the estimation process is performed only when only one person is speaking and has sufficient power for the audio signal. Under such conditions, the effect of estimation is expected most. The estimation processing is most required in the echo removal when the estimation of the echo path is not completed. On the other hand, in the conventional method which individually supports the echo processing of each channel as described above, it cannot be said that the physical processing mechanism for performing the estimation processing and the processing time are efficiently used, and the hardware is wasted. There is a problem that occurs.

Accordingly, an object of the present invention is to perform more efficient processing by integrating echo processing of a large number of channels into a multiplexed signal of a plurality of channels transmitted on a communication line. Another object of the present invention is to provide a multi-channel echo canceller capable of simplifying hardware.

[0009]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a multi-channel echo for performing echo processing on an input signal including an echo component in which a plurality of channels transmitted on a communication line are multiplexed. In the canceller, a canceller circuit is provided for each channel and performs echo processing of the input signal of each channel based on a reference signal provided for each channel, and performs echo estimation processing based on the input signal of each channel. An estimation channel selection circuit for selecting a channel to be performed; an estimation processing circuit for performing echo estimation processing of the channel selected by the estimation channel selection circuit; and a control signal output by the estimation processing by the estimation processing circuit, A supply circuit for selectively supplying the canceller circuit of the channel selected by the selection circuit, The serial control signals, characterized in that it has to update the process state of an echo processing in each canceller circuit.

In the above-described multi-channel echo canceller of the present invention, the estimation channel selection circuit selects the channel for which the echo estimation processing is performed with the highest priority based on the input signal of each channel. The estimation processing circuit receives the signal of the channel selected by the estimation channel selection circuit and performs echo estimation processing on this channel.
Then, as a result of the echo estimation processing, a control signal is supplied to the canceller circuit of the channel, and a coefficient for echo processing in the canceller circuit is updated. With the above operation, the estimation processing of each channel can be performed by a small number of estimation processing circuits, so that it is not necessary to provide an estimation processing circuit individually for each channel and perform the estimation processing. The structure of the wear can be simplified.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multi-channel echo canceler according to the present invention will be described below. FIG.
FIG. 2 is a block diagram illustrating a configuration of a multi-channel echo canceller according to the present embodiment. In the figure, an input signal Sin including an echo component obtained by multiplexing a plurality of channels is shown.
(Mux) is input to the demultiplexer circuit 110,
It is divided into signals of each channel. On the other hand, the reference signal Rin
(Mux) is input to the demultiplexer circuit 120,
It is divided into signals of each channel. Then, the input signal y (t) and the reference signal x (t) divided into each channel are output to the echo canceller circuit 130 corresponding to each channel.
Supplied to

Each echo canceller circuit 130 has an FIR (finite impulse) for generating a pseudo echo signal.
response; finite length impulse response) filter 132
And an estimation operation determination circuit (DT Det) 134 for determining the timing of echo estimation, and a subtractor 136 for subtracting the input signal of each channel from the pseudo echo signal. Then, the output signal d (t) of each channel from which the echo has been removed by each echo canceller circuit 130 is input to the multiplexer circuit 140, multiplexed, and output as an output signal Sout (Mux). The output signal of each echo canceller circuit 130 is supplied to the estimation processing circuit 300 via the selector 210.

The estimation processing circuit 300 includes an output signal of each echo canceller circuit 130 selectively supplied via selectors 210, 220 and 230, a reference signal of each channel, and a filter coefficient value of the FIR filter 132. Performs echo estimation processing of the channel based on
It has an adaptive FIR filter 310 for updating the filter coefficients. Then, the filter coefficient value updated by the adaptive FIR filter 310 is supplied to the estimation channel selection circuit 400 as a control signal, and is also supplied to the FIR filter 132 of the corresponding echo canceller circuit 130 via the selector 240.

The estimation channel selection circuit 400 determines a channel to be echo-estimated according to the estimation request signal supplied from the estimation operation determination circuit (DT Det) 134 and the update state of the filter coefficient in each echo canceller circuit 130. And the selectors 210, 220, and 23 described above.
0 and 240, and selectively performs echo estimation processing (filter coefficient update processing) for each channel.

Next, a more detailed configuration and operation of the above-described multi-channel echo canceller will be described. FIG. 2 is a block diagram showing a configuration of the estimation channel selection circuit 400. The estimation channel selection circuit 400 receives the estimation request supplied from the estimation operation determination circuit 134 of each echo canceller circuit 130 and, when a plurality of estimation requests compete, selects them under certain conditions. 410. Further, the estimation channel selection circuit 4
Reference numeral 00 denotes power calculation circuits 420 and 430 for taking in the filter coefficients before and after the update processing of the currently selected channel and performing power calculation, respectively, and each power calculation circuit 4
It has a comparison circuit 440 that compares the outputs of the comparators 20 and 430 and calculates the comparison value (difference), and a storage circuit 450 that stores the output of the comparator 440 together with the channel number.

In the selection circuit 410, when a plurality of estimation requests from the estimation operation judgment circuit 134 compete with each other,
With reference to the storage contents of the storage circuit 450, the estimation request is compared with the change amount of the filter coefficient of each channel competing for the estimation request,
The request for estimating the channel having the largest change amount is selected, and the selection signal output circuit 460 is controlled to output the selection signal to each of the selectors 210, 220, 230, and 240. In other words, the estimation channel selection circuit 400 determines that the larger the amount of change in the filter coefficient (difference before and after the estimation), the more unstable the estimation is, that is, the estimation is not completed, and preferentially selects the estimation channel. .

Next, an estimation operation determination circuit (DT Det) 13
Reference numeral 4 is for monitoring the call state of each channel, determining the timing of echo estimation, and outputting an estimation request to the selection circuit 410 of the estimation channel selection circuit 400. That is, the estimation operation determination circuit 134 outputs the reference signal (x (t))
Is compared with the power of the input signal (y (t)) including the echo component, and is estimated when the power of x (t) is sufficiently larger than the power of y (t) (for example, a difference of 12 dB). And outputs an estimation request.

As described above, in the echo canceller requiring multi-channel processing, one estimation processing circuit 30
By setting the value to 0, the estimation processing is performed only on the selected limited channels, so that there is an effect that the total amount of arithmetic processing can be reduced and the processing mechanism can be simplified. For example, in the case of an echo canceller composed of an N-tap FIR filter having M channels (assuming 4), assuming a calculation amount of 2N times for the estimation operation and 1N times for the pseudo echo generation, In the method, M (2N + 1N) = 3MN = 12N, but in the present invention, M (1N) + 2N = MN + 2N = 6N, and in this case, the calculation amount or the processing mechanism is reduced to about half. Becomes possible.

In the above example, the estimation processing of a plurality of channels is performed by one estimation processing circuit 300. However, the number of the estimation processing circuits 300 is not limited to one, but may be two or more. It may be.

[0020]

As described above, according to the present invention, in a multi-channel echo canceller for performing echo processing on an input signal including an echo component in which a plurality of channels transmitted on a communication line are multiplexed, For many canceller circuits that perform channel echo processing, while continuing the echo processing of each canceller circuit, determine the necessity of performing estimation processing for each channel, select a canceller circuit that performs estimation processing, The estimation processing is performed in a time-division manner by a small number of estimation processing circuits. Therefore, the estimation processing of each channel can be performed by a small number of estimation processing circuits.
It is not necessary to provide an estimation processing circuit individually for each channel to perform the estimation processing, and the configuration of hardware for performing the estimation processing can be simplified. Further, since such estimation processing for each channel and updating of echo processing in each canceller circuit are performed in parallel with echo processing in each canceller circuit, echo processing in each channel can be performed without interrupting echo processing in each channel. It is possible to optimize the processing. Therefore, the echo processing can be optimized without disturbing the communication of each channel, and the communication quality of each channel can be appropriately maintained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a multi-channel echo canceller according to the present invention.

FIG. 2 is a block diagram showing a configuration example of an estimation channel selection circuit in the multi-channel echo canceller shown in FIG.

FIG. 3 is a block diagram showing an example of a conventional multi-channel echo canceller.

[Explanation of symbols]

110, 120 ... Demultiplexer circuit, 130 ...
Echo canceller circuit, 132 ... FIR filter, 1
34 ... Estimation operation determination circuit, 136 ... Subtractor, 140
... Multiplexer circuit, 210, 220, 230, 2
40 ... selector, 300 ... estimation processing circuit, 310 ...
... Adaptive FIR filter, 400 ... Estimated channel selection circuit, 410 ... Selection circuit, 420, 430 ... Power calculation circuit, 440 ... Comparison circuit, 450 ... Storage circuit, 4
60 ... Selection signal output circuit.

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04B 3/00-3/44

Claims (14)

(57) [Claims] A plurality of channels transmitted on a communication line
In a multi-channel echo canceller that performs echo processing on an input signal containing a multiplexed echo component, a multi-channel echo canceller is provided for each channel, and based on a reference signal provided for each channel, A canceller circuit that performs an echo process; an estimation channel selection circuit that selects a channel on which an echo estimation process is performed based on the input signal of each channel; and an estimation process that performs an echo estimation process on the channel selected by the estimation channel selection circuit. and a circuit, wherein the control signal output by the estimating processing circuit according estimation process, and a selectively supplying supply circuit to the canceller circuit of the channel selected by the estimated channel selection circuit, the canceller by the control signal Echo in the circuit
A multi-channel echo canceller characterized by updating a processing state of processing . 2. The canceller circuit has a filter for generating a pseudo echo signal from the reference signal of each channel, and the control signal of the estimation processing circuit is a signal for updating a filter coefficient in the filter of the canceller circuit. 2. The multi-channel echo canceller according to claim 1, wherein: 3. The multi-channel echo canceller according to claim 1, wherein the filter of the canceller circuit generates a pseudo echo signal by performing a convolution operation of the reference signal of each channel and the filter coefficient. . 4. The multi-channel echo canceller according to claim 2, wherein said canceller circuit has a subtraction circuit for subtracting an input signal of each of said channels and a pseudo echo signal output from said filter. . 5. The estimation channel selection circuit monitors a communication state of each channel, and selects a channel for performing an echo estimation process based on an output signal of an estimation operation determination circuit that determines a timing of echo estimation. The multi-channel echo canceller according to claim 2, wherein 6. The estimation operation determination circuit compares the power of the input signal of each channel and the power of the reference signal, and determines that the timing of echo estimation is reached when the power of the input signal is greater than the power of the reference signal by a predetermined value or more. 6. The multi-channel echo canceller according to claim 5, wherein the determination is made and an estimation request is output to the estimation channel selection circuit. 7. The estimation channel selection circuit includes storage means for storing, for each channel, information on a control amount of each canceller circuit by echo estimation processing executed in the past, and a plurality of estimation operation determination circuits. 7. The multi-channel echo canceller according to claim 6, wherein when an estimation request is made, a canceller circuit for performing an echo estimation process is selected based on the information stored in said storage means. 8. The information of the control amount is information of a fluctuation value of the control signal before and after the echo estimation processing executed in the past, and when the fluctuation value is large, the echo estimation processing is not performed. 8. The multi-channel echo canceller according to claim 7, wherein a canceller circuit that performs echo estimation processing preferentially is selected by determining that the echo is stable. 9. The filter of the canceller circuit is an FI
3. The multi-channel echo canceller according to claim 2, wherein the multi-channel echo canceller is an R filter. 10. The estimation processing circuit according to claim 1, wherein the estimation processing circuit comprises an adaptive filter for selectively inputting a reference signal of each channel and an output signal of each canceller circuit and updating a filter coefficient. Multi-channel echo canceller. 11. The multi-channel echo canceller according to claim 10, wherein said adaptive filter is a FIR adaptive filter. 12. A circuit according to claim 1, further comprising a dividing circuit for dividing the multiplexed input signal into input signals for respective channels and supplying the divided signals to the respective canceller circuits.
The multi-channel echo canceller described in the paragraph. 13. The apparatus according to claim 1, further comprising a division circuit for dividing the multiplexed reference signal into reference signals for each channel and supplying the divided reference signals to each of said canceller circuits.
The multi-channel echo canceller described in the paragraph. 14. The multi-channel echo canceller according to claim 1, further comprising a multiplexing circuit that multiplexes and outputs a signal output from each of said canceller circuits.