JP3226656B2 - AD converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gain error-free AD (analog-to-digital) converter using a ΔΣ modulator.

[0002]

2. Description of the Related Art An A / D converter for performing A / D conversion using a .DELTA..SIGMA. Modulator includes an integrating means for integrating an analog input signal (converted signal) and a reference signal, a quantizing means for quantizing an output signal of the integrating means, and an integrating means. A ΔΣ mode comprising feedback means for controlling the reference signal to invert or invert according to the output of the quantization means and to integrate the reference signal.
The modulator has a durator and a digital filter for inputting an output signal of the ΔΣ modulator . In such an AD converter, a range of an analog input signal to be AD-converted (AD conversion range) is given by a reference signal. To suppress the Δ と り modulator from oscillating, take the analog input signal as 1 / n times the reference signal,
A gain correction of n times is performed by a digital filter at the subsequent stage of the ΔΣ modulator, and the gain of the resulting code with respect to the analog input signal is set to a predetermined value (US Pat. No. 4,518,841).

[0003]

However, in the above-mentioned conventional example, an element for introducing an analog input signal into the ΔΣ modulator and an element for introducing a reference signal are separate. Therefore, the ratio between the analog input signal and the reference signal in the ΔΣ modulator may be 1 / (n + α) instead of 1 / n due to the variation between the individual elements. In this case, if the digital filter section performs n-times gain correction, the output code includes an n / (n + α) -times gain error from a predetermined value. In order to further correct this, in each AD converter, a gain error is calculated in advance, the calculated value is stored, and correction calculation is performed on each AD conversion value based on the stored value. Must. Therefore, it takes time to calculate the gain error and time to perform the correction calculation in advance, and furthermore, a circuit for calculating the gain error, a circuit for storing the gain error, and a circuit for performing the correction calculation. There is a problem that the circuit of the above is required.

An object of the present invention is to solve the above-mentioned problems and to provide an AD converter free from a gain error.

[0005]

In order to achieve the above object, the present invention provides an integrating means for integrating an analog input signal and a reference signal, a quantizing means for quantizing an output signal of the integrating means, and the quantizing means. AD converter comprising a Δ フ ィ ー ド バ ッ ク modulator comprising feedback means for controlling the reference signal to perform normal or inverted inversion in accordance with the output, and a digital filter to which the output signal of the ΔΣ modulator is inputted. The analog input
Signal and the reference signal
Selection means for outputting to the common input element of the integration means is provided.
In addition, the selection means is provided between the determination times of the quantization means.
The analog input signal and the reference signal are predetermined.
Output to the common input element of the integrating means in time division
Characterized in that it.

[0006]

According to the present invention, the analog input signal and the reference signal are selectively supplied to the integrating means via a common element, so that a memory element or a circuit for correcting a gain error due to a variation between input elements is required. Disappears.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The AD converter receives an analog input signal (conversion signal) and a reference signal for setting an AD conversion range, selects one of them by time-division using a selection signal, and outputs the selected signal. It has a ΔΣ modulator 2 for inputting an output signal from the means 1 and a digital filter 3 for inputting an output signal from the ΔΣ modulator 2 and outputting an AD conversion code.

FIG. 2 shows a specific example of the selection means 1 and the ΔΣ modulator 2, and the ΔΣ modulator 2 is constituted by a switched capacitor filter. FIG. 3 is a timing chart showing the operation. This example is manufactured as an LSI by a CMOS process, and each switch is an MO.
It consists of a transfer gate using an S transistor.

[0010] As shown in FIG.
W1, SW2 and an inverter 4 are provided. The ΔΣ modulator 2 includes capacitors C1 to C6, switches SW2
SW18, operational amplifiers A1 and A2, comparator CP and logic circuit 5 are provided.

Each switch is opened and closed by clocks S1 to S6 having a relationship as shown in FIG. The conversion signal and the reference signal are alternately selected by SW1 and SW2 at a ratio of 1: 3 with respect to the cycle of the clock S1. That is, when SW1 is 1, SW2 is closed at a ratio of 3. First, when the selection signal is 1, the conversion signal is output to the Δ を 通 し て modulator through SW1, and when the selection signal is 0, the reference signal is output through SW2.
出力 Output to the modulator. In response to this, in the ΔΣ modulator, the logic circuit 5 responds to the selection signal or the judgment output (“1” or “0”) from the comparator CP obtained as described later, as follows. S5 and S6 are created based on S1 and S2,
By S2, S5 and S6, SW3 to SW on both sides of C1
6 is opened and closed to accumulate signal charges in C1, and C2 is stored in C2.
One charge is added or subtracted.

(1) When the selection signal is 1, S5 and S6 become S5 = S1 and S6 = S2. First, the converted signal is stored in C1 at the timing of S1, and the charges stored in C1 at the timing of S2. Is integrated into C2.

(2) When the selection signal is 0 and the comparator CP
Is S1, S5 = S2, S6 = S1. First, both sides of C1 are connected to the analog ground at the timing of S1, and the reference signal charge stored in C1 is subtracted from C2 at the timing of S2. . This operation is repeated until the selection signal becomes 1 as shown in FIG.
Do it twice.

(3) When the selection signal is 0 and the comparator CP
Is S0 = S1 and S6 = S2, the reference signal charge is first stored in C1 at the timing of S1, and the reference signal charge stored in C1 is added to C2 at the timing of S2. . This operation is performed three times until the selection signal becomes 1 as shown in FIG.

As described above, the voltage at the node A in FIG. 2 changes as shown in FIG. The sampling period of the ΔΣ modulator is four times S1 as shown by S3 and S4, which coincides with four integration operations by C1. S
3, SW7 to SW10 that open and close according to S4
The point voltage information is accumulated and integrated in C3 and C4. The resulting voltage at node B changes as shown in FIG.

The voltage information at the points A and B is represented by S3, S4
SW11 to SW18 and C5, C6 that open and close according to
, And the result is obtained as voltage information at the node C as shown in FIG. The comparator CP updates the judgment output of the voltage information at the point C at the judgment time indicated by Δ in FIG. 3, and inputs the same to the logic circuit 5 as described above.

In this embodiment, since the ratio between the converted signal range value and the reference signal is 1/3, the digital filter 3 at the subsequent stage gives a gain of three times. The gain with respect to the converted signal (analog input signal) becomes 1 times the predetermined value. Further, the ratio between the reference signal and the converted signal range value is desirably a ratio between integers. In this case, an input can be given by using a common input element by the number of times corresponding to the integer.

[0018]

As described above, according to the present invention, the analog input signal and the reference signal are selectively supplied to the integrating means via the common element, so that the gain error due to the variation between the input elements can be corrected. And an AD converter free of a gain error without the need for the storage element or circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram of the embodiment.

FIG. 3 is an operation explanatory diagram of the embodiment.

[Explanation of symbols]

 C1, C2 Capacitor SW1 to SW18 Switch

Claims (1)

(57) [Claims] 1. An analog input signal and a reference signal
Integrating means for integrating the output signal, and quantizing an output signal of the integrating means.
The quantization means and the output according to the output of the quantization means.
Control to integrate the reference signal forward or reverse.
Control meansΔΣ modulator
And saidΔΣ modulatorDigital output
In the AD converter consisting of the filterAny of the analog input signal and the reference signal
And outputs it to the common input element of the integrating means.
Selection means, wherein the selection means is
During the judgment time, the analog input signal and the reference
Signal and a common ratio of the integrating means in a predetermined ratio by time division.
Output to input element An AD converter characterized in that: