JP3219068B2 - Programmable delay generator and application circuit using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable delay generator that generates a pulse that rises with a time delay set by digital data, using an input pulse as a trigger. The present invention also relates to a frequency synthesizer that generates an arbitrary frequency from a certain reference frequency using the programmable delay generator.

[0002] The present invention also relates to a multiplier using the programmable delay generator to obtain an output signal having a frequency that is an integral multiple of the frequency of an input signal. Also, the present invention relates to a duty ratio conversion circuit that converts the duty ratio of an input signal to a predetermined value and outputs the converted signal using the programmable delay generator.

[0003]

2. Description of the Related Art FIG. 12 shows a configuration example of a conventional programmable delay generator (reference: Allolog Devices, Linear Data Book 1994/1995, pp. 12-36 to 12-6).
Four).

In FIG. 12, an integrator is formed by a current source 82, a capacitor 83 and a switch 84. The trigger circuit 81 opens and closes the switch 84 according to the leak signal 401 and the trigger signal 402, and the integrator outputs the ramp wave voltage V
Generate s. On the other hand, the latch 85 outputs the latch signal 403
Latches the setting data 404 according to the D / A converter 8
Set to 6. The D / A converter 86 generates a threshold voltage Vk proportional to the setting data. The comparator 87 compares the ramp voltage Vs with the threshold voltage Vk, and outputs a pulse that rises at a timing when the two voltages match. The one-shot 88 receives the output pulse of the comparator 87 and outputs a pulse having a pulse width corresponding to the time constant τ to the output signal output terminal 405.

FIG. 13 is a time chart showing an operation example of a conventional programmable delay generator. In addition, the code of each input / output terminal is substituted for the code of each signal.
(a) is a trigger signal 402, (b) is a latch signal 403, (c)
Is the setting data 404, (d) is the leak signal 401, (e) is the ramp voltage Vs which is a voltage across the capacitor 83, and (f) is D
The threshold voltage Vk, (g), which is the output voltage of the / A converter 86, indicates the output signal 405 of the programmable delay generator (one-shot 88).

First, the setting data 404 is latched in synchronization with the latch signal 403, and the D / A converter 86 outputs a threshold voltage Vk proportional to the setting data 404. The threshold voltage Vk is obtained by dividing the unit voltage of the D / A converter 86 by V
Assuming that ₀ and the setting data are K, Vk = −K · V ₀ (1)

Next, with the trigger signal 402 input as a trigger, a current flows through the capacitor 83, and the ramp voltage Vs changes. The ramp voltage Vs at time t, the current value of the current source 82 I, a capacitance value of the capacitor 83 C, when the rise time of the trigger signal 402 to _{t 0, Vs = - (I} / C) · (t −t ₀ )... (2)

Next, the comparator 87 outputs the threshold voltage Vk
And the ramp wave voltage Vs coincidence is detected. Time from time t ₀ until Vk and Vs match, ie, output signal 4
The delay time td before the rise of the clock signal 05 is expressed as td = (K · V ₀ · C) / I (3) from the equations (1) and (2). This output signal 405 is a one-shot 88
Falls after the elapse of the time constant τ. Also, the leak signal 4
01 causes the capacitance 83 to leak, and the ramp voltage Vs is initialized.

As described above, the conventional programmable delay generator can generate a delay time proportional to the setting data K expressed by the equation (3).

[0010]

By the way, with the performance enhancement of the frequency synthesizer, a fractional delay time in which both the numerator and the denominator are variable is required. Such a fractional delay time is required, for example, when extracting a jitter-free signal from the output signal of the accumulator, or when reducing the spurious of a fractional-N PLL frequency synthesizer.

However, the conventional programmable delay generator can generate a delay time proportional to the setting data K but cannot generate a fractional delay time as shown in the equation (3). Further, as shown in the equation (3), since the delay time includes the circuit constants V ₀ , C, and I, each adjustment is indispensable to improve the absolute accuracy of the delay time.

According to equation (3), the current of the current source 82
Fractional delay time can be generated by changing the value I.
Function, but circuit constants to improve absolute accuracy of delay time
V₀ , C, and I need to be adjusted.
Thus, in the conventional programmable delay generator, the delay
Frequency synthesizers that require absolute delay time accuracy
Application to is difficult.

On the other hand, by using a conventional programmable delay generator, a pulse is generated from an input signal at intervals shorter than the cycle of the input signal, thereby obtaining an output signal having a frequency that is an integral multiple of the frequency of the input signal. Or
When the duty cycle of an input signal is converted to a predetermined value by determining the time from the rise to the fall of the output pulse with a programmable delay generator, and the output is to be converted to a predetermined value, the circuit constant must be adjusted to the frequency of the input signal. Adjustments must be made. Even when the input frequency is fixed, the conventional programmable delay generator needs to adjust the circuit constants V ₀ , C, and I to improve the absolute accuracy of the delay time.

According to the present invention, there is no need to adjust circuit constants.
It is an object of the present invention to provide a programmable delay generator capable of generating a fractional delay time that can be set by both the numerator and the denominator with high accuracy. It is another object of the present invention to provide a frequency synthesizer that can generate a low spurious output signal without adjustment by using the programmable delay generator.

Still another object of the present invention is to provide a multiplier capable of generating a low spurious output signal without adjustment by using the programmable delay generator as a multiplier. It is still another object of the present invention to provide a duty ratio conversion circuit that can convert a duty ratio with high accuracy without adjustment by using the programmable delay generator as a multiplier.

[0016]

SUMMARY OF THE INVENTION A programmable delay generator according to the present invention comprises a threshold voltage generating circuit for generating a threshold voltage Vk proportional to setting data K, and a ramp for generating a ramp wave voltage Vs proportional to setting data S. The wave generation circuit is realized with the same circuit configuration. Thus, when comparing the threshold voltage Vk and the ramp voltage Vs, the effects of the circuit constants of the two circuits on the delay time can be offset, and the delay time is determined by the fraction of the setting data K and S. Can be. That is, a fractional delay time can be generated without adjustment.

Further, the programmable delay generator of the present invention can improve the absolute accuracy of the delay time by synchronizing the operations of the threshold voltage generation circuit and the ramp generation circuit with an external clock.

The frequency synthesizer of the present invention can obtain an arbitrary amount of delay without adjustment by using the programmable delay generator of the present invention as a means for phase interpolation in a direct digital synthesizer. An output signal can be generated.

The multiplier of the present invention uses the programmable delay generator of the present invention as a means for generating pulses at intervals shorter than the period of an input signal, thereby generating output pulses aligned at exactly equal intervals without adjustment. Therefore, an output signal with low jitter and low spurious can be obtained.

By using the programmable delay generator of the present invention as a means for determining the pulse width of the output signal, the duty ratio conversion circuit of the present invention can convert the duty ratio into a high-precision duty ratio without adjustment.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment of Programmable Delay Generator) FIG. 1 shows a first embodiment of a programmable delay generator according to the present invention.

In the figure, a ramp generation circuit 10A comprises
It comprises a data selector 11, a latch 12, a current switch array 13, a switch 14, a capacitor 15, an S-side enable signal input terminal 101, a setting data S input terminal 102, and an S-side leak signal input terminal 103. Output the ramp wave voltage Vs. The threshold voltage generating circuit 20A includes a data selector 21, a latch 22, a current switch array 23, a switch 24, a capacitor 25, a K-side enable signal input terminal 201, a setting data K input terminal 202, and a K-side leak signal input terminal 203. , And outputs a threshold voltage Vk as a voltage across the capacitor 25. A common clock input terminal 301 is connected to the ramp wave generation circuit 10A and the threshold voltage generation circuit 20A.

The ramp generation circuit 10A and the threshold voltage generation circuit 20A have the same circuit configuration, and include the capacitance values C of the capacitors 15 and 25 and the unit current I of the current switch arrays 13 and 23.
Circuit constants such as ₀ are manufactured with the same value. This can be easily realized by integrating both circuits on the same substrate.

The comparator 31 compares the ramp voltage Vs and the threshold voltage Vk, and outputs a pulse which rises at a timing when the two voltages match. One shot 32
Receives the output pulse of the comparator 31 and outputs a time constant τ
Is output to the output signal output terminal 302.

FIG. 2 shows a first example of the programmable delay generator.
6 is a time chart illustrating an operation example of the embodiment. In addition, the code of each input / output terminal is substituted for the code of each signal. (a) is a clock signal 301, (b) is setting data K, (c) is setting data S, (d) is a K-side enable signal 201, (e) is an S-side enable signal 101, and (f) is a threshold voltage. Vk, (g) is the ramp voltage Vs, and (h) is the output signal 3.
02, (i) is the K-side leak signal 203, and (j) is the S-side leak signal 103.

When the K-side enable signal 201 rises, the data selector 21 sets the setting data K input terminal 202
Is connected to the latch 22. The latch 22 outputs the setting data K input terminal 20 at the rising edge of the clock 301 input first after the rising edge of the K-side enable signal 201.
The setting data K is taken in from Step 2. Accordingly, the current switch array 23 allows a current proportional to the setting data K to flow, and the threshold voltage Vk, which is the voltage across the capacitor 25, decreases. Here, assuming that the time at which the clock 301 rises next after the threshold voltage Vk has dropped for the first time is t ₀ , and the clock cycle is T, the time t since the threshold voltage Vk has dropped for the first time
Threshold voltage Vk at _{(t 0 -T ≦ t ≦ t} 0) is, Vk = _- represented by (KI 0 / C) · ( t-t 0 + T) ... (4).

Next, control is performed so that the K-side enable signal 203 falls and the S-side enable signal 103 rises from time t ₀ -T to time t ₀ . Then, the latch 22 takes in the initial value ₀ at time t0, the current switch array 23 is turned off, the decrease of the threshold voltage Vk stops, and the sample switch enters the sample hold state. Thereafter (t ≧
The threshold voltage Vk of t ₀ ) is represented by Vk = − (KI ₀ / C) · T (5)

On the other hand, the latch 1 of the ramp generation circuit 10A
2 fetches the configuration data S from the setting data S input terminal 102 via the data selector 11 at time _{t 0.} Accordingly, the current switch array 13 causes a current proportional to the setting data S to flow, and the ramp voltage Vs, which is a voltage across the capacitor 15, decreases. Ramp voltage Vs at time _{t 0} after the time t, Vs = _- represented by (SI 0 / C) · ( t-t 0) ... (6).

Next, the comparator 31 sets the threshold voltage Vk
And the ramp wave voltage Vs coincidence is detected. Time from time t ₀ until Vk and Vs match, ie, output signal 3
02 rise time td (= t−t ₀ )
Is represented by td = (K / S) · T (7) from the equations (5) and (6). This output signal 302 is the one-shot 32
Falls after the elapse of the time constant τ.

The capacitors 25 and 15 are leaked at the rise of the K-side leak signal 203 and the S-side leak signal 103, and the threshold voltage Vk and the ramp voltage Vs return to the initial values. The timing of each leak signal may be after the coincidence of Vk and Vs is detected and the output signal 302 is output. In FIG. 2, both rise at t ₀ + T and t ₀ +2
Although it is set to fall at T, the output signal 302
May be fed back as each leak signal.

As described above, the programmable delay generator of the present embodiment can generate a delay time proportional to the fraction K / S expressed by the equation (7). K and S that form this fraction are setting data that can be set arbitrarily, and a delay time can be generated by an arbitrary fraction.

The reason why the circuit constant is not included in the equation (7) is that the ramp wave generating circuit 10A and the threshold voltage generating circuit 20
Circuit constants of A, that is, since the unit current _{I 0} of the capacitance value C and the current switch array 13 and 23 of the capacitor 15, 25 were the same value. If the ramp wave generation circuit 10A and the threshold voltage generation circuit 20A having the same configuration are manufactured, no adjustment is required even if the values of the respective circuit constants are different from the design values, and the influence on the generated delay time is also reduced. Absent. Also,
The operation of the ramp wave generating circuit 10A and the operation of the threshold voltage generating circuit 20A are synchronized with the clock 301 input from the outside, and the time during which the decrease of the threshold voltage Vk continues is accurately synchronized with the clock. Can be improved in absolute accuracy.

(Second Embodiment of Programmable Delay Generator) FIG. 3 shows a second embodiment of the programmable delay generator of the present invention.

In the figure, the ramp generation circuit 10B comprises:
Latches 12-1, 12-2, a current switch 16, a switch 14, a capacitor 15, a voltage divider 17, an S-side enable signal input terminal 101, a setting data S input terminal 102, and an S-side leak signal input terminal 103 are provided. The capacitance voltage Vsc output as the voltage between both ends of the voltage divider 15 is divided by the voltage divider 17 to output the ramp voltage Vs. The threshold voltage generation circuit 20B includes the latches 22-1 and 22-2, the current switch 2
6, switch 24, capacitor 25, voltage divider 27, K-side enable signal input terminal 201, setting data K input terminal 20
2. A capacitor voltage Vkc, which is constituted by a K-side leak signal input terminal 203 and is output as a voltage across the capacitor 25, is divided by a voltage divider 27 to output a threshold voltage Vk. A common clock input terminal 301 is connected to the ramp wave generation circuit 10B and the threshold voltage generation circuit 20B.

The ramp wave generating circuit 10B and the threshold voltage generating circuit 20B have the same circuit configuration, the capacitance value C of the capacitors 15 and 25, the current value I ₀ flowing through the current switches 16 and 26, and the voltage dividing devices 17 and 27. Circuit constants such as the pressure reference value M are assumed to be manufactured with the same value. This can be easily realized by integrating both circuits on the same substrate.

The comparator 31 compares the ramp voltage Vs and the threshold voltage Vk, and outputs a pulse that rises at a timing when the two voltages match. One shot 32
Receives the output pulse of the comparator 31 and outputs a time constant τ
Is output to the output signal output terminal 302.

FIG. 4 shows a second example of the programmable delay generator.
6 is a time chart illustrating an operation example of the embodiment. In addition, the code of each input / output terminal is substituted for the code of each signal. (a) is the clock 301, (b) is the setting data K, (c) is the setting data S, and (d) is the K-side enable signal 2.
01, (e) is the S-side enable signal 101, (f) is the capacitance voltage Vkc, (g) is the capacitance voltage Vsc, (h) is the threshold voltage Vk,
(i) is the ramp voltage Vs, (j) is the output signal 302, (k)
Is the K-side leak signal 203 and (l) is the S-side leak signal 103
It is.

First, the setting data K is input from the setting data K input terminal 202, and the K-side enable signal 201 rises. The latch 22-1 captures the K-side enable signal 201 in synchronization with the rising edge of the clock 301, and the latch 22-2 captures the setting data K in synchronization with the rising edge of the clock 301. Current switch 26 is initially applying a current I ₀ at this timing, capacitive voltage Vkc a voltage across the capacitor 25 decreases. Here, assuming that the time when the clock 301 rises next from the first time when the capacitance voltage Vkc decreases for the first time is t ₀ and the clock cycle is T, the time t (t ₀ −T ≦ t) from the first time when the capacitance voltage Vkc decreases for the first time.
The capacitance voltage Vkc at ≦ t ₀ ) is represented by Vkc = − (I ₀ / C) · (t−t ₀ + T) (8)

Next, control is performed so that the K-side enable signal 201 falls and the S-side enable signal 101 rises from time t ₀ -T to time t ₀ . Then, the latch 22-1 so that the off current switch 26 at time t _0, stops the lowering of the capacitance-voltage Vkc, a sample-and-hold state. Thereafter, the capacitance voltage Vkc (t ≧ t ₀ )
Is represented by Vkc = − (I ₀ / C) · T (9)

The capacitance voltage Vkc is input to the voltage divider 27, divided into a voltage proportional to the setting data K held in the latch 22-2, and output as a threshold voltage Vk. The threshold voltage Vk output from the voltage divider 27 is expressed as follows: Vk = (K / M) · Vkc (10) Here, the divided voltage reference value M is a maximum value of K or a value larger than K, and is a value specific to the type of the voltage divider 27. R-2 widely used as a voltage divider 27
When using an R resistor network or a potentiometer type resistor network, M is the maximum value of K + 1. Note that the voltage divider 2
7 is not sufficiently higher than the output impedance of the integrator constituted by the switch 24, the capacitor 25 and the current switch 26, an impedance conversion such as a voltage follower is provided between the integrator and the voltage divider 27. Just insert the container.

According to the equations (9) and (10), the threshold voltage Vk is represented by the following equation: Vk = − (K / M) · (I ₀ / C) · T (11)

On the other hand, at time _{t 0,} the latch 12-1 of the ramp generator circuit 10B takes in the S-side enable signal from the S-side enable signal input terminal 101, the latch 12-2 is set data from the setting data S input terminal 102 Capture S. The current switch 16 initially applying a current I ₀ at this timing, capacitive voltage Vsc is the voltage across the capacitor 15 decreases. Capacitive voltage Vsc at time _{t 0} after the time t, Vsc = _- represented by (I 0 / C) · ( t-t 0) ... (12).

The capacitance voltage Vsc is input to the voltage divider 17, divided into a voltage proportional to the setting data S held in the latch 12-2, and output as a ramp voltage Vs. The ramp wave voltage Vs output from the voltage divider 17
Is represented by Vs = − (S / M) · (I ₀ / C) · (t−t ₀ ) (13)

Next, the comparator 31 sets the threshold voltage Vk
And the ramp voltage Vs match. V from the time _{t 0}
k, Vs, the output signal 30
Delay time td before 2 rises (= t−t ₀ )
Is represented by td = (K / S) · T (14) from the equations (11) and (13). This output signal 302 is the one-shot 32
Falls after the elapse of the time constant τ.

The capacitors 25 and 15 are leaked at the rise of the K-side leak signal 203 and the S-side leak signal 103, and the threshold voltage Vk (capacitance voltage Vkc) and the ramp voltage Vs (capacity voltage Vsc) return to the initial values. . The timing of each leak signal may be after the coincidence of Vk and Vs is detected and the output signal 302 is output. In FIG. 4, both are set so as to rise at t ₀ + T and fall at t ₀ + 2T, but the output signal 302 may be fed back as each leak signal.

As described above, the programmable delay generator according to the present embodiment can generate a delay time proportional to the fraction K / S expressed by the equation (14). K and S that form this fraction are setting data that can be set arbitrarily, and a delay time can be generated by an arbitrary fraction.

The reason why the circuit constant is not included in the equation (14) is that the ramp wave generation circuit 10B and the threshold voltage generation circuit 20
B, the circuit constant of B, that is, the capacitance value C of the capacitors 15 and 25, the current value I ₀ flowing through the current switches 16 and 26,
This is because the reference values M of the partial pressures 7 and 27 are the same. If the ramp wave generation circuit 10B and the threshold voltage generation circuit 20B having the same configuration are manufactured, no adjustment is required even if the values of the respective circuit constants are different from the design values, and the influence on the generated delay time is also reduced. Absent. The operation of the ramp wave generation circuit 10B and the operation of the threshold voltage generation circuit 20B are synchronized with the clock 301 input from the outside, and the time during which the threshold voltage Vk continues to decrease is also accurately synchronized with the clock. The absolute accuracy of the delay time can be improved.

(First Embodiment of Frequency Synthesizer) FIG. 5 shows a first embodiment of the frequency synthesizer.

In the figure, the frequency synthesizer comprises an accumulator 40A, a data conversion circuit 50A, a control circuit 6
0A, the programmable delay generator 70 of the present invention described above.
It consists of. The accumulator 40A includes the adder 4
1A and a latch 42A. The setting data S input from the setting data S input terminal 102 is set in the adder 41A and the programmable delay generator 70 of the accumulator 40A. Clock input terminal 301
Is supplied to the latch 42A of the accumulator 40A and the programmable delay generator 70.

FIG. 6 is a diagram for explaining the operation principle of the accumulator 40A. The number of bits n of the accumulator is 3, and the setting data S is 3. The _MSB of the most significant bit θ _MSB of the output data θ of the accumulator matches S = 3 pulses within a period of 2 ⁿ = 8 clock cycles. Therefore, the average frequency f ₀ is obtained by setting the clock frequency to f
_Assuming that _CLK , f ₀ = (S / 2 ⁿ ) f _CLK (15) This accumulator, by itself, is the simplest form of a direct digital synthesizer, and many other types of direct digital synthesizers are also used for calculating phase signals.

However, the accumulator alone includes a large jitter in the output signal θ _MSB as shown in FIG. Since the jitter appears as a large unnecessary wave component (spurious component) in the observation of the frequency spectrum, it is difficult to apply the accumulator alone to the local oscillator for the wireless device. To suppress this spurious component, the most common direct digital synthesizer uses a ROM
Is used to generate a sine wave as an output.

As another method for suppressing spurious components, there is known a means of phase interpolation (reference: V. Rei
nhardt et al., “A short survey of frequency synthe
sizer techniques ”, in Proc. 40th Annual Frequency
Control symp., Pp. 355-365, May 1986). As shown in FIG. 6, the phase interpolation means delays each pulse of the output signal θ _MSB for each pulse to generate θ _ideal . The delay amount δt of this pulse is represented by δt = ((2 ⁿ⁻¹ −θp) / S) · T (16), where θp is the value of θ immediately before the rising of the _MSB . For example, since the value θp of θ immediately before the first θ _MSB rises is 3, since the first θ _{MSB is} delayed by δt = ((4-3) / 3) · T = T / 3 , Θ _ideal coincide with the first pulse.

As a conventional means for phase interpolation, a delay generator in which the threshold voltage generation circuit and the ramp wave generation circuit shown in the prior art are configured by different circuits (reference: H. Nosaka e)
t al., “A phase interpolation direct digital synth
esizer with a digitally controlled delay generato
r ”, in 1997 Symp. VLSI Circuits Dig., pp.75-76, Ju
ne 1997) and a delay generator that switches the delay line taps (Reference: VNKochemasov et al., “Digital-
computer synthesizers of two-level signalswith pha
se-error compensation ”, Telecommunications and ra
dio engineering, vol. 36/37, pp. 55-59, Oct. 1982). However, these delay generators, as described in the related art, have a problem that the delay amount needs to be adjusted in order to improve the accuracy, and it is difficult to adjust the unit delay time.

The programmable delay generator of the present invention described above can obtain an arbitrary amount of delay without adjustment. Therefore, as shown in FIG. 5, a direct digital synthesizer using this as a means for phase interpolation is: It is possible to obtain a low spurious output without any adjustment.

The output data θ of the accumulator 40A is
The most significant bit θ _MSB is input to the programmable delay generator 70 as the S-side enable signal 101 while being input to the data conversion circuit 50A and the control circuit 60A. The S-side enable signal 101 functions as a trigger signal for starting the delay generation by the programmable delay generator 70 as described above.

The data conversion circuit 50 A calculates the numerator data 2 ⁿ⁻¹ −θp of the equation (16) and outputs the setting data K to be given to the programmable delay generator 70. The data conversion circuit 50A can constitute this subtraction operation by a subtraction circuit, but the same result can be obtained by a simpler 2's complement operation (operation of inverting each bit of θp and further adding 1). The control circuit 60A is composed of a simple digital circuit, outputs a signal delayed by one clock after inverting the signal of the most significant bit θ _MSB as the S-side leak signal 103, and outputs the signal at the timing when the most significant bit θ _MSB rises. A signal that rises before the clock and has a pulse width of one clock cycle is output as a K-side enable signal 201. An output signal of the programmable delay generator 70 is taken out to an output signal output terminal 302 and fed back to the programmable delay generator 70 as a K-side leak signal 203.

With such a configuration, the programmable delay generator 70 generates a delay time represented by the equation (16), and the frequency synthesizer shown in FIG. 5 has a small spurious component whose fundamental frequency is represented by the equation (15). Output a square wave.

FIG. 7 is a time chart showing an operation example of the first embodiment of the frequency synthesizer. (a) is the clock 301, (b) is the output data θ of the accumulator 40A, (c) is the most significant bit θ _MSB of the output data θ, (d)
Is the ramp voltage Vs, and (e) is the K-side enable signal 20.
1, (f) is the threshold voltage Vk, (g) is the output signal 302, (h)
Is the K-side leak signal 203 and (i) is the S-side leak signal 103
It is.

The bit number n of the accumulator 40A is n
Is 3, and the setting data S is 3. Also, the most significant bit θ
The timing after one clock period of the rise of the _MSB is made to coincide with the initial time t ₀ of the delay process.

The ramp wave voltage Vs is proportional to the setting data S, and is a ramp wave synchronized with a signal obtained by delaying one cycle of θ _MSB (S-side enable signal 101).
The K-side enable signal 201 rises one clock before the timing when the θ _MSB rises and has a pulse width of 1
This is a signal of a clock cycle. This K-side enable signal 2
01 as a trigger, the threshold voltage Vk is
A ramp wave having a length of one clock cycle proportional to the setting data K (= 2 ^n-1 -θp) output from A is formed, and its voltage is held. Ramp voltage Vs and threshold voltage Vk
, The output signal 302 having a pulse width determined by the one-shot time constant τ is output at that timing. The output signal 302 is fed back to the programmable delay generator 70 as the K-side leak signal 203, resetting the threshold voltage Vk and preparing for the next threshold voltage generation. The S-side leak signal 103 is a signal obtained by inverting the signal of the most significant bit θ _MSB and delaying it by one clock,
The ramp voltage Vs is reset. By the above operation,
An output signal 302 in which each pulse is arranged at equal intervals and has no jitter
Is obtained.

When a toggle flip-flop (T-FF) is added to the output terminal, it is possible to obtain a rectangular wave synthesizer output having a duty ratio of 50%. In this case, the fundamental frequency is half of the expression (15).

FIG. 8 shows experimental results of the first embodiment of the frequency synthesizer. Programmable delay generator 70
The first embodiment shown in FIG. 1 was used. The digital circuit was constituted by CMOS standard logic. The clock frequency is 200 kHz, the number of bits n of the accumulator 40A is 8, the setting data S is 96, and the basic frequency f ₀ of the programmable delay generator 70 is f ₀ = (96/256) · f _CLK = ( 3/8) · f _CLK = 7
5 kHz. In this experiment, a T-FF was added to the output terminal to obtain a rectangular wave having a duty ratio of 50%, and the output frequency was set to 37.5 kHz. (a) is a clock signal 301, (d) is a ramp voltage Vs, (f) is a threshold voltage Vk, and (g) is a rectangular wave output signal with a duty ratio of 50%.

FIG. 9 shows an output signal spectrum as an experimental result of the first embodiment of the frequency synthesizer. T
-The unnecessary frequency (spurious component) other than the reference frequency 37.5 kHz of the FF output and its harmonics is greatly suppressed.
It can be seen that the maximum is -50 dBc or less.

(Second Embodiment of Frequency Synthesizer) FIG. 10 shows a second embodiment of the frequency synthesizer using the programmable delay generator of the present invention.

In the figure, an accumulator 40B, a data conversion circuit 50B, a control circuit 6
0B, comprising the programmable delay generator 70 of the present invention. The accumulator 40B includes an adder 41B and a latch 42B. The setting data S input from the setting data S input terminal 102 is set in the adder 41B and the programmable delay generator 70 of the accumulator 40B. The clock input from the clock input terminal 301 is supplied to the latch 42 of the accumulator 40B.
B and programmable delay generator 70.

The output data θ of the accumulator 40B is
The data is input to the data conversion circuit 50B and the control circuit 60B. The overflow signal output from the adder 41B of the accumulator 40B is input to the data conversion circuit 50B and the control circuit 60B, and is also input to the programmable delay generator 70 as the S-side enable signal 101. In the present embodiment, the overflow signal is delayed by a time represented by δt = ((2 ⁿ −θ) / S) · T (17).

The data conversion circuit 50B calculates the numerator data 2 ⁿ -θ of the equation (17),
The setting data K given to 0 is output. Control circuit 60B
Outputs a signal delayed by one clock after inverting the overflow signal as an S-side leak signal 103, and outputs a signal that rises one clock before the overflow signal rises and has a pulse width of one clock cycle as a K-side enable signal. Output as 201. The output signal of the programmable delay generator 70 is supplied to an output signal output terminal 3
02 and is fed back to the programmable delay generator 70 as a K-side leak signal 203.

With such a configuration, the programmable delay generator 70 generates the delay time shown in equation (17), and
The frequency synthesizer shown in (1) outputs a square wave with a small spurious component whose fundamental frequency is represented by the equation (15). When a toggle flip-flop (T-FF) is added to the output terminal, it is possible to obtain a rectangular wave synthesizer output with a duty ratio of 50%. The fundamental frequency in this case is (1
5) It becomes half of the formula.

(Third Embodiment of Frequency Synthesizer) FIG. 11 shows a third embodiment of the frequency synthesizer using the programmable delay generator of the present invention.

In the figure, the frequency synthesizer includes an accumulator 40C, a data conversion circuit 50C, a control circuit 6
OC, the programmable delay generator 70 of the present invention. The accumulator 40C includes an adder 41C and a latch 42C. The setting data S input from the setting data S input terminal 102 is set in the adder 41C and the programmable delay generator 70 of the accumulator 40C. The clock input from the clock input terminal 301 is supplied to the latch 42 of the accumulator 40C.
C and programmable delay generator 70.

The output data θ of the accumulator 40C is
The data is input to the data conversion circuit 50C and the control circuit 60C. The overflow signal output from the adder 41C of the accumulator 40C becomes an OFD signal delayed by one clock via the latch 42C, and becomes an OFD signal.
C and the control circuit 60C, and as the S-side enable signal 101, the programmable delay generator 7
Input to 0. In the present embodiment, the OFD signal is delayed by a time represented by δt = ((S−θ) / S) · T (18)

The data conversion circuit 50C calculates the numerator data S-θ in the equation (18) and outputs the setting data K to be given to the programmable delay generator 70. The control circuit 60C
After inverting the FD signal, the signal delayed by one clock is referred to as S
And outputs a signal having a pulse width of one clock cycle, which rises one clock before the rising timing of the OFD signal, and which has a pulse width of one clock cycle.
Output as 1. An output signal of the programmable delay generator 70 is taken out to an output signal output terminal 302 and fed back to the programmable delay generator 70 as a K-side leak signal 203.

With such a configuration, the programmable delay generator 70 generates the delay time shown in equation (18), and
The frequency synthesizer shown in (1) outputs a square wave with a small spurious component whose fundamental frequency is represented by the equation (15). When a toggle flip-flop (T-FF) is added to the output terminal, it is possible to obtain a rectangular wave synthesizer output with a duty ratio of 50%. The fundamental frequency in this case is (1
5) It becomes half of the formula.

(First Embodiment of Multiplier) FIG. 14 shows a first embodiment of the multiplier of the present invention.

In the figure, numeral 500 indicates a distribution circuit,
Current switches 501 to 503 and 505 to 507 are set or implemented by hardware so as to flow (or flow) a predetermined current, and current switches 509 to 511 and 513 to 515 are externally controlled to be on and off. Capacity, 5
17-519, 521-523 are switches, 525, 5
26, 528, 529 are comparators, 531, 53
2, 534, 535 are pulse width adjustment circuits, 537, 53
8, 540 and 541 are D-FFs, 543 is an OR gate,
544 is a one-shot multivibrator, 600 is a multiplied signal input terminal, and 601 is an output terminal.

This embodiment includes four delay generators. Assuming that the period of the multiplied signal is T, the first delay generator and the third delay generator generate a (１ ／) T delay time, and the second delay generator and the fourth delay generator Is (3 /
4) Generate a delay time of T.

The current switch 501, the capacitor 509, and the switch 517 generate a threshold voltage V1 of the first delay generator.
The current switch 503, the capacitor 511, and the switch 519 generate the ramp wave V3 of the first delay generator. V1 and V
The output of the comparator 525 for comparing the voltage of the third delay signal becomes the output of the first delay generator. The pulse width adjustment circuit 531 shortens the output pulse width of the first delay generator. This is to prevent the output pulse of the first delay generator from overlapping in time with the output pulse from the second to fourth delay generators.

The current switch 502, the capacitor 510, and the switch 518 generate the threshold voltage V2 of the second delay generator,
The current switch 503, the capacitor 511, and the switch 519 generate the ramp wave V3 of the second delay generator. This V3 serves as both the ramp wave of the first delay generator and the ramp wave of the second delay generator.

The current switch 505, the capacitor 513, and the switch 521 generate the threshold voltage V4 of the third delay generator,
The current switch 507, the capacitor 515, and the switch 523 generate the ramp wave V6 of the third delay generator.

The current switch 506, the capacitor 514, and the switch 522 generate a fourth delay generator threshold voltage V5,
The current switch 507, the capacitor 515, and the switch 523 generate the ramp wave V6 of the fourth delay generator. This V6 serves both as the ramp wave of the third delay generator and the ramp wave of the fourth delay generator.

FIG. 15 is a time chart showing an operation example of the first embodiment of the multiplier. (A) is the multiplied signal (CLK), and (b) is the output (CLK) of the distribution circuit 500.
1) and (c) show the distribution circuit 500 having a negative phase output (CLK2);
(D) is the threshold voltage V1 of the first delay generator, the threshold voltage V2 of the second delay generator, the ramp wave of the first delay generator (also the ramp wave of the second delay generator) V3, ( e) is the third
The threshold voltage V4 of the delay generator, the threshold voltage V5 of the fourth delay generator, the ramp wave of the third delay generator (and the ramp wave of the fourth delay generator) V6, (f) 5 is an output of the first embodiment.

The distribution circuit 500 is composed of only T-FFs, and inputs a pulse of the multiplied signal (CLK) and inverts its output ((b) CLK1, (c) CLK).
2). When CLK1 goes high, the current switch 50
1 and 502 are turned on, and the capacitance 50 is proportional to time.
Charges are charged to 9, 510. When the period T of the multiplied signal elapses, CLK1 goes low, and the current switches 501 and 502 return to the off state. Here, if the input impedance of the comparators 525 and 526 is sufficiently high, the charges charged in the capacitors 509 and 510 are held. Here, if the data is set such that the current sources of the current switches 501 and 502 are 1: 3 or realized by hardware, the voltages V1 and V2 of the capacitors 509 and 510
Is exactly 1: 3.

On the other hand, while CLK1 is in the high state, the switch 519 is in the on state, and the charge of the capacitor 511 is discharged. CLK1 returns to a low state while CLK2
Becomes high, the current switch 503 is turned on, and the capacitor 511 is charged in proportion to time. Here, data is set for the current source of the current switch 503 so as to be four times as large as that of the current switch 501, or the current source is realized by hardware. Then, after a lapse of (１ ／) T from the rise of CLK2, the voltage V3 of the capacitor 511 is increased.
Coincides with V1 and coincides with V2 after elapse of (3/4) T. The comparator 525 detects the timing of (1/4) T and outputs it (output of the first delay generator), and the comparator 526 detects the timing of (3/4) T and outputs it (second delay). Generator output). The outputs (co1, co2) of the pulse width adjusting circuits 531 and 532 are D-FFs.
The D-FFs are sent to set input terminals 537 and 538, and these D-FFs are turned on. This allows the switch 51
7, 518 are turned on to discharge the charges of the capacitors 509, 510 and prepare for the next charge.

The operations of the third and fourth delay generators are exactly the same as those of the above-described first and second delay generators except that they are shifted by T, respectively. Therefore, the pulse width adjustment circuit 532 outputs a pulse after a lapse of (1/2) T after the pulse width adjustment circuit 531 outputs a pulse, and further, the pulse width adjustment circuit 534 outputs a pulse after a lapse of (1/2) T. Output, and (1/2) T
After the elapse, the operation of outputting a pulse by the pulse width adjustment circuit 535 is repeated. As a result, a first embodiment of the multiplier is:
A rectangular wave signal having a period (1/2) T and having a pulse width determined by the one-shot multivibrator 544 is output.

In the first embodiment of the multiplier, a pulse is generated at an interval shorter than the cycle of the input signal by using the delay generator, so that an output signal without adjustment and low spurious can be generated. . The use of the programmable delay generator of the present invention as the delay generator has an effect that spurious characteristics do not deteriorate even if the circuit constant deviates from the set value or the power supply voltage fluctuates.

Although the delay time of the delay generator in this embodiment is (1/4) T and (3/4) T as an example, the delay time of the delay generator realizing the doubler has been described. There are countless combinations. For example, 0, (1/2) T
, (1/2) T, and (2/2) T, and each case can be easily realized with hardware. Considering both the spurious characteristics of the output and the circuit scale, the combination of (1/4) T and (3/4) T is the most excellent.

(Second Embodiment of Multiplier) FIG. 16 shows a second embodiment of the multiplier of the present invention.

In the figure, numeral 500a is a distribution circuit, and 501a to 508a are data switches which are set or implemented by hardware so as to flow in (or flow out) a predetermined current, and which are turned on and off by externally controlled current switches. , 509a to 516a are capacitors, 517a to 524a are switches, 525a to 530a are comparators, 531
a to 536a are pulse width adjustment circuits, 537a to 542a
Denotes a D-FF, 543a denotes an OR gate, 544a denotes a one-shot multivibrator, 600a denotes a multiplied signal input terminal, and 601a denotes an output terminal.

This embodiment includes six delay generators. Assuming that the period of the multiplied signal is T, the first delay generator and the fourth delay generator generate a delay time of (1/6) T, and the second delay generator and the fifth delay generator Is (3 /
6) generating a delay time of T, the third delay generator and the sixth delay generator;
Generates a delay time of (5/6) T.

The operation principle is the same as that of the first embodiment of the multiplier, but the number of delay generators and their delay times are different.
Current switch 501a, capacitor 509a, switch 517
a generates the threshold voltage V1 of the first delay generator, and the current switch 504a, the capacitor 512a, and the switch 520a generate the ramp wave V4 of the first delay generator. V1 and V
The output of the comparator 525a for comparing the voltage of
Output of the delay generator. Pulse width adjustment circuit 531a
Makes the output pulse width of the first delay generator shorter. This is to prevent the output pulse of the first delay generator from overlapping in time with the output pulse from the second to sixth delay generators.

FIG. 17 is a time chart showing an operation example of the second embodiment of the multiplier. (A) is the multiplied signal (CLK), and (b) is the output (CLK) of the distribution circuit 500a.
1) and (c) show the reverse phase output (CLK) of the distribution circuit 500a.
2) and (d) show the threshold voltage V1 of the first delay generator,
, The threshold voltage V3 of the third delay generator, the ramp voltage of the first delay generator (also the second and third ramp generators)
Ramp wave) V4, (e) are the threshold voltage V5 of the fourth delay generator, and the threshold voltage V5 of the fifth delay generator
6, the threshold voltage V7 of the sixth delay generator, the ramp wave of the fourth delay generator (also the ramp wave of the fifth and sixth delay generators)
V8, (f) is the output of the second embodiment of the multiplier.

When the output CLK1 of the distribution circuit 500a goes high, the current switches 501a, 502a, 503
a is turned on, and the capacitors 509a,
Electric charges are charged to 10a and 511a. When the period T of the multiplied signal elapses, CLK1 goes low, and the current switches 501a, 502a, and 503a return to the off state. Here, the comparators 525a, 526
a, if the input impedance of 527a is sufficiently high,
The charges charged in the capacitors 509a, 510a, and 511a are held. Here, the current switches 501a, 50
If data is set such that the current sources 2a and 503a are 1: 3: 5 or realized by hardware, the capacity 509a,
The voltages V1, V2, V3 of 510a, 511a are exactly 1: 3: 5.

On the other hand, while CLK1 is in the high state, the switch 520a is on, and the charge of the capacitor 512a is discharged. CLK1 returns to the low state, and at the same time
When K2 is set to the high state, the current switch 504a is turned on, and the capacitor 512a is charged with electric charge in proportion to time. Here, data is set for the current source of the current switch 504a to be six times that of the current switch 501a, or the current source is realized by hardware. Then, CLK
After a lapse of (1/6) T from the rise of the capacitor 2, the capacitance 51
The voltage V4 of 2a matches V1, matches V2 after (3/6) T elapses, and matches V3 after (5/6) T elapses.
The comparator 525a detects the timing of (1/6) T and outputs it (output of the first delay generator), and the comparator 526a detects the timing of (3/6) T and outputs it (second delay). Generator output) and the comparator 52
7a detects this (5/6) T timing and outputs it (the third delay generator output). Pulse width adjustment circuit 53
1a, 532a, 533a outputs (co1, co2, c
o3) is sent to the set input terminals of the D-FFs 537a, 538a, 539a to turn on these D-FFs. This allows the switches 517a, 518a, 519
a is turned on and the capacitors 509a, 510a, 511
The charge of a is discharged to prepare for the next charge.

The operations of the fourth to sixth delay generators are exactly the same as those of the above-described first to third delay generators except that they are shifted by T, respectively. Therefore, the pulse width adjusting circuits 531a to 536a output pulses in order at every (１ ／) T. As a result, the second embodiment of the multiplier outputs a square wave signal having a pulse width determined by the one-shot multivibrator 544a and having a period (1/3) T.

The second embodiment of the multiplier can generate an unadjusted low spurious output signal by using a delay generator to generate pulses at intervals shorter than the period of the input signal. . The use of the programmable delay generator of the present invention as the delay generator has an effect that spurious characteristics do not deteriorate even if the circuit constant deviates from the set value or the power supply voltage fluctuates.

Although the delay time of the delay generator in this embodiment is (1/6) T, (3/6) T, (5/6) T, an example has been described. There are innumerable combinations of the delay times of the delay generators. For example,
0, (1/3) T, combination of (2/3) T, (1/3)
3) Combinations of T, (2/3) T, and (3/3) T are conceivable, and each case can be easily realized with hardware. Considering both spurious characteristics of output and circuit scale, (1/6) T, (3/6) T, (5/6)
The combination of T is the best.

(Third Embodiment of Multiplier) FIG. 18 shows a third embodiment of the multiplier of the present invention.

In the figure, numeral 500b is a distribution circuit, and 501b to 503b, 505b, and 507b are data set or realized by hardware so that a predetermined current flows (or flows out), and ON / OFF is externally controlled. Current switches 509b-511b, 513
b, 515b are capacities, 517b to 519b, 521b,
523b is a switch, 525b to 526b, 528b is a comparator, 513b to 532b, 534b is a pulse width adjustment circuit, 537b to 538b, and 540b is a DF.
F, 543b is an OR gate, 544b is a one-shot
A multivibrator, 600b is a multiplied signal input terminal,
601b represents an output terminal.

This embodiment includes three delay generators. Assuming that the period of the multiplied signal is T, the first delay generator generates a delay time of (1/6) T, the second delay generator generates a delay time of (5/6) T, A third delay generator generates a delay time of (9/6) T.

The operation principle is the same as that of the first and second embodiments of the multiplier, but the number of delay generators and their delay times are different. The current switch 501b, the capacitor 509b, and the switch 517b generate a first delay generator threshold voltage V1,
Current switch 503b, capacitance 511b, switch 519
b generates the ramp wave V3 of the first delay generator. V1
And the output of the comparator 525b comparing the voltages V3 and V3 is the output of the first delay generator. Pulse width adjustment circuit 5
31b shapes the output pulse width of the first delay generator to be short. This means that the output pulse of the first delay generator is the second,
This is to prevent the output pulse from the third delay generator from overlapping in time.

FIG. 19 is a time chart showing an operation example of the third embodiment of the multiplier. (A) is the multiplied signal (CLK), and (b) is the output (CLK) of the distribution circuit 500b.
1) and (c) show the negative phase output (CLK
2) and (d) show the threshold voltage V1 of the first delay generator,
The threshold voltage V2 of the delay generator, the ramp wave of the first delay generator (and the ramp wave of the second delay generator) V3, (e) are the threshold voltage V4 of the third delay generator, The ramp wave V5, (f) of the delay generator is the output of the third embodiment of the multiplier.

When the output CLK1 of the distribution circuit 500b goes high, the current switches 501b and 502b are turned on, and the capacitors 509b and 510b are charged in proportion to time. When the period T of the multiplied signal elapses, CLK1 goes low, and the current switch 501
b and 502b return to the off state. Here, if the input impedance of the comparators 525b and 526b is sufficiently high, the charges charged in the capacitors 509b and 510b are held. Here, the current switches 501b and 502b
When the data is set such that the current source becomes 1: 5 or realized by hardware, the voltage V of the capacitors 509b and 510b
1, V2 is exactly 1: 5.

On the other hand, while CLK1 is in the high state, the switch 519b is on, and the electric charge of the capacitor 511b is discharged. CLK1 returns to the low state, and at the same time
When K2 is set to the high state, the current switch 503b is turned on, and charges are charged to the capacitor 511b in proportion to time. Here, data is set for the current source of the current switch 503b so as to be six times that of the current switch 501b, or the current source is realized by hardware. Then, CLK
After a lapse of (1/6) T from the rise of the capacitor 2, the capacitance 51
The voltage V3 of 1b coincides with V1 and coincides with V2 after a lapse of (5/6) T. The comparator 525b calculates the (1 /
6) The timing of T is detected and output (output of the first delay generator), and the comparator 526b detects the timing of (5/6) T and outputs it (output of the second delay generator). The outputs of the pulse width adjustment circuits 531b and 532b (co
1, co2) are sent to the set input terminals of the D-FFs 537b and 538b, and these D-FFs are turned on. This turns on the switches 517b and 518b, and discharges the charges of the capacitors 509b and 510b to prepare for the next charge.

The third delay generator operates similarly to CLK1.
A pulse is output after a lapse of (3/6) T from the rise of. This timing corresponds to (9/6) T after the rise of CLK2. Therefore, the pulse width adjusting circuits 531b to 532b and 534b output pulses in order every (4/6) T. As a result, the third embodiment of the multiplier has a period (4/4) with a pulse width determined by the one-shot multivibrator 544b.
6) A rectangular wave signal of T is output.

The third embodiment of the multiplier can generate a non-adjusted low spurious output signal by using a delay generator to generate pulses at intervals shorter than the period of the input signal. . The use of the programmable delay generator of the present invention as the delay generator has an effect that spurious characteristics do not deteriorate even if the circuit constant deviates from the set value or the power supply voltage fluctuates.

Although the delay time of the delay generator in this embodiment is (1/6) T, (5/6) T, (9/6) T, an example has been described. There are innumerable combinations of delay times of the delay generator that realize the above. For example, a combination of 0, (4/6) T, (8/6) T,
Combinations of (2/6) T, (6/6) T, and (10/6) T are conceivable, and each case can be easily realized with hardware. Considering both spurious characteristics of output and circuit scale, (1/6) T, (5/6) T,
The combination of (9/6) T is the most excellent.

(First Embodiment of Duty Ratio Converter) FIG. 20 shows a first embodiment of the duty ratio converter of the present invention.

In the figure, numeral 550 is a multiplier (doubler) of the present invention, 551 is a T-FF, 602 is a pulse signal input terminal, and 603 is an output terminal.

FIG. 21 is a time chart showing an operation example of the first embodiment of the duty ratio conversion circuit. (A)
Is a pulse signal, (b) is the output of the multiplier 550, and (c) is T
FF551 output is shown. Assuming that the period of the input pulse signal (a) is T, the output (b) of the multiplier 550
Is a rectangular wave having a period (1/2) T. T-FF551
Switches the output between high and low every time a pulse from the multiplier 550 is input. Therefore, the output of the T-FF 551 is a rectangular wave having a duty ratio of 50% and a period T.

The first embodiment of the duty ratio conversion circuit uses the multiplier of the present invention to accurately generate the timing of a half cycle of the input pulse signal.
Irrespective of the duty ratio of the input pulse signal, it can be converted into a rectangular wave signal having a duty ratio of 50% without adjustment. The use of the multiplier of the present invention has the effect of preventing the output duty ratio from deviating from 50% even if the circuit constant deviates from the set value or the power supply voltage fluctuates. The use of the multiplier of the present invention has an effect that a 50% duty ratio can be obtained without adjustment even if the frequency of the input pulse signal is changed.

(Second Embodiment of Duty Ratio Converter) FIG. 22 shows a second embodiment of the duty ratio converter of the present invention.

In the figure, numeral 560 is a distribution circuit,
561, 562, 564, and 565 are current switch arrays for flowing (or flowing) current proportional to input data, 567, 568, 570, and 571 are capacitors;
3, 574, 576, 577 are switches, 579, 58
0, 582, 583 are switches for switching multi-bit digital data, 585, 587 are comparators, 58
9 to 592 are pulse width conversion circuits, 593 and 595 are D-
FF, 597, 598 are SR-FF, 599 is an OR gate, 604 is a pulse signal input terminal, 605 is an output terminal,
606 is a setting data K input terminal, and 607 is a setting data S
Indicates an input terminal.

This embodiment includes two delay generators. Assuming that the period of the input pulse signal is T, the first
And the second delay generator generate a delay time of (K / S) T.

A current switch array 561, a capacitance 567,
The switch 573 generates the threshold voltage V1 of the first delay generator, and the current switch array 562, the capacitor 568, and the switch 574 generate the ramp wave V2 of the first delay generator.

The current switch array 564, the capacitance 570,
The switch 576 generates the threshold voltage V3 of the second delay generator, and the current switch array 565, the capacitor 571, and the switch 577 generate the ramp wave V4 of the second delay generator.

FIG. 23 is a time chart showing an operation example of the second embodiment of the duty ratio conversion circuit. (A)
Is a pulse signal (CLK), (b) is a distribution circuit 560 output (CLK1), and (c) is a distribution circuit 560 reverse-phase output (CL
K2), (d) are threshold voltage V1 of the first delay generator, ramp wave V2 of the first delay generator, (e) is threshold voltage V3 of the second delay generator, second delay generator Ramp wave V
4, (f) is the output of the second embodiment of the duty ratio conversion circuit.

The distribution circuit 560 is a T-FF, and inverts the output of the pulse signal (CLK) as well as the input of the pulse signal (CLK) ((b) CLK1, (c) CLK2). CLK1
Becomes high, the current switch array 561 is turned on, and the capacitance 56 is proportional to the setting data K and time.
7 is charged. After the period T of the input pulse signal has elapsed, CLK1 returns to the low state, the current switch array 561 is turned off, and the voltage V1 of the capacitor 567 is held. The held voltage V1 is represented by the following equation. V1 = − (KI ₀ / C) · T (19) where I ₀ is a unit current of the current switch array 561. CLK1 is held at the same timing as V1 is held.
2 goes high, the current switch array 562 goes on, and the capacitance 56 is proportional to the setting data S and time.
8 is charged. When the time at which the CLK2 rises to a high state and _{t 0,} voltage of the capacitor 568 V
2 is represented by the following equation. V2 = − (SI ₀ / C) · (t−t ₀ ) (20) Accordingly, the time td from time t ₀ until V1 and V2 match (that is, the delay time of the first delay generator) td is: It is expressed by the following equation. td = (K / S) · T (21)

The SR-FF 597 has the rising edge of CLK2.
Timing (ie, time t₀ ) And V
It is reset at the timing when 1 and V2 match. Follow
Therefore, the output pulse width of SR-FF 597 matches the equation (21)
I do. On the other hand, the second delay generator is different from the first delay generator in time.
The first delay generator and the second
Each of the delay generators operates in a 2T cycle. Therefore O
The output of the R gate 599 has a period T, a pulse width (K / S)
It becomes a T rectangular wave. That is, the duty ratio conversion circuit
The second embodiment generates a square wave having a duty ratio (K / S).
Live.

The duty ratio conversion circuit according to the present invention can convert the duty ratio into a high-precision one with no adjustment by using the programmable delay generator according to the present invention as a means for determining the pulse width of the output signal. The use of the programmable delay generator of the present invention as the delay generator does not cause a deviation from the set value of the output duty ratio even if there is a deviation from the set value of the circuit constant or a fluctuation of the power supply voltage. There is. Using the programmable delay generator of the present invention as the delay generator has the effect that a desired duty ratio can be obtained without adjustment even if the frequency of the input pulse signal is changed.

(Third Embodiment of Duty Ratio Converter) FIG. 24 shows a third embodiment of the duty ratio converter of the present invention.

In the figure, numeral 560a is a distribution circuit, and 561a to 566a are current switch arrays for flowing (or flowing) current proportional to input data.
67a to 572a are capacitors, 573a to 578a are switches, 579a to 584a are switches for switching multi-bit digital data, 585a to 588a are comparators, 589a to 592a are pulse width conversion circuits, and 593a
-596a is D-FF, 597a, 598a is SR-F
F, 599a indicate an OR gate, 604a indicates a pulse signal input terminal, 605a indicates an output terminal, 608 indicates a setting data K1 input terminal, 609 indicates a setting data K2 input terminal, and 610 indicates a setting data S input terminal.

This embodiment includes four delay generators. Assuming that the period of the input pulse signal is T, the first
The third and third delay generators generate a delay time of (K1 / S) T, and the second and fourth delay generators generate a delay time of (K2 / S) T. I do.

Current switch array 561a, capacitance 567
a, the switch 573a generates the threshold voltage V1 of the first delay generator, and outputs the current switch array 562a, the capacitance 56
8a, the switch 574a generates the threshold voltage V2 of the second delay generator, and outputs the current switch array 563a, the capacitance 5
69a, the switch 575a generates a common ramp wave voltage V3 of the first and second delay generators.

Current switch array 564a, capacitance 570
a, the switch 576a generates the threshold voltage V4 of the third delay generator, and outputs the current switch array 565a and the capacitor 57.
1a, the switch 577a generates the threshold voltage V5 of the fourth delay generator, and outputs the current switch array 566a, the capacitance 5
72a and a switch 578a generate a common ramp voltage V6 for the third and fourth delay generators.

FIG. 25 is a time chart showing an operation example of the third embodiment of the duty ratio conversion circuit. (A)
Is a pulse signal (CLK), (b) is an output (CLK1) of the distribution circuit 560a, (c) is an inverted-phase output (CLK2) of the distribution circuit 560a, and (d) is a threshold voltage V of the first delay generator.
1, the threshold voltage V2 of the second delay generator, the ramp wave V3 of the first and second delay generators, (e) is the threshold voltage V4 of the third delay generator, the ramp of the fourth delay generator The wave V5 and the ramp wave V6 (f) of the third and fourth delay generators are the outputs of the third embodiment of the duty ratio conversion circuit.

In the second embodiment of the duty ratio conversion circuit, only the falling timing of the output pulse is determined by the delay generator, and the rising timing of the output pulse coincides with the input pulse signal. In the third embodiment, the timing at which the output pulse rises and the timing at which the output pulse falls are determined by different delay generators. The timing at which the output pulse rises is determined by the first and third delay generators, and the timing at which the output pulse falls is determined by the second and fourth delay generators. The delay times td1 of the first and third delay generators are set data K1, S
Is expressed by the following equation. td1 = (K1 / S) · T (22) On the other hand, the delay time td2 of the second and fourth delay generators is expressed by the following equation using the setting data K2 and S. td2 = (K2 / S) · T (23)

The SR-FF 597a is set by the output pulse of the first delay generator and reset by the output pulse of the second delay generator. Therefore, the output pulse width of the SR-FF 597a is represented by ((K2−K1) / S) · T.
On the other hand, the third and fourth delay generators operate with a time delay of T from the first and second delay generators, and all the delay generators operate with a 2T cycle. Therefore, the output of the OR gate 599a is a rectangular wave having a period T and a pulse width ((K2−K1) / S) · T. That is, the third embodiment of the duty ratio conversion circuit generates a rectangular wave having a duty ratio ((K2−K1) / S).

The duty ratio conversion circuit according to the present invention can convert the duty ratio into a high-precision one with no adjustment by using the programmable delay generator according to the present invention as a means for determining the pulse width of the output signal. The use of the programmable delay generator of the present invention as the delay generator does not cause a deviation from the set value of the output duty ratio even if there is a deviation from the set value of the circuit constant or a fluctuation of the power supply voltage. There is. Using the programmable delay generator of the present invention as the delay generator has the effect that a desired duty ratio can be obtained without adjustment even if the frequency of the input pulse signal is changed. The present embodiment has the advantage that the phase of the output signal can be freely set because the rising and falling timings of the output pulse can be freely selected independently of the timing of the input pulse signal.

(PLL Frequency Synthesizer) FIG.
1 shows an embodiment of a PLL frequency synthesizer of the present invention.

In the figure, numeral 611 is a reference signal input terminal, 612 is an output terminal, 700 is a phase comparator, 70
1 is a loop filter, 702 is a voltage controlled oscillator (VC
O) and 703 are frequency dividers having a predetermined frequency division number, and 704 is a frequency multiplier of the present invention having a frequency multiplier N / M.

The PLL frequency synthesizer of the present embodiment is characterized in that the multiplier of the present invention is inserted between the frequency divider and the phase comparator in the basic PLL frequency synthesizer configuration. Thus, attempts to insert a mixer or a pulse train generator between a frequency divider and a phase comparator for the purpose of frequency conversion have been reported. Attempt to insert a pulse train generator (Reference: T. Nakagawa and T. Ohira, “A pha
se noise reduction technique for MMIC frequency sy
nthesizers that uses a new pulse generator LSI, ”I
EEE Trans. Microwave Theory Tech., Vol. 42, no. 1
2, pp. 2579-2582, Dec. 1994.), a pulse train generator is inserted between the frequency divider and the phase comparator to increase only the reference frequency while keeping the frequency step fine. , Has successfully reduced the phase noise. However, attempts to insert a pulse train generator will produce spurs if the integer multiple of the time interval between the inserted pulses does not match the frequency of the divider. For this reason, it was necessary to adjust the time interval of the insertion pulse train.

On the other hand, since the frequency multiplier of the present invention outputs pulses at equal intervals without any adjustment, the PLL frequency synthesizer of this embodiment using the same outputs the reference frequency without generating spurs in the output. Can be increased N / M times, and the phase noise can be reduced. Further, in the present embodiment, even if the band of the loop filter 701 is widened, the phase noise characteristic that can be achieved by the configuration of the basic PLL frequency synthesizer can be maintained, so that high-speed frequency switching is possible.

[0133]

As described above, the programmable delay generator of the present invention can generate the ramp wave voltage and the threshold voltage for determining the delay time by a circuit having the same configuration. No value adjustment is required. Also, since the ramp voltage and the threshold voltage can be set independently of each other, a fractional delay time can be generated in which both the numerator and denominator can be set. Further, since the operations of the ramp generation circuit and the threshold voltage generation circuit are synchronized with the external clock, the absolute accuracy of the delay time can be improved.

The frequency synthesizer of the present invention can generate an unadjusted and low spurious output signal by performing phase interpolation of the output pulse of the accumulator using the programmable delay generator of the present invention. Also,
The frequency synthesizer of the present invention is capable of lower power consumption and higher frequency operation than a normal direct digital synthesizer using a ROM.

The multiplier of the present invention can generate an unadjusted and low spurious output signal by generating pulses at intervals shorter than the cycle of the input signal using the programmable delay generator of the present invention. it can. The use of the programmable delay generator of the present invention as the delay generator has an effect that spurious characteristics do not deteriorate even if the circuit constant deviates from the set value or the power supply voltage fluctuates. The multiplier of the present invention does not require a filter as compared with a conventional multiplier using a non-linear combination of elements or a conventional multiplier using a mixer, and can be connected in multiple stages without a filter. This is effective in expanding the frequency range of the multiplied signal and reducing the circuit scale. Further, the multiplier of the present invention is characterized in that the circuit scale is smaller and the power consumption is lower than that of a conventional multiplier using a PLL frequency synthesizer.

By using the programmable delay generator of the present invention as a means for determining the pulse width of the output signal, the duty ratio conversion circuit of the present invention can convert the duty ratio to a high-precision duty ratio without adjustment. The use of the programmable delay generator of the present invention as the delay generator does not cause a deviation from the set value of the output duty ratio even if there is a deviation from the set value of the circuit constant or a fluctuation of the power supply voltage. There is. Using the programmable delay generator of the present invention as the delay generator has the effect that a desired duty ratio can be obtained without adjustment even if the frequency of the input pulse signal is changed.

The PLL frequency synthesizer of the present invention has a multiplier of the present invention inserted between the frequency divider and the phase comparator of the conventional PLL frequency synthesizer to realize the same step frequency as that of the conventional PLL frequency synthesizer. A high frequency reference signal proportional to the multiplication ratio can be used. The fact that the frequency of the reference signal can be increased has the effect that high-speed settling and high-speed frequency switching can be performed while maintaining the same phase noise characteristics as in the related art. Further, there is an effect that the phase noise can be reduced while realizing the same frequency switching time as the related art. With the PLL frequency synthesizer of the present invention, the advantage of the low spurious property of the multiplier can be used as it is, and it is possible to obtain a low jitter, low spurious output signal without adjustment.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a programmable delay generator according to the present invention.

FIG. 2 is a time chart showing an operation example of the first embodiment of the programmable delay generator.

FIG. 3 is a block diagram showing a second embodiment of the programmable delay generator of the present invention.

FIG. 4 is a time chart showing an operation example of the second embodiment of the programmable delay generator.

FIG. 5 is a block diagram showing a first embodiment of the frequency synthesizer of the present invention.

FIG. 6 is a view for explaining the operation principle of the accumulator 40A.

FIG. 7 is a time chart showing an operation example of the first embodiment of the frequency synthesizer.

FIG. 8 is a diagram showing experimental results of the first embodiment of the frequency synthesizer.

FIG. 9 is a diagram showing an output signal spectrum in an experimental result.

FIG. 10 is a block diagram showing a second embodiment of the frequency synthesizer of the present invention.

FIG. 11 is a block diagram showing a third embodiment of the frequency synthesizer of the present invention.

FIG. 12 is a block diagram showing a configuration example of a conventional programmable delay generator.

FIG. 13 is a time chart showing an operation example of a conventional programmable delay generator.

FIG. 14 is a block diagram showing a first embodiment of the frequency multiplier of the present invention.

FIG. 15 is a time chart showing an operation example of the first embodiment of the frequency multiplier;

FIG. 16 is a block diagram showing a second embodiment of the frequency multiplier of the present invention.

FIG. 17 is a time chart showing an operation example of the second embodiment of the frequency multiplier;

FIG. 18 is a block diagram showing a third embodiment of the frequency multiplier of the present invention.

FIG. 19 is a time chart showing an operation example of the third embodiment of the multiplier.

FIG. 20 is a block diagram showing a first embodiment of a duty ratio conversion circuit according to the present invention.

FIG. 21 is a time chart showing an operation example of the first embodiment of the duty ratio conversion circuit.

FIG. 22 is a block diagram showing a second embodiment of the duty ratio conversion circuit of the present invention.

FIG. 23 is a time chart showing an operation example of the second embodiment of the duty ratio conversion circuit.

FIG. 24 is a block diagram showing a third embodiment of the duty ratio conversion circuit of the present invention.

FIG. 25 is a time chart illustrating an operation example of the third embodiment of the duty ratio conversion circuit.

FIG. 26 is a block diagram showing an embodiment of a PLL frequency synthesizer of the present invention.

[Explanation of symbols]

10A, 10B Ramp generation circuit 20A, 20B Threshold voltage generation circuit 11, 21 Data selector 12, 22, Latch 13, 23 Current switch array 14, 24 Switch 15, 25 Capacity 16, 26 Current switch 17, 27 Voltage divider 31 Comparator 32 One-shot 40A, 40B, 40C Accumulator 41A, 41B, 41C Adder 42A, 42B, 42C Latch 50A, 50B, 50C Data conversion circuit 60A, 60B, 60C Control circuit 70 Programmable delay generator 81 Trigger circuit 82 Current source 83 Capacity 84 Switch 85 Latch 86 D / A converter 87 Comparator 88 One shot 101 S-side enable signal input terminal 102 Setting data S input terminal 103 S-side leak signal input terminal 201 K-side enable signal Input terminal 202 setting data K input terminal 203 K-side leak signal input terminal 301 clock input terminal 302 output signal output terminal 401 leak signal input terminal 402 trigger signal input terminal 403 latch signal input terminal 404 setting data input terminal 405 output signal output terminal 500 , 500a, 500b Distribution circuit 501, 501a, 501b Current switch 502, 502a, 502b Current switch 503, 503a, 503b Current switch 504a Current switch 505, 505a, 505b Current switch 506, 506a Current switch 507, 507a, 507a Current switch 508 Current switch 509, 509a, 509b capacity 510, 510a, 510b capacity 511, 511a, 511b capacity 512a capacity 513, 513a, 13b capacity 514, 514a capacity 515, 515a, 515b capacity 516a capacity 517, 517a, 517b switch 518, 518a, 518b switch 519, 519a, 519b switch 520a switch 521, 521a, 521b switch 522, 522a switch 523, 523a, 523b switch 524a switch 525, 525a, 525b comparator 526, 526a, 526b comparator 527a comparator 528, 528a, 528b comparator 529, 529a comparator 530a comparator 531, 531a, 531b pulse width adjustment circuit 532, 532a, 532b pulse width adjustment circuit 533a pulse width adjustment Circuit 534, 534a, 534b Pulse width adjustment circuit 535 535a Pulse width adjustment circuit 536a Pulse width adjustment circuit 537, 537a, 537b D-FF 538, 538a, 538b D-FF 539a D-FF 540, 540a, 540b D-FF 541, 541a D-FF 542a D-FF 543, 543a, 543b OR gate 544, 544a, 544b One-shot multivibrator 550 Multiplier 551 T-FF 560, 560a Distribution circuit 561, 561a Current switch array 562, 562a Current switch array 563a Current switch array 564, 564a Current switch array 565 Current switch array 566a current switch array 567, 567a capacity 568, 568a capacity 569a capacity 570, 570a capacity 571, 571a capacity 5 2a Capacity 573, 573a Switch 574, 574a Switch 575a Switch 576, 576a Switch 577, 577a Switch 578a Switch 579, 579a Switch 580, 580a Switch 581a Switch 582, 582a Switch 583, 583a Switch 584a Switch 585, 585a Comparator 586a Comparator 586a 587a Comparator 588a Comparator 589, 589a Pulse width adjustment circuit 590, 590a Pulse width adjustment circuit 591, 591a Pulse width adjustment circuit 592, 592a Pulse width adjustment circuit 593, 593a D-FF 594a D-FF 595, 595a D-FF 596a D -FF 597, 597a SR-FF 598, 598a SR-FF 599, 5 99a OR gate 600, 600a, 600b Multiplied signal input terminal 601, 601a, 601b Output terminal 602 Pulse signal input terminal 603 Output terminal 604, 604a Pulse signal input terminal 605, 605a Output terminal 606 Setting data K input terminal 607 Setting data S Input terminal 608 Setting data K1 input terminal 609 Setting data K2 input terminal 610 Setting data S input terminal 611 Reference signal input terminal 612 Output terminal 700 Phase comparator 701 Loop filter 702 VCO 703 Divider 704 Multiplier

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Akihiro Yamagishi 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 5/13 H03K 5/04 H03K 5/00

Claims (22)

(57) [Claims] 1. A first and a second circuit which operate with a common external clock with the same circuit configuration for providing a final attained potential corresponding to setting data input from the outside and a potential gradient until the potential is reached. A ramp wave generating circuit, and a comparator circuit that compares the output (Vs) of the first ramp wave generating circuit with the output (Vk) of the second ramp wave generating circuit and generates an output pulse when they match. The first setting data (S) is set at a predetermined time (t ₀ ) in the first ramp wave generation circuit, and the first setting data (S) is set at the time (t ₀ ) as a starting point. A first ramp wave voltage (Vs) having a proportional slope is generated, and a second ramp wave generation circuit precedes the predetermined time (t ₀ ) by at least one clock time (T) to generate second set data. (K) is set and compared with the second setting data (K). The comparison circuit generates and holds a threshold voltage (Vk) as an example, and the comparison circuit starts from the time (t ₀ ) and changes the first ramp wave voltage (Vs) that changes with a slope proportional to the first setting data (S). ) Is equal to the threshold voltage (Vk), an output pulse is generated, so that the delay time (td) from the predetermined time (t ₀ ) is reduced by the ratio (K) of the first and second set data. / S) generating a delayed output pulse proportional to / S). 2. A current source for providing a current proportional to setting data in each of the first and second ramp voltage generating circuits, and a capacitor having one end charged by the current source connected to a predetermined potential. And providing a potential gradient to the other end of the capacitor. 3. An S-side enable signal, setting data S, and a clock are input, and the setting data S is synchronized with the first specific clock after the S-side enable signal is input to a first capacitor having a capacitance value C. flowing a current SI ₀ to proportional, lamp outputs the clock after the input time when the t a (SI 0 / _C) · voltage across the first capacitor, represented by t as ramp voltage Vs A wave generation circuit, a K-side enable signal input at least m clocks before the S-side enable signal is input (m is a natural number), setting data K, and a clock;
Time m set by the K-side enable signal
T (T is the clock period) passing a current KI ₀ proportional to only the setting data K, then the second volume of the voltage across (KI 0 / _C) · mT threshold is output as the threshold voltage Vk holds A voltage generation circuit compares the level of the ramp wave voltage Vs with the level of the threshold voltage Vk, and a timing at which the two coincide with each other is set as a delay time td = (K / S) · mT for the specific clock. A delay time generating means for outputting an output signal having a pulse width, wherein the first capacitance and the second capacitance are respectively input at predetermined timings after an output signal is output from the delay time generating means A programmable delay generator having a configuration leaked by an S-side leak signal and a K-side leak signal. 4. The programmable delay generator according to claim 3, wherein the ramp generation circuit is configured to latch the setting data S by using a clock as a trigger in response to the input of the S-side enable signal, and to respond to the setting data S. and a current switch array for controlling the current SI ₀ flowing through the first capacitor, the threshold voltage generating circuit includes a latch for holding the configuration data K clock as a trigger by the input of the K-side enable signal, to the setting data K Correspondingly programmable delay generator, wherein a slip-free that the current switch array for controlling the current KI ₀ only flow time mT to the second capacitor. 5. An S-side enable signal, setting data S, and a clock are input to a first capacitor having a capacitance value C and a first clock after the input of the S-side enable signal (hereinafter referred to as a “specific clock”). When the current I ₀ flows in synchronism and the time after the clock input is t, the voltage across the first capacitor represented by (I ₀ / C) · t is further proportional to the setting data S. A ramp generation circuit for outputting a voltage (S / MM)） (I ₀ / C) ・ t divided by a value S / MM (MM is an integer of S and K or more) as a ramp voltage Vs; The K-side enable signal, the setting data K, and the clock are input at least m clocks before the enable signal is input (m is a natural number), and the second capacitance having the capacitance value C is
Time mT set by K-side enable signal (T is the clock period) current only I _0, then the second
Capacity of the voltage across _(I 0 / C) · mT holds, further setting voltage divided by the value K / MM proportional to the data _{K (K / MM) · (} I 0 / C) · mT threshold A threshold voltage generating circuit that outputs a voltage Vk is compared with the level of the ramp wave voltage Vs and the level of the threshold voltage Vk, and the timing at which the two coincide with each other is a delay time td = (K / S). delay time generating means for outputting an output signal having a predetermined pulse width set as mT, wherein the first capacitance and the second capacitance are respectively provided after an output signal is output from the delay time generating means A programmable delay generator, which is configured to leak by an S-side leak signal and a K-side leak signal inputted at a predetermined timing. 6. The programmable delay generator according to claim 5, wherein the ramp generation circuit includes two latches for holding setting data S and an S-side enable signal input from outside using a clock as a trigger, and A current switch for flowing a current to the first capacitor according to the side enable signal; and a voltage divider for dividing a voltage across the first capacitor by a divided value S / MM according to the setting data S, The generation circuit includes two latches that hold setting data K and a K-side enable signal that are input from outside using a clock as a trigger, a current switch that causes a current to flow to a second capacitor according to the K-side enable signal, A voltage divider that divides a voltage across the second capacitor by a divided value K / MM corresponding to K. 7. Inputting a clock and setting data S,
An n-bit accumulator that accumulates the setting data S in synchronization with the clock and output data θ of the accumulator are input, and the output data θ one clock cycle before the _{MSB of} the most significant bit rises is defined as θp (2 ^{n -1} −θp), a data conversion circuit for outputting this value as setting data K, and inputting the output data θ of the accumulator, one clock cycle before the most significant bit θ _MSB rises. A control circuit that generates a K-side enable signal having a rising edge and a pulse width of one clock cycle; the setting data S; setting data K output from the data conversion circuit; and a K-side enable output from the control circuit. claim for inputting a signal, the most significant bit theta _MSB of the output data theta of the accumulator as S-side enable signal 3 Frequency synthesizer, characterized in that a programmable delay generator as claimed in 6. 8. The frequency synthesizer according to claim 7, wherein the S-side leak signal and the K-side leak signal applied to the programmable delay generator according to claim 3 are obtained by feeding back an output signal of the programmable delay generator. A frequency synthesizer characterized in that the frequency synthesizer is provided. 9. Inputting a clock and setting data S,
N-bit data for accumulating the setting data S in synchronization with the clock
Accumulator, output data θ of the accumulator and overflow
-Input the signal (2 ⁿ-Θ)
Data conversion circuit that outputs this value as setting data K.
Path, output data θ of the accumulator and overflow
Input signal and the overflow signal rises
The pulse rises one clock cycle earlier and has a pulse width of one clock cycle.
A control circuit for generating a K-side enable signal having a clock cycle; the setting data S;
And the K-side input output from the control circuit.
Enable signal and the output from the accumulator.
Overflow signal is input as S-side enable signal
And a programmable delay generator according to claims 3 to 6.
A frequency synthesizer characterized by: 10. The frequency synthesizer according to claim 9, wherein the S-side leak signal and the K-side leak signal applied to the programmable delay generator according to claim 3 are obtained by feeding back an output signal of the programmable delay generator. A frequency synthesizer characterized in that the frequency synthesizer is provided. 11. An n-bit accumulator for receiving a clock and setting data S and accumulating the setting data S in synchronization with the clock, and an OFD signal obtained by delaying output data θ of the accumulator and an overflow signal by one clock. A data conversion circuit which inputs and calculates a value corresponding to (S-θ) and outputs this value as setting data K; and one clock which inputs the output data θ of the accumulator and the OFD signal and raises the OFD signal. A control circuit that generates a K-side enable signal that rises before the cycle and has a pulse width of 1 clock cycle; setting data S; setting data K output from the data conversion circuit; and output from the control circuit A K-side enable signal and an O output from the accumulator
4. The FD signal is input as an S-side enable signal.
A frequency synthesizer comprising: the programmable delay generator according to any one of (1) to (6). 12. The frequency synthesizer according to claim 11, wherein the S-side leak signal and the K-side leak signal provided to the programmable delay generator according to claim 1 are obtained by feeding back an output signal of the programmable delay generator. A frequency synthesizer characterized in that the frequency synthesizer is provided. 13. When a multiplied signal having a period T is input, d is an arbitrary time, N is an integer of 2 or more, and M is an integer of 1 or more, N kinds of specific delay times d + (k · M /
N) the data is set to generate T (k is any integer from 0 to N-1), or it is hard-designed to fixedly generate the above specific delay time;
7. The delay generator (plural) according to claim 3, a distribution circuit that inputs the multiplied signal and sends a delay generation timing to each of the delay generators (plural), and the delay generator. And an OR gate for calculating the logical sum of the outputs of the plurality of devices (multiple devices), and outputs a signal having a frequency N / M times that of the multiplied signal. 14. The multiplier according to claim 13, wherein the delay time of the delay generator is (１ ／) T, (3 /
4) Two types of T (d = (1/4) T, N = 2, M
= 1) 2 of the frequency of the multiplied signal.
Multiplier that outputs double frequency. 15. The multiplier according to claim 13, wherein a delay time of the delay generator is (1/6) T, (3 /
6) T and (5/6) T (d = (1/6)
T, N = 3, M = 1), wherein the multiplier outputs a frequency three times the frequency of the multiplied signal. 16. The multiplier according to claim 13, wherein the delay time of the delay generator is (1/6) T, (5 /
6) T and (9/6) T (d = (1/6)
T, N = 3, M = 2) a multiplier that outputs a frequency that is 3/2 times the frequency of the multiplied signal. 17. A pulse signal having a period T is inputted, the multiplier according to claim 13 or 14 is inputted, and the output is switched between high and low every time the pulse is inputted. And a toggle flip-flop (T-FF). 18. A distribution circuit for inputting a pulse signal having a period T, inputting the pulse signal, and distributing the rising or falling timing into a plurality of timings, and synchronizing the output pulse with the output of the distribution circuit. A flip-flop that switches between high and low, a delay generator according to claim 3, wherein an output of the distribution circuit is input as a clock, an output is sent to the flip-flop, and the output is switched between low and high. A duty ratio conversion circuit composed of: 19. A distribution circuit that receives a pulse signal having a period T, receives the pulse signal, and distributes the rising or falling timing into a plurality of timings, and inputs the output of the distribution circuit as a clock.
And a flip-flop that receives an output of the delay generator, switches its output to high or low, receives an output of the other delay generator, and switches its output to low or high. And a duty ratio conversion circuit. 20. The multiplier according to claim 13, wherein a plurality of ramp wave generating circuits each of which is included in said delay generator (a plurality of times) is provided by a smaller number of ramp wave generating circuits. A multiplier and a duty ratio conversion circuit, which are commonly used. 21. The duty ratio conversion circuit according to claim 17, wherein the ramp generation circuit is commonly used for a plurality of delay generators. 22. A voltage controlled oscillator (VCO), a frequency divider for dividing the frequency of the output of the VCO to a predetermined number, a frequency or a phase of an output of the frequency divider and a reference signal inputted from outside. And a loop filter integrating the output of the comparator and sending the output to the VCO. A PLL frequency synthesizer comprising: 17. A PLL frequency synthesizer comprising the multiplier according to claim 13 inserted therein.