JP3217811B2 - Sine wave oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an LCR meter and the like.
For example, the present invention relates to a sine wave oscillating circuit that generates a sine wave signal to be applied to an object to be measured during measurement.

[0002]

2. Description of the Related Art Conventionally, as this kind of sine wave oscillation circuit, there is, for example, a configuration shown in FIG. 4, in which a frequency divider 1 in which three or more binary circuits for dividing an input clock pulse are connected in series, A converter 2 of a Walsh transform matrix circuit that generates a Walsh function wave based on the output of each binary circuit, and weighting necessary for obtaining a pseudo sine wave is performed on the output Walsh function of the converter 2 It comprises a combining unit 3 for combining, and a filter unit 4 for shaping the waveform of the combined wave signal output from the combining unit 3 into a pseudo sine wave and removing harmonics contained in the pseudo sine wave.

When a pseudo sine wave having a frequency f is obtained, a clock having a frequency (8 · f) that is eight times that of the frequency f is input to the frequency dividing section 1. A Walsh function corresponding to the clock of (8 · f) is generated.

[0004] Then, as shown in FIG.
, The Walsh function is weighted with amplitude, and these weighted Walsh functions are synthesized. By passing the synthesized wave signal through the filter unit 4, a pseudo sine wave signal having the frequency f can be obtained.

In this case, low-order harmonics do not appear in the synthesized wave signal output from the synthesizing unit 3. For example, when the pseudo sine wave is divided into eight, harmonics up to the sixth order do not appear. Can be suppressed, and only the higher-order harmonics need to be removed, so that the cut-off frequency of the subsequent filter unit 4 can be set higher.

Further, since the cutoff frequency of the filter unit 4 can be increased, the response speed of the output pseudo sine wave signal and the phase characteristics of the filter unit 4 can be improved. For details, see JP-A-53-117361.
Please refer to Japanese Patent Publication No.

[0007]

However, the sine wave oscillation circuit requires a clock having a frequency of 8 · f with respect to the frequency f of the output pseudo sine wave. In order to obtain the clock, it is necessary to generate a clock having a frequency eight times that of the clock, that is, a high-frequency clock. Further, since the variable range of the clock is widened, the clock is generated with high precision by a PLL circuit or the like. There is a problem that it is difficult.

When the frequency of the output pseudo sine wave is changed, the frequency of the input clock may be changed. However, it is necessary to change the cutoff frequency of the filter unit 4 accordingly. A plurality of filters must be prepared, and these filters must be switched according to the frequency of the output sine wave.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to easily create a clock for obtaining a pseudo sine wave, and to set a cutoff frequency of a filter for obtaining a sine wave from the pseudo sine wave. It is an object of the present invention to provide a sine wave oscillation circuit which is fixed, can obtain sine waves of various frequencies, and can remove harmonic components contained in the sine waves.

[0010]

Means for Solving the Problems To achieve the above object,
Because, the present invention, the first filter means, clock 1 / N of the previous SL frequency (fc) of a sine wave signal No. of waveform shaping the clock of a predetermined frequency (fc) the frequency (fc)
Frequency-divided by a frequency dividing means for outputting, said dividing means frequency output clock to M times (M / N · fc = fs , however,
In fc / 2 <fs <fc, M, N is a PLL means for outputting a clock of both integers), and pulse generating means for generating an impulse rise of the output clock of the PLL means or at the timing of the falling, the output impulse of the pulse generating means and a mode control signal for sampling, sampling the output sine wave signal <br/> of the first filter means, and hold to stepped pseudo sine
A sample / hold means for outputting a No. wave signal, said samples <br/> Le / the pseudo sine wave signal No. outputted from the hold means by a waveform shaping with a sine wave signal No. of frequency (fc-fs) , e Bei and second filter means of the fixed cutoff frequency to remove the harmonics contained in the sinusoidal signal, the M / N
Of the sample / hold means according to the ratio of
Change the sampling frequency and simulate the output of the sample / hold means.
Passing a similar sine wave signal through the second filter means.
Therefore, various frequencies (f
c-fs) is obtained.

According to this configuration, by changing the ratio of M / N , the period of the output impulse of the pulse generating means is changed, that is, the sine of the frequency (fc) in the sample / hold means is changed. The sampling timing of the waves is shifted.

Then, the frequency fc-fs of the step-like pseudo sine wave signal output from the sample / hold unit is obtained.
When the pseudo sine wave signal is passed through the second filter section, a sine wave having the frequency fc-fs can be obtained, that is, sine waves having various frequencies can be obtained.

At this time, when the pseudo sine wave of the predetermined frequency is obtained, the frequency variable range of the clock generated in the PLL unit is small, so that the input clock can be easily created.

Further, since the sine wave obtained by the pseudo sine wave signal is divided into a predetermined number, a low-order harmonic does not appear in the output pseudo sine wave according to the division number.
That is, the lower harmonics are suppressed.

Further, the obtained sine wave has a frequency of 2 fs.
Since only harmonics having a frequency equal to or higher than -fc, that is, higher than the frequency of the sine wave appear, the cutoff frequency of the second filter unit can be fixed to a high value at which the harmonic can be removed. When obtaining sine waves of various frequencies, it is possible to remove harmonics contained in the sine waves by the second filter unit having the fixed cutoff frequency.

Further, since the variable range of the M / N may be narrower than the variable range of the frequency of the pseudo sine wave, the response speed of the output sine wave can be further improved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, the sine wave oscillation circuit includes a first filter unit 10 that shapes a clock of a predetermined frequency (fc) to obtain a sine wave of the same frequency, and reduces the clock of the frequency (fc) to 1 / N. Frequency divider 11 for frequency division
A PLL unit 12 for multiplying the frequency (1 / N) · fc clock by M times, and a frequency (M / N) · fc
(= Fs) The impulse generator 13 generates an impulse at the rising edge of the clock, for example.
A sample / hold unit 14 for sampling and holding the sine wave output from the first filter unit 10 using the impulse as a mode control signal for sampling;
The sampled and held step-like pseudo sine wave signal (frequency fc-fs) is shaped into a sine wave, and a second filter unit having a fixed cutoff frequency for removing harmonics contained in the sine wave. 15 is provided.

Note that M and N are integers, and can be set according to the frequency of the sine wave to be obtained.

Next, the operation of the sine wave oscillation circuit having the above configuration will be described with reference to the timing charts of FIGS. Note that the relationship between fc and fs of the frequency is fc / 2
It is assumed that <fs <fc is satisfied.

First, if the frequency (fc) of the input clock is 1
MHz, and the sampling frequency fs (= M / N · f
c) is between 900 kHz and 999 kHz, ie M
/ N is 0.9 to 0.999.

A 1 MHz frequency clock (FIG. 2)
When the clock shown in (a) is input to the first filter unit 10 and the frequency divider 11, as shown in FIG.
The input clock signal is shaped into a sine wave by the first filter unit 10.

On the other hand, as shown in FIG. 2 (c), in the frequency dividing section 11 and the PLL section 12, the input clock is multiplied by M / N, but in this case, it is 900 kHz to 999 kHz. A clock of any frequency can be obtained.

For example, if the M / N is 0.900,
As shown in FIG. 2D, an impulse is output from the impulse generating unit 13 at a rising timing of the 900 kHz clock by the 900 kHz clock.

This impulse is applied to the sample / hold unit 1
4, the pseudo-sine wave whose waveform has been shaped by the first filter unit 10 (FIG. 2B)
Are sampled and held by the impulse. By this sampling and holding, a step-like signal is obtained. This step-like signal corresponds to a pseudo sine wave, and fc-fs = 1 MHz-900 kHz.
= 100 kHz (shown by the solid line in FIG. 2 (e)).

The details will be described with reference to the enlarged time chart of FIG. 3. The frequency (fc) of the input clock and the PL
The frequency (fs) of the output clock of the L unit 12 is defined as M /
In accordance with the value of N, there is a slight shift with time (shown in FIGS. 7A and 7C),
Rising edge of the output clock (a, b, c, d,
The points e and f) and the zero cross point of the sine wave output from the first filter unit 10 shift with time and gradually increase (as shown in FIGS. 3B and 3C).

Therefore, if the output sine wave of the first filter section 10 is sampled and held at the rising edge of the output clock of the PLL section 12, as shown by the solid line in FIG. A step-like signal divided into a predetermined number by an impulse generated by the output clock, that is, a pseudo sine wave signal having a predetermined frequency (fc−fs) can be obtained.

Therefore, a step-like signal sampled and held at 900 kHz (a pseudo sine wave signal)
Is passed through the second filter unit 15 so that 100 kHz
A sine wave having a frequency of z (fc-fs) can be obtained (shown by a broken line in FIG. 2E).

If the above-mentioned M / N is set to 0.999, the frequency fc-fs = 1 from the second filter unit 15 is obtained.
Since a pseudo sine wave of MHz-999 kHz = 1 kHz is output, a high frequency pseudo sine wave of 1 kHz to 100 kHz can be obtained by changing the M / N and changing the period of the impulse. .

Moreover, when obtaining a high-frequency pseudo sine wave signal, the input clock of 1 MHz does not have to be so precise, and when obtaining a sine wave through the first filter unit 10, the sine wave is The input clock can be easily created without distortion.

Since the sampled and held pseudo sine wave signal has a shape obtained by dividing a sine wave into a predetermined number, for example, when the number of divisions of the sine wave is 20,
As in the prior art, no harmonic up to the 19th harmonic appears in the pseudo sine wave signal.

The lowest frequency of the harmonic is 2 fs-
fc (experimental formula). For example, when the frequency of the input clock is 1 MHz and a pseudo sine wave of 1 kHz to 100 kHz is to be obtained, the second filter unit 15
Before passing through the pseudo sine wave signal, the lowest frequency is 800 kHz
Only higher harmonics from z to 998 kHz or more appear.

Therefore, since it is only necessary to remove the higher harmonics of 800 kHz or more, the cutoff frequency of the second filter unit 15 for shaping the pseudo sine wave signal into a sine wave is changed to the pseudo sine wave frequency (1 kHz to 1 kHz). 100 kHz), which means that only one filter having a fixed cutoff frequency is required, and the design of the second filter section 15 can be facilitated.

In order to obtain a pseudo sine wave of 1 kHz to 100 kHz, the frequency of the output clock of the PLL unit 12 may be varied between 900 kHz and 999 kHz, that is, the variable range is narrower than that of the output pseudo sine wave. Thus, the response speed of the pseudo sine wave can be further increased.

[0034]

As described above, according to the sine wave oscillation circuit of the present invention, the first filter for shaping the input clock of the predetermined frequency (fc) into a sine wave, and the input clock generates the M signal. A frequency dividing unit and a PLL unit for obtaining a clock having a frequency of / N · fc (= fs), an impulse generating unit for generating an impulse at the rising edge of an output clock of the PLL unit, and using the impulse as a mode control signal for sampling. A sample / hold unit that samples and holds the sine wave passed through the filter and outputs a step-like signal (pseudo sine wave signal) corresponding to a sine wave with a clock frequency of fc-fs; And a second filter section for shaping the signal to output a sine wave and removing a harmonic contained in the sine wave, and varying the M / N. Thus, a pseudo sine wave having a frequency fc-fs is obtained, so that the pseudo sine wave signal is passed through the second filter unit to obtain a sine wave, and when the frequency of the sine wave is varied, Since the sine wave obtained by the pseudo sine wave signal is divided into a predetermined number, low-order harmonics can be suppressed in accordance with the division number, and the pseudo signal obtained by the step-like signal is obtained. Since only higher harmonics (2fs-fc) or higher frequencies than the frequency of the sine wave appear, the cutoff frequency of the second filter section can be fixed to a high value, thereby providing one filter having a fixed cutoff frequency. Thus, there is an effect that harmonics included in the sine wave can be removed, and the design of the second filter section becomes easy.

According to the present invention, when a pseudo sine wave having a variable frequency is obtained, when the input clock is passed through the first filter unit to obtain a sine wave, the sine wave only needs to be free from distortion. It is easy to create an input clock and P
Since the frequency variable range of the clock generated in the LL section is small, it is easy to create the clock.

Further, according to the present invention, when varying the output pseudo sine wave, the variable range of the M / N may be narrower than the variable range of the pseudo sine wave, so that the response speed of the pseudo sine wave is improved. Can be further improved.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a sine wave oscillation circuit showing one embodiment of the present invention.

FIG. 2 is a schematic time chart illustrating the operation of the sine wave oscillation circuit shown in FIG.

FIG. 3 is a schematic enlarged time chart for explaining the operation of the sine wave oscillation circuit shown in FIG. 1;

FIG. 4 is a schematic block diagram of a conventional sine wave oscillation circuit.

5 is a schematic waveform diagram illustrating the operation of the sine wave oscillation circuit shown in FIG.

[Explanation of symbols]

 Reference Signs List 10 first filter section 11 frequency division section (1 / N frequency division) 12 PLL section (M times) 13 impulse generation section 14 sample / hold section 15 second filter section

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03B 28/00

Claims (1)

(57) [Claims] 1. A first filter means a sine wave signal. No. clock waveform shaping to the frequency of the predetermined frequency (fc) (fc), dividing the clock 1 / N of the frequency (fc) Frequency dividing means for outputting the divided clock, and a frequency obtained by multiplying the output clock of the frequency dividing means by M (M / N ·
fc = fs , where fc / 2 <fs <fc and M, N
PLL means for outputting a clock of an integer clock, pulse generating means for generating an impulse at the rising or falling timing of the output clock of the PLL means, and mode control of sampling the output impulse of the pulse generating means. as a signal, the first sampling the output sinusoidal signal of the filter means, and hold to a sample / hold means for outputting a stepped No. pseudo sine wave signal, the pseudo output from the sample / hold means with a sine wave signal <br/> No. performs waveform shaping to a sine wave signal No. of frequency (fc-fs), a second filter means fixed cut-off frequency to remove the harmonics contained in the sinusoidal signal comprising a, by the ratio of the M / N, the sample / hold means
Change the sampling frequency of the
The output pseudo sine wave signal of the stage is passed through the second filter means.
In this way, various harmonics of a predetermined order or higher are removed.
A sine wave oscillation circuit for obtaining a sine wave having a frequency (fc-fs) .