JP3213022B2 - Antenna for wireless local area network station - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

This invention relates to a local area network (LA) in which a plurality of stations communicate with another station via a transmission medium for transmitting digital data.
N).

[0002]

2. Description of the Related Art Local area networks (hereinafter, L)
Various methods are known for sharing network communication channels or links between stations within an AN). One widely used method is the carrier sense multiple access method that performs collision detection.
iple access with collision detect, hereafter CSMA /
CD method). According to this known method, a station wishing to transmit a message intercepts the communication channel until it becomes idle before beginning to transmit the message. In addition, the station continues to listen to the channel after starting to transmit. If a collision is detected, that is, if two or more stations start transmitting information packets, the station that detects the collision stops transmitting messages and all other stations have a collision. In response to the notification, the transmission of the message is stopped, and a jam pattern (signal of unknown meaning) is transmitted so as to wait a random time before starting transmission of the message.

[0003] The CSMA / CD protocol is based on the International Standard (ISO) and the corresponding IEEE standard 802.
No. 3 and is a common protocol used for LANs between stations using wired connections. Several manufacturers produce chips for it according to IEEE Standard 802.3. One example is Intel 8258 commercially available from Intel Corporation of Santa Clara, California, USA.
There are six LAN coprocessors. Such a chip is LA
Provides various functions useful in N, such as data rate domain, backoff algorithm, slot duration, offset and limit of replay counter, and interframe interval period.

[0004] However, a LAN with a wired connection has a disadvantage that a large number of cables are required for interconnection between stations. Providing such a cable is generally inconvenient and inflexible if one wants to change the physical location of the station. Then L
It has been proposed to use a radio communication link operating at radio frequency instead of the cable that performs the interconnection of the ANs. However, if a single radio channel must be used for such a LAN, the widely used CSMA / CD protocol is generally not applicable. This is because stations generally cannot receive (ie, listen) during transmission.

[0005] European Patent Application No. 0648818 discloses a wired LAN utilizing a data collision avoidance method. Each station with a data packet ready for transmission monitors the activity of the communication channel. If communication activity on the channel is detected, the station waits until the channel becomes idle,
It then waits for a random time, at the end of which, if the channel is still idle, it performs the transmission.

[Problems to be solved by the invention]

It is an object of the present invention to provide a LAN station suitable for a single-channel electromagnetic wave transmission link which enables high-throughput data communication with a simple configuration and at low cost.

[0007]

SUMMARY OF THE INVENTION Accordingly, the present invention is a transceiver device operating on a radio electromagnetic wave transmission channel (hereinafter referred to as a channel) having a plurality of antennas in a local area network station, wherein the channel is inactive. A communication control device that operates to delay transmission of a data frame (hereinafter referred to as a delayed data frame) for a back-off period for a random number;
Controlling an antenna switching device to select one of the plurality of antennas for operation in connection with the transceiver device and to provide an antenna slot period having a duration equal to the back-off period; A synchronizer for synchronizing the start of the data frame transmission with the start of the antenna slot period.

Another aspect of the present invention is a method of transmitting a data frame in a local area network including a plurality of local area network stations each including a transceiver device and a plurality of antennas adapted to operate on a radio transmission channel. (A) if the transmission channel is active at each station, delay the transmission of data frames for a random number of backoff slot periods after the transmission channel becomes inactive at the station; (B) providing switching means at each station for sequentially connecting each of the antennas to the transceiver device for a period equal to one of the back-off slot periods; c) the network in the network Providing a data frame transmission method characterized by comprising the step of synchronizing said antenna slot time period for all stations.

Since the local area network station according to the present invention uses a commercially available CSMA / CD controller chip as a communication controller, it has a simple and inexpensive configuration, is suitable for a single channel electromagnetic wave transmission link, and has a CSMA Provides high data throughput by using multiple antennas synchronized to the / CD backoff slot. The reason for the high data throughput is that this synchronizer provides a small carrier detection time. This will be described later in detail.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to FIG. 1, there is shown a local area network (radio LAN) 10 including a plurality of stations 12, individually designated 12-1 to 12-N. Each station has two antennas 14 and 16, each polarized in a different direction. These are individually designated as 14-1 to 14-N and 16-1 to 16-N. Alternatively, the two antennas 14, 16 may be pointing in different directions.

The communication between stations 12 is on a single radio channel and uses spread spectrum communication technology (spread).
spectrum communication technology). In the indoor radio LAN of the preferred embodiment,
A 902-928 MHz band is used. Another suitable frequency band is around 2.5 GHz.

Referring now to FIG. 2, a block diagram of the components of a representative station 12 is shown. These show blocks related to the present invention. Station 12 includes a transceiver 20, a LAN controller 22, a central processing unit (CPU) 24, and a memory 26.
The local bus 28 is connected to the LAN controller 22 by a bus 30 and the central processing unit 2 by a bus 32.
4 or to the memory 26 by a bus 34. The LAN controller 22 uses the CSMA / CD method (carrier sense multiple access with collision det).
section, carrier sensing multiple access method by collision detection)
It is a commercially available LAN control device suitable for the protocol. In the preferred embodiment, the LAN controller 22 is an Intel 82586 LAN coprocessor chip available from Intel Corporation of Santa Clara, California, USA.

The transceiver 20 and the LAN controller 22 are interconnected by a bus 36 carrying data and control signals. The station 2 has a transceiver 2
0 and a LAN controller 22 and a signal generation circuit 40 and an antenna slot control circuit 200 are included. The signal generation circuit 40 receives a transmission clock pulse TXCLK from the transceiver 20 via a line 42,
N controller 22 sends a transmission request signal (reques
t-to-send).

The signal generating circuit 40 also has a line 4
Carrier sense signal CRS and clear-to-send signal C from transceiver 20 via 6 and 48.
Receive TSA. The TXCLK pulse on line 42 and the CRS signal on line 46 are applied directly to LAN controller 22.

Signal generation circuit 40 transmits a transmission request signal R via line 50 connected to antenna slot control circuit 200.
It outputs the TSB and outputs the line 52 connected to the LAN controller 22.
, And a pseudo collision detection signal C via a line 54 also connected to the LAN controller 22.
Output DT. The various signals applied to and provided by the signal generation circuit 40 will be described later in detail.

The LAN controller 22 is connected to the central processing unit 24 via signal lines 60 and 62, and a control signal (for example, an interrupt signal) can pass between the central processing unit 24 and the LAN controller 22. .

The output of antenna slot control circuit 200 is connected via line 202 to the control input of switch 204. Switch 204 has terminals 206 and 208 which are coupled to antennas 14 and 16, respectively. For convenience, antennas 14 and 16 are referred to as antennas A and B, respectively.
Another terminal 210 of the switch 204 is
And a transceiver 212 via a line 212 for transmitting RF signals between the antennas 14 and 16. The antenna slot control circuit 200 provides a transmission request signal RTSC to an output line 220 connected to the transceiver 20. The output line 202 is connected to the transceiver 20 via a line 222 and operates with a specific antenna A or B.
Is provided to the transceiver 20.

Antenna slot control circuit 200 also receives via line 224 an input identifying whether transceiver 20 is in a transmit mode or a receive mode.
Another control signal (described below) is received via lines 226, 228 coupled to transceiver 20.

Station 12 also includes a slot synchronization control circuit 240 that provides a synchronization control signal to antenna slot control circuit 200 via line 242. This slot synchronization control circuit 240 also transmits / receives mode signal T / R MODE from transceiver 20 via line 244.
2 and coupled to transceiver 20
A control signal ED (described later) is received via 46. 2MH
z local oscillator 250 provides a locally generated clock signal (CLK) via line 252 to slot synchronization control circuit 240 and LAN controller 22.

The transceiver 20 outputs a signal RXCLK indicating "receive a clock signal" and a signal RXDATA indicating "received a data signal" to the lines 260 and 262 included in the bus connected to the LAN controller 22, respectively.
Receive through.

The LAN controller 22 is, for example, the IEEE
Protocol CSMA / CD defined in standard 802.3
It should be understood that it works according to. As described above, the LAN controller 22 is a commercially available LAN control device. The operation of such a controller according to its use in a CSMA / CD system will be briefly described with reference to background information that will aid in understanding the invention. CSMA / CD
When used in a wired LAN utilizing a legal protocol, this controller constantly monitors the activity of the link. Whenever the controller senses a carrier signal on the link, it delays the passage of data frames by delaying all pending transmissions. After the carrier signal becomes inactive, the controller continues to delay for an interframe period of several clock cycles. If there is a frame to be transmitted at the end of that time, it starts transmitting independently of the sensed carrier. After the transmission has begun, the controller attempts to transmit the entire frame. Usually, the frame transmission is completed and notified to the host processor. However, the transmission may be terminated before completion. This occurs, for example, when a collision detection signal is input to the controller, as described below. When the controller completes the delay and starts transmitting, it may still experience link conflicts. This situation is called a collision and is generally detected by a transceiver. This collision activates the collision detection input of the controller. The controller signals the collision by sending a jam pattern to other stations. This jam pattern is detected by another station on the LAN. The dynamic handling of collisions is largely determined by the so-called "slot time". The slot time is configurable and is typically the maximum end-to-end delay time of the network (the time from the end of the delay in the network to the next end) plus the jam time. Slot time is important. The reason is that it is the worst time to detect a collision. After a collision has occurred, the controller attempts to retransmit the frame after a so-called backoff time, unless the number of retransmission attempts exceeds the maximum allowed. The controller calculates the backoff time according to the IEEE 802.3 standard. The back-off time is an amount obtained by integrating the slot time. It is a random number from 0 to the maximum. Its maximum value is 2 ^R -1, where R is 1
This is the minimum value between 0 and the number of retransmission attempts. This range can be extended using "accelerated collision resolution" mechanisms. This function can be applied to give a range from 0 to the maximum value 2 ^{R + K} -1. Here, K is the offset number of the retry counter, and R + K is a maximum value of 10. It should be appreciated that the controller includes a retry counter that increases with each retransmission attempt. If the transmission is successful, the user is notified accordingly. If the number of retries exceeds the maximum,
An error is reported.

Returning to the single channel radio LAN 10 of FIG. 1, it is difficult to apply the CSMA / CD protocol since the transmitting station 12 cannot receive the signal. Therefore, it makes collision detection difficult or impossible. However, if the danger of a collision is small, there is a possibility that the CSMA method can be applied without detecting the collision. This requires that all communication activity on the carrier be detected very quickly, in order to minimize the possibility that different stations will start transmitting at the same time or at very close times. This carrier detection time can be considered as a period during which a collision can occur and therefore must be small compared to the duration of the message. In a radio LAN, several factors contribute to the carrier detection time. That is, transceiver delay (transmitter and receiver) and air delay contribute.
The major part of the carrier delay time (about 30 microseconds) is due to the receiver, which comes from the automatic gain controller, correlation filter and carrier signal detection. Air delays for indoor distances of 300 meters or less are small (less than 1 microsecond). This carrier detection time is long compared to the carrier detection time of 1 to 6 microseconds in a typical wired LAN. Therefore, it is disadvantageous to apply the CSMA method directly to a radio LAN.

Referring again to FIG. 2, the signal generation circuit 40
Effectively simulates a collision. This provides a CDT (collision detection) signal on line 54 when data frame transmission is delayed, even if no actual collision has occurred.
Thus, transmission of the delayed data frame is started only after the elapse of the random backoff time. In this way, the risk of collisions resulting from the stations 12 starting transmitting simultaneously or at very close time intervals is significantly reduced.

With the above in mind, the signal generation circuit 40 will be described with reference to FIG. The input line 42 carrying the TXCLK pulse is connected to an inverter 70, the output of which is connected to the count input of a 4-bit counter 72.
The counter 72 has its QD output connected to the 4-bit counter 76 via a line 74 and its QB output connected to the D input of a D-type flip-flop 90 via a line 78. The input line 46 for providing the carrier sense signal CRS is connected via lines 84 and 86 to the reset inputs of the counters 72 and 76, respectively. Apparatus 70, 7
2, 76 together form a timer (generally designated 88) such that the active signal appears at the QB output of counter 76 after 32 TXCLK periods, measured from the falling edge of the CRS signal. Please understand that.

The Q output terminal of the flip-flop 90 (FIG. 3) is connected to the clock input terminal of a D-type flip-flop 92. This clock input of flip-flop 90 is connected to input line 42 via line 94. The D input of flip-flop 92 is connected to supply voltage Vcc. The input line 46 is connected to an inverter 98, the output of which is connected to the flip-flop 9 via lines 100 and 102, respectively.
0 and 92 are connected to the reset input terminals. With this configuration, the Q output terminal of flip-flop 92 provides window start signal WS on output line 104.

Line 104 is an 8-bit shift register 106
3 (FIG. 3), and its clock input is connected to TX via line 108 connected to input line 42.
Receive a CLK pulse. The output terminal of the shift register 106 is connected to each input terminal of the header 109. The header 109 has its output end connected to the line 110 in common,
As a result, a desired one of the outputs of the shift register is selected and a desired delay signal is supplied to the output line 110. Line 1
10 is connected to the inverter 112. Inverter 11
The output on line 114 provides an active low level window end signal WE /. WS on lines 104 and 114
The signal and WE / signal are applied to AND gate 116. The output of gate 116 provides a wind signal WD on line 118.

The wind signal WD on line 118 is OR
Applied to gate 120, the output of which is connected to the D input of D-type flip-flop 122, while its Q output is connected to output line 54 to provide a dummy collision detection signal CDT. The clock input of flip-flop 122 is connected to line 124, and TXCL
Receive K pulse. The reset input of flip-flop 122 is connected to input line 44 via line 126.
Line 44 carries a transmission request signal RTSA.

The Q output of flip-flop 122 (FIG. 3) is also connected via line 128 to the input of OR gate 120 and the input of OR gate 130. The other input terminal of the OR gate 130 is connected to the output terminal of the AND gate 132. AND gate 132 has an input terminal connected to the output terminal of inverter 98 and an output terminal connected to inverter 112, respectively.
Are connected respectively to the output terminals.

The input line 44 is also connected to the inverter 134, the output terminal of which is connected to the input terminal of the NOR gate 136, and the second input terminal thereof is connected to the output terminal of the OR gate 130. The output of the NOR gate 136 is connected to a line 50 for providing a transmission request signal RTSB.

The input line 48 is connected to an inverter 138 (FIG. 3), and its output is connected to a NAND gate 140 (FIG. 3).
And a second input terminal of the flip-flop 122
Q / output. An output terminal of the NAND gate 140 is connected to an output line 52 for applying the transmission release signal CTSB.
Connected to.

The operation of the signal generation circuit 40 (FIG. 3) will be described briefly. When the carrier sense signal CRS on line 46 falls, timer 88 provides an active output signal on line 78 after 32 TXCLK pulse periods. These 32 periods correspond to an inter-frame interval (IFS) time. The output of timer 88 is synchronized by flip-flop 90 to eliminate any voltage spikes. The CRS / signal at the output of inverter 98 ensures that flip-flops 90, 92 are enabled when signal CRS falls. The output of flip-flop 92 provides a window start signal WS 32 TXCLK pulse periods after the CRS signal drops. When the window start signal WS on line 104 is inactive, it resets the shift register 106. When window start signal WS becomes active, it is delayed and inverted by shift register 106, header 109, and inverter 112 to provide an inverted window end signal WE / on line 114. The WS signal on signal line 104 and the WE / signal on line 114 are coupled to AND gate 116.
To provide a wind signal WD. This WD signal is generated during N TSCLK pulse periods (N is a predetermined number).
Become active. Here, N is a number between 1 and 8 and is selected by selecting a desired one of the outputs QA through QH of the shift register 106 by connecting a corresponding number of pins on the header 109. . In the preferred embodiment, the output QD of shift register 106 is selected,
Thus, when window signal WD becomes active, this output signal remains active for 4 TXCLK cycles.

If signal RTSA on line 44 goes active during the active state of the wind signal, flip-flop 122 provides a signal CDT on line 54 to simulate a collision. Flip-flop 1 with line 128
The feedback from 22 to the OR gate 120 ensures that when the signal CDT goes active, the signal CDT remains active until the signal RTSA edge falls (after the controller 22 has completed transmitting the preamble and the jam pattern). .

Inverter 138 and NAND gate 1
40 ensures that the signal CTSB follows the signal CTSA unless the signal CDT is active (no simulated collision). When signal CDT becomes active, signal CTSB also becomes active independently of signal CTSA.

The signal RTSB is supplied to the inverter 134, AND
Gate 132, OR gate 130 and NOR gate 1
36 is generated. Thus, if signal CDT is active, signal RTSB does not follow signal RTSA. Therefore, this prevents transmission of the preamble and the jam pattern. Also, since signal CTSA / coming from inverter 138 is applied to NAND gate 140 along with the output of flip-flop 122, signal CTSB will be the same as signal CTSA as long as signal CDT is inactive.
Follow.

If another station is transmitting a data frame but station 12 (FIG. 2) has not requested the transmission of the data frame, after a 32-bit IFS (interframe interval) time, the window signal WD will be asserted. It will be appreciated that although generated, the window signal WD has no significant effect since the station 12 has not requested a data frame to be transmitted. If station 12 is requesting a data frame to be transmitted but other stations are inactive, the waveforms are shown with the CRS signal remaining low. Under this condition, no wind signal WD is generated.
The transmission request signal RTSA causes the signal generation circuit 40 to generate a transmission request signal RTSB to the antenna slot control circuit 200. Transceiver 20 responds to this by providing transmission cancellation signal CTSA to signal generation circuit 40, and circuit 40
A transmission cancellation signal CTSB is given to the N controller 22.
This enables data frame transmission.
If another station is transmitting a data frame, the signal CRS of the station 12 is activated when the LAN controller 22 of the station 12 is notified that the station 12 wants to transmit a data frame. It has become. Under this condition, the transmission of the data frame in the station 12 is delayed by the LAN controller 22. After the signal CRS becomes inactive and the inter-frame interval time IFS has elapsed, the window signal WD is generated in the signal generating circuit 40 in the manner described above with reference to FIG. Since LAN controller 22 also activates signal RTSA at this time, signal generation circuit 40 activates signal CDT on line 54 to simulate a collision. This causes the LAN controller 22 to stop the transmission after the transmission of the preamble and the jam pattern is completed. However, these patterns are not transmitted by station 12. The reason is that the signal RTSB is not generated if the collision is simulated. Therefore L
The AN controller 22 is set in the back-off mode, and calculates the back-off time based on the slot time for the random number as described above. After the elapse of the random number back-off period, the LAN controller 22 attempts to retransmit the delayed frame as shown on the right side of FIG.

Referring to FIG. 4, a diagram of a representative data frame 300 transmitted within LAN 10 is shown. This data frame 300 contains a preamble (P) for adjusting its parameters, such as the gain of the receiving station, to optimal values.
R) portion 302, a network identification portion (NWID) 306 that identifies the particular network 10 transmitting the data frame 300, a user data portion 308 that includes the source and target station addresses along with the transmitted data, and an end delimiter portion (ED). ) 3
10 inclusive.

Referring to FIG. 5, a block diagram of slot synchronization control circuit 240 (FIG. 2) is shown. Line 25
2 above are applied to the cyclic counter 350. This counter typically produces an output signal on line 352 every 40 microseconds (80 CLK pulses). Line 352 is connected to stop synchronization logic 354, which is enabled in response to the signal on line 356, blocks the pulse on line 352, and
8 is disabled (disabled) in response to the signal on 8 and passes the pulse on line 352. Stop synchronization logic 354 has an output connected to line 242 and, when enabled, outputs the output signal of counter 350 on line 24.
2, and when the function is stopped, the passage of the output signal is suppressed. Stop synchronization logic 354 has its output connected to line 242 and passes the output signal from counter 350 when enabled, while suppressing the output when disabled. The slot synchronization control circuit 240 includes a delay circuit 360. This circuit receives the CLK pulse on input line 362 and its output is connected on line 364 to the reset input of counter 350. Line 364 is also connected to line 358. Delay circuit 360 also has its first input connected to line 244. This line 244 is a signal T / R identifying whether the station is in a transmission mode or a reception mode.
It carries MODE. The second input of circuit 360 is line 2
46. This line carries the signal when the transceiver 20 detects the end of data frame delimiter ED (FIG. 4). As described later, this configuration can selectively provide a delay in resetting the counter 350.

Referring now to FIG. 6, a block diagram of the antenna slot control circuit 200 (FIG. 2) is shown. Slot synchronization control circuit 2 sent over line 242
The signal from 40 is applied to the synchronization start logic 380,
This circuit 380 receives at its input the request-to-send signal RTSB on line 50 and at its output the transceiver 2
A request to send signal RTSC is provided on line 220 tied to 0. Input line 242 is also connected to antenna switch control logic 384 via line 382. The antenna switch control logic 384 also has a line 224 as its input.
The upper signal T / RMODE, the enable switching input signal on line 226, is received to control switch 204 (FIG. 2) to select antenna A or B.

As described above, the CSMA / CA method (carrier sensing multiple access method with collision avoidance) and two antennas 1
The local area network station 12 for wireless radio LAN using 4 (antenna A) and 16 (antenna B) has been described.

The operation of the above described circuit is described below.
The present invention relates to time slot control in the MA / CD method.

Station 12 is in either a transmit mode or a receive mode. Switch 204 (FIG. 2) has two states, state A in which antenna A operates and state B in which antenna B operates. In the transmission mode, the switch 204 is controlled by the antenna slot control circuit 200 so as to be in the state A. That is, the antenna A is always in operation for transmission. When the station 12 is not in the transmission mode, the switch 204 is in the reception mode, and unless carrier detection is performed (ie, when the signal CRS in FIG. 2 is inactive), switching occurs every antenna slot time, and the station 12 is in the state. A
And B alternate. This antenna slot time is chosen equal to the back-off slot duration described above for the LAN controller 22. As will be described later,
This antenna slot period is synchronized with the backoff slot period. The duration of the antenna slot period is selected to correspond to the time required to make carrier detection reliable. This synchronization obtained by the slot synchronization control circuit 240 and the antenna slot control circuit 200 controls the timing of antenna switching and transmission start.

From the above discussion of LAN controller 22, it should be appreciated that at the start of any one of a variety of different time slots, LAN controller 22 can begin transmitting delayed data frames. As mentioned above, the circuits described herein provide synchronization between transmissions. This gives a minimum carrier detection time when transmitting the delayed frame, thus reducing the risk of collision. Similarly, antenna switching and the start of transmission of a new (ie, non-delayed) data frame are synchronized, with the same benefits.

When the station 12 desires to transmit a data frame, the transceiver 20 goes into transmission mode,
T / R representing transmission mode on lines 224, 244 (FIG. 2)
Give a MODE signal. Assuming that the transmission was granted, the preamble PR, start delimiter SD (4 symbols), network ID (16 symbols), user data symbol,
And finally, a data frame 300 (FIG. 4) containing the end delimiter ED (four symbols) is transmitted. As described above, when the station 12 is not in the transmission mode, it is in the reception mode, and an appropriate T / R MODE signal is supplied. When a data frame is received, transceiver 20
The detection mechanism within identifies the beginning of significant data for the starting delimiter SD (FIG. 4). Transceiver 20 is connected to line 26
The user data (RXDATA) is sent to the LAN controller 22 via the LAN controller 2 (FIG. 2). The end of the received data frame is determined by detecting the end delimiter ED. This delimiter consists of four symbols following the last data bit. The ED detection signal on line 246 is used to reset cyclic counter 350.

Referring now to FIGS. 5 and 7, how the slot synchronization control circuit 24 is activated after the carrier is activated.
It will be described whether 0 is reset. In FIG. 7, the upper three waveforms relate to the station 12 in transmit mode, and the lower three waveforms relate to the station in receive mode. In particular, the first and fourth waveforms represent transmission and reception of a data frame, respectively. The second and fifth waveforms are line 3 during the data frame transmission and reception periods, respectively.
52 (FIG. 5). And the third and sixth waveforms represent the signal on line 242 (FIGS. 5 and 6) during the transmission and reception of the data frame, respectively.

The slot synchronization control circuit 240 operates at intervals of 60 milliseconds, that is, 120 CLK cycles after the detection of the end delimiter ED of the transmission frame, in order to allow the station 12 to transmit as described above. This time is, in the preferred embodiment, 4 microseconds, which is the time to compensate for transceiver delay and air delay, followed by an extended interframe time formed by two IFS times (interframe interval, 16 microseconds each); 8 microsecond preamble (PR) time (equivalent to 2 byte preamble)
And a jam time of 16 microseconds. The 16 micron corresponds to the length of the jam pattern generated after the LAN controller 22 detects (simulated) collision. This IFS time and preamble time are L
It is programmed into the AN controller 22. The extended interframe interval time corresponds to the time when the first backoff slot time starts. FIG. 5 and FIG. 7 (transmission mode)
Referring to FIG. 7, after the end delimiter (ED) is detected, the delay of 120 CLK cycles introduced by the delay circuit 360 is changed at the time indicated by the broken line 400 in FIG.
It can be seen that 0 is reset. As shown in FIG. 7, the pulses generated on line 352 (FIG. 5) after detection of signal ED are blocked by stop synchronization logic 354. Thus, the antenna slot control circuit 200 (FIGS. 2 and 6)
The next pulse on line 242 applied to occurs at the time indicated by dashed line 400.

When the station receives the data frame, as shown in the lower part of FIG.
0 is reset after 56 microseconds after detecting the end delimiter ED of the received frame, that is, after 112 CLK cycles. Thus, the reset occurs without the 4 microsecond delay involved at the transmitting station. With this configuration, the slot synchronization control circuits 240 of all the stations 12 of the LAN 10 are accurately reset at the same time indicated by a broken line in FIG.

With particular reference to FIG.
It can be appreciated that transmission can only be started at the beginning of the antenna slot period. Signal generation circuit 4
0 (FIG. 2), when the transmit request signal RTSB becomes active on line 50, the synchronization start logic 380
The signal on line 242 applied to ensures that the transmit request signal RTSC output on line 220 is provided at the beginning of the next antenna slot period. This is because the signal on line 242 is also applied to antenna switch control circuit 384. Transceiver 20 is controlled to the transmit mode, antenna A is selected by the select signal on line 228, and transceiver 20 transmits the preamble (PR), start delimiter (SD), and network ID (NWID) of the data frame. Transceiver 20 also activates signal CTSA on line 48, and signal generator 40 activates signal CTSB on line 52. This signal CTSB causes the LAN controller to transmit the user data in the data frame.

If there is no carrier activity on the transmission channel (CRS inactive) and the station 12 wishes to transmit (issue an RTSA), the signal RTSC becomes active with a delay of 0 to 40 microseconds. This is because the synchronization start logic 380 provides the signal RTSC at the start of the antenna slot.

If station 12 wishes to transmit when there is carrier activity (CRS is active), signal generation circuit 40 is provided when the DRS signal becomes inactive, as described above in connection with FIG. Activates the CDT signal on line 54 to simulate a collision. L
The AN controller 22 then waits for the above time (ie, an extended interframe interval time of 56 microseconds + a backoff slot time of a random number (up to 63) in units of 40 microseconds). Cyclic counter 350
FIG. 5 is reset 112 CLK cycles after the signal ED on line 246 becomes active. This 112 CLK cycle delay corresponds to an interframe interval of 56 microseconds. Thus, the first moment the RTSB signal can be active (0 backoff time) coincides with the first slot sync pulse on line 242 after the cyclic counter 350 has been reset. Similarly, if different number K (unit 40 microseconds)
Is selected by the LAN controller 22, the signal RTSB is reactivated at approximately the beginning of the antenna slot interval.

As described above, the slot synchronization control circuit 2
40 and antenna slot control circuit 200 can reestablish synchronization of antenna switching such that synchronization of all network stations 12 is achieved. Since the transmission of data frames can only be started at the beginning of an antenna slot, this synchronization means that the carrier detection time is minimized at both the station receiving the non-delayed frames and the station receiving the backed-off delayed frames. That is, it is.

Referring now to FIGS. 8A and 8B. Waveform (1) represents the carrier activity on the unsynchronized transmission channel. Waveform (2) represents carrier activity in the synchronized transmission channel. Waveform (3) represents a valid antenna A or B determined by the state of switch 204 (FIG. 2). Waveform (4) shows transceiver 20
Represents the detection of carrier activity at. FIG. 8 (a) shows a situation where it has been determined at 20 that antenna A has been selected for receiving a data frame. FIG. 8 (b) shows a situation where it has been determined at 20 that antenna B has been selected for reception of the received data frame. The selection of antenna A or antenna B can be made based on a determination of which antenna will give a higher signal level, for example during reception of the preamble of the data frame. The carrier detection times 420 and 422 (FIGS. 8 (a) and 8 (b)) when the synchronization between the antenna slot and the start of transmission exists are the carrier detection times 424 and 424 when there is no such synchronization.
It should be understood that it is shorter than 26. It should be appreciated that the minimum carrier detection time (420, 422) is achieved with the above circuit, so that the risk of (real) collision of data frames on the transmission channel is minimized. This is because transmission is delayed if carrier activity is detected. Such a reduced risk of collisions enables a high data throughput to be achieved in the network 10.

After a long period of no carrier activity, the local oscillators 25 at various stations
0 (FIG. 2), the network 10
Station 12 may lack synchronization. However, after the first new transmission occurs, this synchronization is reestablished. Therefore, the carrier detection time is short even under a high network load, and the above-described high throughput can be achieved.

Modifications of the preferred embodiment of the present invention are possible. For example, a frequency exceeding 3000 GHz, for example, an infrared frequency can be adopted as the wireless transmission channel. Also, three or more antennas can be employed.

[Brief description of the drawings]

FIG. 1 is a diagram of a radio LAN.

FIG. 2 is a block diagram of a representative station used in the LAN of FIG.

FIG. 3 is a circuit diagram of a signal generation circuit used in the station of FIG. 2;

FIG. 4 is a diagram showing a representative data frame transmitted on a LAN.

FIG. 5 is a block diagram of the slot synchronization control circuit shown in FIG. 2;

FIG. 6 is a block diagram of the antenna slot control circuit shown in FIG. 2;

FIG. 7 is a waveform chart showing synchronization in the transmission mode and the reception mode of the station.

FIG. 8 is a waveform chart showing carrier detection time and antenna selection.

[Explanation of symbols]

 12 Local Area Network Station 14, 16 Multiple Antennas 20 Transceiver 22 CSMA / CD Communication Controller 200 Antenna Slot Control Circuit

──────────────────────────────────────────────────続 き Continuation of the front page (73) Patent holder 596077259 600 Mountain Avenue, Murray Hill, New Jersey 07974-0636 U.S.A. S. A. (72) Inventor Hans van Driest The Netherlands, 3721 Emjay Vilsau Veng, La Brandenberger Weg 4 (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28

Claims (2)

(57) [Claims] 1. A transceiver device operating on a radio electromagnetic wave transmission channel (hereinafter referred to as a channel) having a plurality of antennas in a local area network station, and when the channel is inactive, a backoff slot period for a random number, A communication controller that operates to delay transmission of a data frame (hereinafter referred to as a delayed data frame), the communication controller including a CSMA / CD local area network (LAN) controller used in a wired LAN; An antenna switching device for initiating the back-off slot period using a simultaneous collision detection signal, selecting one of the plurality of antennas to operate in connection with the transceiver device, and equal to the back-off slot period. Ann with duration Controls the antenna slot device for providing Nasurotto period, local area network station, characterized in that it comprises a synchronization device and to synchronize the start of the data frame transmission to the start of the antenna slot periods. 2. A method for transmitting a data frame in a local area network including a plurality of local area network stations each including a transceiver device and a plurality of antennas adapted to operate on a wireless transmission channel, comprising: If the transmission channel is active at the station, the CSMA / CD local area network (LA) used in the wired LAN
N) determining to delay transmission of the data frame by a random number of backoff slot periods after the transmission channel becomes inactive at the station by using the simultaneous collision detection signal according to the controller; (B) providing switching means adapted to sequentially connect each said antenna to said transceiver device for a period equal to one of said back-off slot periods at each station; and (c) providing said switching means in said network. Synchronizing the antenna slot period for all stations.