JP3212878B2 - I interface signal identification circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a basic layer D.
The present invention relates to an I-interface receiving circuit of a SU (Digital Service Unit), and relates to an I-interface signal identifying circuit for identifying a received signal from a terminal connected to a short-range passive bus.

[0002]

2. Description of the Related Art There are three types of DSU I interfaces: short passive bus connection, extended bus connection, and point-to-point connection. FIG. 3 is an explanatory diagram illustrating an example of a short passive bus connection. As shown in this figure, in the short passive bus connection, a line length of about 2
A DSU is connected to one end of a short-distance passive bus within 00 m, and up to eight terminals (T
E) is connected. Here, the transmission signal of each terminal is superimposed on the short-range passive bus, and the DSU receives the superimposed signal.

At this time, naturally, the terminal-DS
Since the signal transmission distance between U differs for each terminal, the phase difference between the transmission signal (signal transmitted by the terminal) and the reception signal (signal received by DSU) also differs for each terminal. That is, among the terminals actually connected, the phase difference of the terminal closest to the DSU (terminal A in the example shown in FIG. 3; hereinafter, referred to as “the nearest terminal”) is 10 μS,
The terminal furthest to U (terminal D in the example shown in FIG.
The above-mentioned phase difference of the “farthest terminal” is a maximum of 14 μS
Becomes In order to absorb this phase difference, the DSU sets a sampling point for sampling a data frame of a received signal received from each terminal to a position where data bits of all terminals are superimposed (point a in FIG. 4). I have.

Hereinafter, a method of setting the sampling points will be described in detail. FIG. 5 is a block diagram showing a configuration example of a conventional I interface signal identification circuit. Here, the I-interface signal identification circuit identifies a signal from a terminal connected to a short-range passive bus. The I-interface signal identification circuit includes a multipoint sampling pulse extraction circuit unit 1 and a violation detection unit 2
, An F-bit phase detection unit 3, a reception timing generation circuit unit 6 ', and a frame aligner 7.

In FIG. 1, a multipoint sampling pulse extracting circuit 1 receives a data frame from an I interface, and sets the signal level (1/0) of each data bit constituting the received signal data frame and its pulse width. Is detected. The violation detection unit 2 receives the output of the multipoint sampling pulse extraction circuit unit 1 as an input, and detects a frame violation of the data frame. The F-bit phase detection unit 3 receives the output of the violation detection unit 2 as an input, and detects the F-bit phase of the data frame.

[0006] The reception timing generation circuit 6 'generates a sampling clock of a fixed frequency. At this time, the reception timing generation circuit 6 ′ sets a sampling point at a fixed position based on each data bit of the transmission signal, and sets a sampling timing of the sampling clock at the sampling point. Frame aligner 7
Samples the received data frame with the sampling clock generated by the reception timing generation circuit 6 ′. As described above, in the conventional I-interface signal identification circuit, the F-bit phase detector 3 detects the phase of the received signal and determines the sampling point of the received signal data frame.

The above operation is summarized as follows.
That is, as shown in FIG. 4, the conventional I-interface signal identification circuit uses a fixed sampling method in which a sampling point is set at a fixed position based on a transmission signal data frame. At this time, the sampling point is such that eight terminals are connected to the short-range passive bus, the phase difference of the received signal data frame with respect to the transmitted signal data frame of the nearest terminal is 10 μS, and the transmission of the farthest terminal is performed. This is set on the assumption that the phase difference between the received signal data frame and the signal data frame is 14 μS. As a result, the sampling point is set at a position where the data bits of all terminals are superimposed, as shown at point a in FIG.

[0008]

By the way, the above-mentioned I
In the interface signal identification circuit, when the number of connected terminals changes, an optimum sampling margin (time interval between rising and falling of data bits and a sampling point) is always ensured for all the states. There was a problem that it could not be done.

For example, consider the case where the terminals connected to the short-range passive bus are only the terminals A and C shown in FIG. In this case, the sampling point is desirably set at an intermediate position between the phase of the received signal data frame of the terminal A and the phase of the received signal data frame of the terminal C, that is, the point b in FIG. However, as mentioned above,
The sampling point of the conventional received signal data frame is defined by a terminal having a phase of 10 μs (terminal A shown in FIG. 3) and a terminal having a phase of 14 μS
3 (terminal D shown in FIG. 3) is connected, so that even if terminal D is not connected, the sampling point is always set to terminal D
Is set to a position where sampling can be performed (point a shown in FIG. 6). Therefore, in this case, as shown in FIG.
The rear sampling margin is unnecessarily small for the data frame of the terminal A, and the front sampling margin is unnecessarily large for the data frame of the terminal C.

[0010] The present invention has been made under such a background, and regardless of the connection state of the terminal,
It is an object of the present invention to provide an I-interface signal identification circuit capable of setting a sampling point of a received signal data frame from each terminal to an optimum position for received signal data frames of all terminals. It is another object of the present invention to improve jitter tolerance and reduce data errors due to phase hits, thereby improving reliability.

[0011]

According to the first aspect of the present invention,
In an I-interface signal identification circuit for identifying a reception signal of each terminal connected to an I-interface of a basic layer DSU via a short-distance passive bus, extraction means for extracting the reception signal, and violation for detecting a violation from the reception signal Detecting means, based on the violation detection result, the phase of the F bit of the received signal from the nearest terminal that is the nearest terminal to the DSU, and the reception from the farthest terminal that is the terminal farthest from the DSU. It is characterized by comprising phase difference detecting means for detecting a phase difference from the L-bit phase of the signal, and variable means for automatically adjusting the timing of the fixed sampling clock based on the phase difference. According to a second aspect of the present invention, in the I-interface signal identification circuit according to the first aspect, the extracting means detects a signal level and a pulse width of each data bit constituting the received signal. The invention according to claim 3 is the I-interface signal identification circuit according to claim 2, wherein the violation detection means includes:
Violation of the received signal is detected based on the signal level and pulse width detected by the extracting means. The invention according to claim 4 provides the I according to claim 3
In the interface signal identification circuit, the phase difference detection means detects a change point of the F bit and a change point of the L bit in the received signal based on a detection result of the violation detection means, and determines a change point of the F bit. By detecting the change point of the F bit of the nearest terminal, the phase of the signal received from the nearest terminal is detected, and the change point of the L bit is determined as the change point of the L bit of the farthest terminal, thereby obtaining It is characterized in that the phase of the signal received from the terminal is detected, and the phase difference between the signal received from the nearest terminal and the signal received from the farthest terminal is determined. According to a fifth aspect of the present invention, in the I interface signal identification circuit according to the fourth aspect, the variable means shifts a sampling timing of the fixed sampling clock to an intermediate position of a phase difference obtained by the phase difference detecting means. It is characterized by the following.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of an I interface signal identification circuit according to an embodiment of the present invention. In this figure, parts corresponding to the respective parts in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. In the I-interface signal identification circuit shown in this figure, an L-bit phase detector 4 and a reception timing variable circuit 5 are newly provided.

Here, the L-bit phase detector 4 receives the output of the violation detector 2 as input and detects the L-bit phase of the received signal data frame. Further, the variable reception timing circuit 5 determines the phase of the received signal data frame of the nearest terminal and the farthest terminal based on the F bit and the L bit detected by the F bit phase detector 3 and the L bit phase detector 4. And adjusts the sampling timing of each terminal with respect to the received signal data frame to an intermediate position of the phase difference. Each block shown in FIG. 1 can be easily realized by a dedicated LSI such as a gate array, or a CPU (Central Processing Unit) that executes a program describing the following operation.

Next, the operation of the I interface signal identification circuit having the above configuration will be described. First, referring to FIG. 2, transmission signal data frames from each terminal connected on a short-distance passive bus are superimposed and deformed on the bus. That is, the F bit of the deformed data frame is drawn to the data frame of the nearest terminal, and the end of the L bit is drawn to the data frame of the farthest terminal.

As a result of the superimposition and transformation, the data frame is a signal that is difficult to digitally process, that is, a signal close to an analog signal. Therefore, the superimposed and transformed data frame is processed by a processing circuit (not shown) in the DSU. : Figure 1
And a digital signal which can be identified by the DSU. Further, thereby, the F bit of the data frame of the nearest terminal appears in the F bit in the data frame, and the L bit of the data frame of the farthest terminal appears in the L bit. The data frame preprocessed in this way is received by the I interface signal identification circuit shown in FIG.

The multi-point sampling pulse extraction circuit 1 generates a signal level (1/0) of each data bit constituting a received data frame (received data frame).
And its pulse width. Violation detector 2
Detects the violation based on the detection result of the multi-point sampling pulse extraction circuit unit 1, thereby detecting the frame position of the received signal data frame.

The F-bit phase detector 3 detects the F bit from the received signal data frame whose frame position has been detected by the violation detector 2, and the L-bit phase detector 4 detects the L bit from the received signal data frame. Find the bit.

The variable reception timing circuit 5 detects the phase of the received signal data frame from the closest terminal by using the detected change point of the F bit as the change point of the F bit of the closest terminal. Similarly, the variable reception timing circuit 5
Detects the phase of the received signal data frame from the farthest terminal by using the detected Lbit changing point as the Lbit changing point of the farthest terminal. Then, the variable reception timing circuit 5 sets the intermediate position of the detected phase difference between the two phases as the sampling timing of the reception signal data frame.

The reception timing generation circuit section 6 generates a fixed frequency sampling clock, and changes the sampling timing set by the reception timing variable circuit 5 to the sampling timing.
The phase of the sampling clock is shifted. The frame aligner 7 samples the reception signal data frame with the sampling clock generated by the reception timing generation circuit 6.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. Even if there is, it is included in the present invention.

[0021]

As described above, according to the present invention, it is possible to improve the jitter tolerance of the I interface signal discriminating circuit and reduce data errors due to phase hits. The reason is that, by detecting the phase of the L bit in addition to the phase of the F bit, the phase of the received signal of the nearest terminal and the phase of the received signal of the farthest terminal can be distinguished, and the received signal from the terminal is located at the optimum position. This is because sampling can be performed with

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an I interface signal identification circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a data frame according to the embodiment.

FIG. 3 is an explanatory diagram showing an example of a short passive bus connection.

FIG. 4 is an explanatory diagram showing an example of a conventional data frame.

FIG. 5 is a block diagram illustrating a configuration example of a conventional I-interface signal identification circuit.

FIG. 6 is an explanatory diagram showing an example of a conventional data frame.

[Explanation of symbols]

1. Multi-point sampling pulse extraction circuit section 2. Violation detection section 3. F-bit phase detection section 4.
... L-bit phase detector, 5... Variable reception timing circuit, 6, 6 ′... Reception timing generation circuit, 7.
Frame aligner

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-232335 (JP, A) JP-A-4-13397 (JP, A) JP-A-6-21931 (JP, A) JP-A-63-63 131743 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/02 H04L 29/10 H04M 11/00 302

Claims (3)

(57) [Claims] 1. An I-interface signal identification circuit for identifying a reception signal of each terminal connected to an I-interface of a basic layer DSU via a short-distance passive bus, comprising: extraction means for extracting the reception signal; Violation detection means for detecting
Based on the detection result, change the phase of the F bit of the received signal.
Based on the detection result of the F-bit phase detecting means for detecting , and the violation detecting means,
L-bit phase for detecting the L-bit phase of the received signal
Detecting means for detecting the phase of the detected F bit from the end closest to the DSU;
Consider the phase of the signal received from the nearest terminal
And the phase of the detected L bits is
Of the received signal from the farthest terminal which is the terminal furthest from U
By receiving the signal from the nearest terminal,
Between the phase of the signal and the phase of the signal received from the farthest terminal.
A phase difference is detected, and a fixed sampler is placed at an intermediate position of the phase difference.
To shift the sampling timing of the
Communication timing varying means.
Interface signal identification circuit. 2. The I-interface signal identification circuit according to claim 1, wherein said extraction means detects a signal level and a pulse width of each data bit constituting said reception signal. . 3. The I-interface signal identification circuit according to claim 2, wherein said violation detecting means detects violation of a received signal based on a signal level and a pulse width detected by said extracting means. I interface signal identification circuit.