JP3212869B2 - Internal clock generation circuit for synchronous semiconductor memory circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for controlling a synchronous semiconductor memory circuit device, and more particularly, to an SDRAM internal clock generation circuit.

[0001]

2. Description of the Related Art Synchronous semiconductor memory circuits (hereinafter referred to as SDRs)
AM) is synchronized with the internal clock, and data input / output is also executed in synchronization with the internal clock. Normally, in the operation of the SDRAM, the frequency of the supplied internal clock is changed according to the processing speed of an external device to which the SDRAM outputs data. For example, this is the case of continuous reading of data by a burst operation. To facilitate the change of the internal clock frequency as described above,
Conventionally, various proposals have been made.

Japanese Patent Laid-Open Publication No. Hei 6-290583 discloses an internal clock generation circuit as a "synchronous semiconductor memory", which is shown in FIG. In FIG. 8, the external clock signal CLK101 received by the first initial stage circuit 103 is controlled by an external control signal (clock enable signal) CKE102 received by the second initial stage circuit 104, and the SDRA
A clock adapted to the processing speed of the external device of M.
A clock for reducing power consumption of the AM is generated.

FIG. 9 shows a circuit diagram of the first initial stage circuit 103 and the second initial stage circuit 104. Each first-stage circuit forms a normal current mirror circuit with the P-channel transistors Q3 and Q4 and the N-channel transistors Q5 and Q6. Here, when the circuit invalid signal φe is at a high level, the P-channel transistors Q1 and Q2 are turned off, the N-channel transistor Q9 is turned on, and the output signal φout takes a low level regardless of the input signal φin. When the circuit invalidation signal φe takes a low level, the P-channel transistors Q1 and Q2 are turned on, the N-channel transistor Q9 is turned off, and the current mirror circuit is activated. The output signal φout is compared with the reference signal φr of the current mirror circuit to be opposite to the input signal φin.

FIG. 11 is a timing chart of the internal clock generation circuit shown in FIG. In the figure, φ1 is an output signal of the first initial stage circuit 103, and the external clock signal CL
Compared to K101, the signal is inverted by the first initial stage circuit 103 and is affected by a delay in circuit operation. Further, φ2 is an output signal of the second initial stage circuit 104, and compared with the external control signal CKE102, φ2 is the same as φ1.
Is inverted and delayed by the operation of the first stage circuit 104. The first control circuit 502 shown in FIG. 8 includes a D-type flip flip 502a and a D-latch 50 as shown in FIG.
2b, holds the value of the second signal φ2 at that time every time the first signal φ1 rises, starts to output the held value at the fall of the first signal φ1, and starts the next signal 1
Until the fall of the signal φ1. By the above operation, the first control circuit 502 controls the control signal φ5 shown in FIG.
4 is output.

Next, the internal clock φ56 will be described. The internal clock φ56 is output by the second control circuit 508.
Is suppressed. Therefore, the internal clock φ56, which is the output of the second control circuit 508 shown in FIG.
Is an external control signal CKE that is asynchronous with the first signal φ1.
The effect is suppressed by the low level of 102 and the clock period is lengthened. However, the current mirror circuits of the first and second first-stage circuits as shown in FIG. 9 are high-speed and small-amplification signal input circuits, but have a drawback of large power consumption.

Here, Japanese Patent Application Laid-Open No. 7-65574 discloses a "first stage circuit system for semiconductor memory". This internal clock generation circuit invalidates the first stage circuit of the current mirror circuit together with the high level of the circuit invalidation signal φ9 in FIG. The CMOS type first-stage circuit is intended to reduce power consumption by suspending the SDRAM during mode switching such as control of a self-refresh mode.

[0007]

Recently, SDRAMs have been developed.
At the same time, the processing speed required of the system is increasing, and the system clock frequency and the processing speed of peripheral circuits are also increasing. In such an environment, the external clock signal CLK10
The relative delay between 1 and the internal clock φ56 causes a problem during high-speed processing (for example, reading data from SDRAM).

[0008] In order to solve this problem, there is a method of advancing the phase of the internal clock with respect to the external clock. FIG.
1 shows a conventional internal clock generation circuit which advances the phase of an internal clock from an external clock. In FIG. 12, CL
K101 is an external clock, CKE102 is an external control signal, 103 and 104 are first and second first-stage circuits, respectively, 502 and 508 are first and second circuits, respectively.
The control circuits are the same as those shown in FIG.

The timing correction circuit 106 shown in FIG. 12 is constituted by, for example, a PLL (phase-locked loop) circuit. This circuit is ISSCC96 / SESSION23 / DRAM by Saeki et al.
/ PAPER SP 23.4, February 1996, "A 2.5ns Clock Acce
ss 250MHz 256Mb SDRAM witha Synchronous Mirror Del
ay ". This circuit is used when a continuous clock signal is not available and provides a third signal φ3 that is ahead of the first signal φ1.
2 shows a timing chart of each signal. Here, the first signal φ1, the second signal φ2, and the control signal φ54 are the same as those in FIG. The phase of the timing correction signal φ3 is ahead of the first signal φ1.

The second control circuit 508 outputs the timing correction signal φ3 as an internal clock φ86 whose phase is advanced, but suppresses the timing correction signal φ3 during the high level of the control signal φ54. However, the timing correction signal φ
When the phase of the third control circuit is advanced by more than π, the second control circuit 5
08, that is, the internal clock φ86 is
However, there is a danger that the operation of the circuit will be problematic due to the narrow rectangular wave.

[0011]

SUMMARY OF THE INVENTION The main object of the present invention is to provide:
An object of the present invention is to provide an internal clock generation circuit for an SDRAM that generates an internal clock with an advanced phase, which can be stably controlled by an asynchronous external control signal. as a result,
It is possible to easily obtain an SDRAM for a system having a high processing speed without causing a problem in circuit operation.

[0012] To this end, the present invention relates to a first clock receiving an external clock signal and synchronizing with the external clock signal.
A first initial stage circuit that generates an external control signal and a second initial stage circuit that generates a second signal synchronized with the external control signal; and a first initial stage circuit that receives the first signal and outputs the first signal.
Time signal for generating a third signal whose phase is advanced from that of the first signal
And ring correction circuit, a first control circuit the first signal and the second signal to generate a fourth signal is input, the first
1 signal and the fourth signal are input to the first internal clock.
A second control circuit that generates a clock, and a second internal clock that is input with the third signal and the fourth signal and that is advanced in phase from the first internal clock. An internal clock generation circuit for a synchronous semiconductor memory circuit device having a third control circuit, wherein the first control circuit includes a D-type flip-flop.
The first signal is connected to the clock terminal
The second signal is input to the D terminal and the fourth signal is input to the D terminal.
A signal is output from a Q terminal, and the second and third control circuits
The first or third signal is input to one end and the fourth signal is
A NOR circuit which is inputted a signal at the other end, the input and output
RS comprising first and second NAND circuits cross-connected
A latch circuit, and an output from the first NAND circuit
And an inverter for outputting the first or second internal clock.
And the first or third signal is the RS latch.
Input to the first NAND circuit serving as a set terminal of the switch circuit.
And the output of the OR circuit including the NOR circuit is
The RS latch circuit is delayed with respect to the first or third signal.
Input to the second NAND circuit serving as a glue set terminal.
Characterized in that that.

Further, in addition to the above-described internal clock generation circuit for the SDRAM, an external clock signal is input to generate a first signal synchronized with the external clock signal in order to reduce power consumption of the SDRAM. A first-stage circuit, a second first-stage circuit that receives an external control signal and generates a second signal synchronized with the external control signal, and receives the external clock signal and a power reduction signal and synchronizes with the external clock signal. A third first-stage circuit that generates a third signal, a first control circuit that receives the first signal and the second signal and generates a control signal, a first control circuit that generates the control signal, a second control circuit signal to generate a fourth signal is input, a third control circuit that the third signal and the fourth signal to generate a fifth signal is input, the fifth When a signal is A timing correction circuit for generating a timing correction signal having a phase advanced from the fifth signal, a selection circuit receiving a selection signal, selecting one of the fifth signal and the timing correction signal, and outputting the selected signal as a timing signal; Receiving the first signal and the control signal,
A fourth control circuit for generating an internal clock of
Input signal, the fourth signal, and the control signal.
Fifth control for generating a second internal clock with advanced phase
Circuit for a synchronous semiconductor memory circuit device having a circuit
In the clock generation circuit, the first and second control circuits
And the first signal is a clock signal.
The second or the power reduction signal input to the
And the fourth or the control signal is output from the Q terminal.
And the third and fourth control circuits are connected to the third or fourth control circuit.
One signal is input to one end and the fourth signal or the control
A NOR circuit, which receives a signal at the other end, and its output and input
A first R including first and second NAND circuits connected in a differential manner;
An S latch circuit and an output of the first NAND circuit are input.
And then outputs the fifth signal or the first internal clock
And a first inverter, wherein the first or third signal is
The first NAN serving as a set terminal of the RS latch circuit
D input to the D circuit and including the NOR circuit
The output of the R circuit is delayed before the first or third signal and
The second RS, which is to be a set terminal of the first RS latch circuit.
Input to an AND circuit, and the fifth control circuit
4. 3-input N to which a control signal and a timing signal are input
An OR circuit, and third and fourth circuits whose outputs and inputs are cross-connected.
A second RS latch circuit comprising a NAND circuit;
The output of the NAND circuit of FIG.
A second inverter for outputting a clock.
Before the switching signal becomes the set terminal of the second RS latch circuit
The three-input NOR circuit,
The output of the OR circuit comprising
Becomes a reset terminal of the second RS latch circuit with a delay
The selection signal is input to the fourth NAND circuit, and
In the state of the above, the timing correction signal is selected and
The second internal clock having a phase advanced from the first internal clock.
Locked and when the selection signal is in the second state,
A fifth signal is selected and has the same level as the first internal clock.
The second internal clock of the phase .

[0014]

FIG. 1 shows a first embodiment of the present invention.
Shown in First and second internal clock generation circuits of FIG.
First stage circuits 103 and 104 and the timing correction circuit 10
6 are the same as those in FIG. The external clock signal CLK101 and the external control signal CKE102
The generated first signal φ1, second signal φ2, and timing correction signal φ3 are the same as those in FIG.

The first control circuit 105 is constituted by the D-type flip-flop shown in FIG. 2, and holds the value of the second signal every time the first signal rises, and the next rise of the first signal. Until the control signal φ as shown in FIG.
4 is output.

Second control circuit 107 and third control circuit 1
08 is shown in FIG. This is because the first signal φ1 (or the timing correction signal φ3) and the control signal φ4 are input to the OR.
Circuit 201 and the first signal φ1 (φ3)
It comprises an RS flip-flop 202 that is reset by the output signal of the R circuit. Therefore, when control signal φ4 is at a low level, this control circuit is not affected. When the control signal φ4 is at the high level, the output signal of the OR circuit 201 is maintained at the high level regardless of the level of the first signal φ1 (φ3), so that the RS flip-flop is suppressed from being set, and Clock φ5 (φ
In 6), the low level is maintained. Here, since the OR terminal 201 is connected to the reset terminal, the arrival of the signal is slightly delayed from the set terminal of the RS flip-flop 202. Therefore, compared with the rise and fall of the first signal φ1 (φ3), The first internal clock φ5 (or the second internal clock φ6), which is the output signal of the flip-flop, is slightly delayed.

FIG. 4 shows a timing chart of the circuit diagram of FIG. The rise of the control signal φ4 coincides with the rise of the first signal φ1, and the fall of the control signal φ4 coincides with the rise of the next first signal φ1. The level of the control signal φ4 reflects the level of the second signal φ2 when the first signal φ1 rises.

The second control circuit 107 generates a first internal clock φ5 from the first signal φ1 and the control signal φ4. Further, the third control circuit 108 controls the timing correction signal φ
3 and a control signal φ4 to generate a second internal clock φ6. Referring to FIG. 4, the phase of the second internal clock φ6 is ahead of the phase of the first internal clock φ5, for example, in order to synchronize with the output timing of data reading of the SDRAM.

Next, a second embodiment of the present invention is shown in FIG. In FIG. 5, a selection signal φ11 selects a second internal clock φ16 and a power reduction signal φ8 for suppressing the second internal clock φ16 when it is not required.

FIG. 7 is a timing chart of the circuit of FIG. The first and second first-stage circuits 103 and 104 and the first and second control circuits 105 and 107 are respectively shown in FIG.
And a first signal φ similar to that of FIG.
1, a second signal φ2 and a control signal φ4 are generated from an external clock signal CLK101 and an external control signal CKE102.

The third initial stage circuit 113 outputs a circuit invalid signal φ
The power reduction signal φ8 is input as e (see FIG. 9).
Therefore, power reduction signal φ8 is applied to external clock signal CLK.
The waveform of the output signal φ7 of the third initial stage circuit 113 may be as dangerous as the internal clock φ86 of FIG. 13, as shown by φ7 in FIG. However, this waveform is
5 (see FIG. 3).

The fourth control circuit 119 is the first control circuit 1
As in FIG. 05, it is configured by a D-type flip-flop as shown in FIG. To the fourth control circuit 119, a power reduction signal φ8 is supplied to a data input terminal, and a first signal φ1 is supplied to a clock input terminal. This output signal φ
9, as shown in FIG. 7, the value of the power reduction signal φ8 at the time of the rising of the first signal φ1 is held and output until the next rising of the first signal φ1.

The waveform of the output signal φ10 of the fifth control circuit 115 is shown as φ10 in FIG. Timing correction circuit 10
Numeral 6 advances the phase of the output signal φ10 of the fifth control circuit 115 to generate the timing correction signal φ12.

The selection circuit 117 selects the output signal φ10 of the fifth control circuit 115 or the timing correction signal φ12 according to the selection signal φ11, and supplies the same to the sixth control circuit 118 as the timing signal φ13. The sixth control circuit 118 has a three-input O at a reset terminal as shown in FIG.
It is composed of an RS flip-flop 202 to which the output of the R circuit 203 is supplied. The timing signal φ1 shown in FIG.
3, the control signal φ4, and the second internal clock φ16 generated from the output signal φ9 of the fourth control circuit 119,
A signal asynchronous with the external clock, that is, the external control signal C
Even if control is performed by the KE 102, the power reduction signal φ8, and the selection signal φ11, a waveform that does not cause a danger to the circuit operation is obtained.

In the selection circuit 117, when the selection signal φ11 goes high, the timing correction signal φ12 is selected and output as the timing signal φ13, so that the phase of the second internal clock φ16 is as shown in FIG. I'm advancing. In this case, when the internal clock whose phase is advanced does not match the external device, the output signal φ10 of the fifth control circuit 115 is selected by setting the selection signal φ11 to the low level, and is output as the timing signal φ13. At this time, the second internal clock φ16 returns to the phase of the first internal clock φ5.

When the second internal clock φ16 is not necessary, for example, while the SDRAM is controlled by the external control signal CKE102 to output data to a slow external device, the power reduction signal φ8 is at a high level. As a result, the current mirror circuit of the third initial stage circuit 113 is invalidated, and the power consumption is reduced.

[0027]

As described above, from the internal clock generation circuit of the first embodiment, the SDR having no problem in the circuit operation can be obtained.
A circuit for supplying an advanced phase internal clock for AM is easily obtained. Further, the internal clock generation circuit of the second embodiment can generate not only the internal clock with the advanced phase in addition to the conventional internal clock but also the internal clock by controlling the internal clock with the external control signal and the power reduction signal. This has the effect of lengthening the clock period. As a result, an SDRAM with reduced power consumption for a high-speed processing system can be easily obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment.

FIG. 2 is a circuit diagram of a D-type flip-flop.

FIG. 3 is a circuit diagram of an RS flip-flop;

FIG. 4 is a timing chart of the circuit of FIG. 1;

FIG. 5 is a circuit diagram according to a second embodiment;

6 is a circuit diagram of a control circuit 118 of the circuit of FIG.

FIG. 7 is a timing chart of the circuit of FIG. 5;

FIG. 8 is a circuit diagram of a conventional example.

FIG. 9 is a circuit diagram of a first-stage circuit.

FIG. 10 is a circuit diagram of the control circuit of FIG. 8;

FIG. 11 is a timing chart of the circuit of FIG. 8;

FIG. 12 is a circuit diagram of another conventional example.

13 is a timing chart of the circuit in FIG.

[Explanation of symbols]

CLK101 External clock signal CKE102 External control signal (clock enable signal) 103 First first-stage circuit 104 Second first-stage circuit 105 First control circuit 106 Timing correction circuit 107 Second control circuit 108 Third control circuit 113 Third First stage circuit 115 Fifth control circuit 117 Selection circuit 118 Sixth control circuit 119 Fourth control circuit 201 OR circuit 202 RS flip-flop 203 Three-input OR circuit 502 Conventional first control circuit 502a D-type flip-flop 502b D-type latch circuit 508 Conventional second control circuit φ1 first signal φ2 second signal φ3 timing correction signal φ4 control signal φ5 first internal clock φ6 second internal clock φ7 output signal of third initial stage circuit φ8 Power reduction signal φ9 Output signal of fourth control circuit φ10 Output signal of the fifth control circuit φ11 selection signal φ12 timing correction signal φ13 timing signal φ16 second internal clock φ54 conventional control signal φ56 conventional internal clock φ86 conventional internal clock φe circuit invalid signal φr reference signal φin Input signal of first-stage circuit φout Output signal of first-stage circuit

Claims (2)

(57) [Claims] An external clock signal is input to the external clock signal.
A first first-stage circuit for generating a first signal synchronized with a clock signal
And an external control signal are input and synchronized with the external control signal
A second first-stage circuit for generating a second signal,The first
Of the third signal whose phase is advanced from that of the first signal.
A timing correction circuit for generating a signal ofThe first message
Signal and the second signalFourthThe first to generate a signal
1 control circuit;The first signal and the fourth signal are input and a first internal
A second control circuit from which a clock is generated; The third Signal and saidFourthSignal is inputThe first
From internal clockAdvanced phaseSecondGenerate internal clock
The first3Synchronous semiconductor memory circuit having a control circuit
In the device internal clock generation circuit,The first control circuit includes a D-type flip-flop.
The first signal is input to a clock terminal and the second signal is
The signal is input to the D terminal and the fourth signal is output from the Q terminal.
Force, The second and third control circuits are configured to control the first or third signal.
N is input to one end and the fourth signal is input to the other end.
An OR circuit, First and second NAND circuits whose outputs and inputs are cross-connected
An RS latch circuit comprising: The output of the first NAND circuit is used as an input and the first or
An inverter that outputs a second internal clock; The first or third signal is set in the RS latch circuit.
Input to the first NAND circuit serving as a terminal, The output of the OR circuit including the NOR circuit is the first circuit.
Or, with a delay from the third signal, the RS latch circuit
Input to the second NAND circuit serving as a reset terminal. thing
Internal clock for synchronous semiconductor memory circuit device characterized by the following:
Generation circuit. 2. A first initial stage circuit which receives an external clock signal and generates a first signal synchronized with the external clock signal, and a second signal which receives an external control signal and is synchronized with the external control signal. A second first-stage circuit for generating; a third first-stage circuit for receiving the external clock signal and the power reduction signal and generating a third signal synchronized with the external clock signal; and the first signal and the second signal. A first control circuit that receives the first signal and generates a control signal; a second control circuit that receives the first signal and the power reduction signal and generates a fourth signal; A third control circuit that receives the fourth signal and generates a fifth signal, a timing correction circuit that receives the fifth signal and generates a timing correction signal whose phase is advanced from the fifth signal, Before the selection signal is input Fifth signal selecting circuit and said first signal and said control signal is inputted first internal click output as selecting one timing signal of the timing correction signal
A fourth control circuit for generating a lock, wherein the timing signal, the fourth signal, and the control signal are
A second internal clock for generating a second internal clock having an input and advanced phase
For a synchronous semiconductor memory circuit device comprising
In the unit clock generation circuit, the first and second control circuits are D-type flip-flops.
The first signal is input to a clock terminal and
The second or the power reduction signal is input to a D terminal and the fourth or
Alternatively, the control signal is output from a Q terminal, and the third and fourth control circuits output the third or first signal.
Is input to one end and the fourth signal or the control signal is
NOR circuit input to the end, and first and second NAND circuits whose outputs and inputs are cross-connected
A first RS latch circuit comprising: an output of said first NAND circuit;
First inverter for outputting a signal or a first internal clock
And wherein the first or third signal is set in the RS latch circuit.
The input to the first NAND circuit serving as a terminal, and the output of a first OR circuit including the NOR circuit is
The first RS latch circuit is delayed from the first or third signal.
A signal input to the second NAND circuit serving as a roadside set terminal
And the fifth control circuit is configured to control the fourth control signal and the
-Input NOR circuit to which an input signal is input, and third and fourth NAND circuits whose outputs and inputs are cross-connected
And an output of the third NAND circuit and an input of the second
And a second inverter for outputting a partial clock, wherein the timing signal is set in the second RS latch circuit.
Input to the third NAND circuit serving as a terminal, and the output of an OR circuit including the three-input NOR circuit is
The second RS latch circuit delayed from the timing signal.
An input to the fourth NAND circuit serving as a glue set terminal
It is, when the selection signal is in the first state, the timing correction
A signal is selected and the phase is advanced from the first internal clock.
The second internal clock, and when the selection signal is in the second state, the fifth signal is selected.
The second internal clock having the same phase as the first internal clock.
Internal clock generation circuit for a synchronous semiconductor memory circuit device characterized by comprising an internal clock.