JP3211519B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus in which data of a plurality of pixels is input in units of one block, and which can handle image data in units of pixels.

[0002]

2. Description of the Related Art In recent years, image processing technology has been actively developed. In an image processing apparatus such as a digital copying machine, an original image is read and only an image in a desired area in the original image is extracted. Various editing processes such as a shift process for moving an image in a desired area are possible.

On the other hand, when handling image data, image data of a predetermined number of bits is handled in units of one block. For example, Japanese Patent Laying-Open No. 4-301687 discloses an image processing apparatus for inputting a plurality of image data in units of one block. According to this, the data of one block as a unit of writing / reading is stored in the frame buffer, and a barrel shifter capable of cyclically shifting in units of one pixel as a display unit, and image data on the shifted barrel shifter are stored in the frame buffer. Since a write control circuit is provided for controlling writing to be prohibited or valid for each pixel at the time of writing, valid data after shifting can be written to the frame buffer.

As described above, by handling a plurality of image data in units of one block, the time required for various editing processes can be reduced.

[0005]

However, in the technique disclosed in Japanese Patent Application Laid-Open No. 4-301687, if the number of gradation bits constituting one pixel of the image data is fixed, the image data is reduced to one. Although it can be handled in pixel units, it cannot handle the case where the number of gradation bits is variably input. The reason is that even if the pixel is shifted by the same pixel, the shift amount differs depending on the number of grayscale bits forming one pixel. Accordingly, it is difficult to perform processing such as area extraction or area shift of image data.

The present invention has been made to solve the above problem, and even when there are a plurality of types of gradation bits per pixel of image data, the image data is set according to each gradation bit number. It is an object of the present invention to provide an image processing apparatus capable of performing a predetermined process on a region that has been set.

[0007]

In order to achieve the above object, an image processing apparatus according to claim 1 converts pixel data into M
An image processing apparatus that performs processing on a block-by-bit basis, wherein the number of grayscale bits per pixel N (where N is a divisor of M), the position of the first pixel in the scanning direction of the region to be processed, and Based on the M bits per block,
A calculating unit for calculating a first block to be processed and a first bit to be processed in the block; the first block calculated by the calculating unit; and a block subsequent to the first block, the calculating unit A reading means for sequentially reading out the calculated first bits in block units of M bits.

[0008] The image processing apparatus according to the second aspect is the first aspect.
In the image processing device described in the above, the calculating means is configured to execute a process based on a position of a trailing pixel in a scanning direction of an area where the process is performed, the gradation bit number N and the block unit M bit. , And the reading means performs reading until the image data of the last block is read. According to a third aspect of the present invention, in the image processing apparatus according to the first aspect, a barrel shifter that reads image data in units of M bits and cyclically shifts by a designated number of bits, and latches the image data cyclically shifted by the barrel shifter Latching means, image data cyclically shifted by the barrel shifter, and image data adjacent to the image data and latched by the latching means,
Selecting means for selecting continuous M-bit image data;
The arithmetic means gives the number of bits to be cyclically shifted to the barrel shifter based on the position of the first bit to be processed in the first block, and selects M bits of image data from the first bit to the selecting means. And providing control information for performing the operation.

[0009]

The operation of the image processing apparatus according to the first aspect is as follows. The arithmetic means is the number of gradation bits N per pixel
(Where N is a divisor of M), the position of the head pixel in the scanning direction of the area to be processed, and the M bits in the block unit, the head block to be processed and the processing in the block. The reading means calculates the head block calculated by the calculating means and the block subsequent to the head block from the starting bit calculated by the calculating means in units of M bits. To read sequentially. Therefore, even if the number of gradation bits of one pixel of the image data is different, the image data can be read out by the single image processing device from the first pixel of the area to be processed for every M bits which is a block unit. . According to the image processing apparatus of the second aspect, the calculating means further calculates the position of the trailing pixel in the scanning direction of the region to be processed, the number of gradation bits N, and the M bits of the block unit. Based on this, the last block to be processed is calculated, and the reading means performs reading until the image data of the last block is read. Therefore, even if the number of gradation bits of one pixel of the image data is different, the image data from the head pixel of the area to be processed to the last block to be processed can be read in M-bit block units.

According to the third aspect of the present invention, the barrel shifter reads the image data in units of M-bit blocks, and cyclically shifts the image data by a designated number of bits. The image data cyclically shifted by the barrel shifter is latched by latch means. Then, the selection unit is configured to generate a continuous M from the image data cyclically shifted by the barrel shifter and the image data adjacent to the image data and latched by the latch unit.
Select bit image data.

The arithmetic means gives the number of bits to be cyclically shifted to the barrel shifter based on the position of the first bit to be processed in the first block, and provides the selecting means with M bits of image data from the first bit. Give control information for selecting. Therefore,
In the image processing apparatus according to the third aspect, even if the number of gradation bits forming one pixel of the image data is variable, one circuit configuration performs predetermined processing according to the plurality of gradation bit numbers. In addition, the shift processing and the extraction processing of the image data can be performed with a simple configuration, and the predetermined processing can be efficiently performed even when the write and read block sizes are different.

[0012]

Embodiments will be described below with reference to the drawings.
FIG. 1 is a diagram showing the configuration of an embodiment of an image processing apparatus according to the present invention. In the figure, 1 is a barrel shifter, 2 and 3 are latches, 4 is a data selector, 5 is an image control unit, and 6 is an arithmetic unit. Is shown. In FIG. 1, broken lines indicate the flow of parameter setting values or various control signals, and solid lines indicate the flow of image data.

In FIG. 1, M-bit data is input to a barrel shifter 1 in parallel. The operation mode is controlled by a mode setting signal, and the shift amount is controlled by a shift position control parameter provided from the arithmetic unit 6. In addition,
In the following, shift and extraction will be described as operation modes, but it goes without saying that the present invention can be applied to other image editing.

In the configuration shown in FIG. 1, it will be apparent from the later description that the extraction processing and the shift processing are performed only in the main scanning direction of image reading, but other processing is performed in the sub scanning direction orthogonal to the main scanning direction. It is also possible to operate the configuration shown in FIG. 1 only within the range of the set area in the sub-scanning direction.

Therefore, when the shift processing is performed using the image processing apparatus shown in FIG. 1, a shift mode setting signal is provided as the mode setting signal, and when the extraction processing is performed, the extraction mode setting signal is provided. The barrel shifter 1 is fixedly operated in the left rotation mode when the extraction mode is set by the mode setting signal, and is fixedly operated in the right rotation mode when the shift mode is set. ing.

In the left rotation mode, as shown in FIG. 2, when M = 8 bits and shift by 2 bits is designated by the shift position control parameter, V is sequentially set from the most significant bit (MSB).
D7, VD6, VD5, VD4, VD3, VD2, VD
1, VD0 and the barrel shifter 1, the data is cyclically shifted to the left, and VD5, VD4, VD
3, VD2, VD1, VD0, VD7, and VD6.

FIG. 3 shows the right rotation mode.
As shown in the figure, when M = 8 bits and the shift position control parameter specifies to shift by 2 bits, VD7, VD
6, VD5, VD4, VD3, VD2, VD1, VD0
Is input to the barrel shifter 1 and then cyclically shifted to the right, and VD1, VD0, VD7, VD6,
In this mode, VD5, VD4, VD3, and VD2 are output.

The latch 3 is an M-bit latch, and latches an output from the barrel shifter 1 by a latch clock generated by the image control unit 5. The latch 2 is an M-bit latch, and latches output data of the latch 3 by a latch clock generated by the image control unit 5 and delayed by one stage from the latch clock of the latch 3 by the operation clock.

The data selector 4 includes M selectors. FIG. 4 shows an example of the configuration. FIG. 4 is a diagram showing a configuration example in the case of M = 8 bits. When the shift position control parameter specifies that a 4-bit shift is performed, the barrel shifter 1
VD3 _n , VD2 _n , VD1 _n , VD0 _n , VD7 _n ,
Assuming that 8-bit image data of VD6 _n , VD5 _n , and VD4 _n has been written, the latch 3 stores VD3 _n−1 , VD2 _n−1 , VD1 _n−1 , VD0 of the previous block.
_n-1 , VD7 _n-1 , VD6 _n-1 , VD5 _n-1 , VD4
_{The n-1} 8-bit image data is written, and the latch 2 further stores VD3 _n-2 and VD2 of the previous block.
_n-2 , VD1 _n-2 , VD0 _n-2 , VD7 _n-2 , VD6
8-bit image data of _n-2 , VD5 _n-2 and VD4 _n-2 are written. Then, the data selector 4 sets S0
To S7, and the selector S7 is composed of VD3 _n-2 which is the MSB of the latch 2 and MSB of the latch 3.
VD3 _n-1 is selected and output. The same applies to the following, and the selector 0 selects and outputs either the least significant bit (LSB) of the latch ₂ VD4 _n-2 or the LSB of the latch 3 VD4 _n-1 .

Whether each selector selects the data of the latch 2 or the data of the latch 3 is determined by a data select signal provided from the image control unit 5. For example, in FIG. 4, assume that the upper 4 bits are selected from the latch 2 and the lower 4 bits are selected from the latch 3 by the data select signal.
As shown in the figure, the data selector 4 outputs VD3 _n-2 ,
VD2 _n-2 , VD1 _n-2 , VD0 _n-2 , VD7 _n-1 , V
Eight bits of D6 _n−1 , VD5 _n−1 and VD4 _n−1 will be output. It is clear that these 8 bits are data of continuous pixels in the main scanning direction.

The arithmetic section 6 shifts the barrel shifter 1 based on an area designation parameter for designating an area in the main scanning direction in which the extraction processing or the shift processing is performed and a gradation bit number parameter indicating the number of gradation bits of one pixel. The control parameter, the data select signal for the data selector 4, and the number of blocks for generating the latch clocks of the latches 2 and 3 are calculated. Note that the region from which the image is extracted or the region to be shifted may be specified by the user on the coordinates of the document image or may be surrounded by a marker color of a predetermined color. Part 6
Is a parameter for designating a region to be extracted or a region to be shifted. More specifically, when performing the extraction process, the number of pixels from which to extract in the main scanning direction, the position of the first pixel in the line direction of the area, and the position of the last pixel are input. I do. The same applies to the case where a shift process is performed.

The image control unit 5 generates a latch clock based on the data area parameters calculated by the calculation unit 6, that is, a parameter for specifying a head pixel to be processed and a parameter for specifying a tail pixel.

Next, the operation when the extraction is performed with M = 8 will be described. First, a parameter for designating the first pixel and the last pixel to be extracted and the number of gradation bits of one pixel are input to the arithmetic unit 6 as parameters. For example,
As shown in FIG. 5, it is assumed that the pixels from the m-th pixel to the n-th pixel are to be extracted. M is input as the first pixel to be extracted, n is input as the last pixel, and one pixel is 4 as the gradation bit number parameter. A parameter corresponding to indicating 2 bits is input for gray scale, a parameter corresponding to 2 tones per pixel, that is, a bit corresponding to 1 bit is displayed for black and white, and 4 bits is displayed for 16 gray levels per pixel. A parameter corresponding to that is input, and a parameter corresponding to indicating 8 bits for 256 gradations per pixel. That is, a parameter is made to correspond to each gradation bit number. Note that the number of gradation bits needs to be a divisor of the number of bits in one block.

The operation of the arithmetic unit 6 will be described with reference to FIG. The operation unit 6 generates a shift position control parameter indicating the shift amount of the barrel shifter 1 and a signal specifying a head block to be extracted and a tail block to be extracted. The first block and the last block are as follows. 8-bit data is input to the barrel shifter 1 in parallel. This is one block. When processing is performed in units of blocks as described above, FIG.
Is taken as an example, the data from the first pixel to the (m-1) th pixel can be ignored and the data from the mth pixel to the nth pixel can be extracted. It becomes a problem how many blocks from the top of the line are included in the line, and how many blocks the nth pixel is included in the line. These are designated by the first block designating signal and the last block designating signal.

The calculation section 6 first performs the calculation in step S1. Here, an operation of subtracting 1 ₁₆ from the input head pixel designation parameter is performed. However, when the number of gray scale bits is 8, this calculation is not performed. In addition,
The number with the subscript 16 indicates a hexadecimal number. Hereinafter, the same applies.

Next, at step 2, a shift position control parameter is generated based on the calculation result at step 1. Here, when the gradation bit number is 8 bits, “000” is fixedly output. This means that the shift amount is 0, that is, the bit shift is not performed in the barrel shifter 1. In this case, since the 8-bit data taken in the barrel shifter 1 is the data of one pixel as it is, the bit taken in the barrel shifter 1 Need not be shifted. Note that the values shown in angle brackets are binary values. Hereinafter, the same applies.

However, when the number of gradation bits is four, "0" is added to the least significant bit of the operation result in step S1.
"0" is added as a shift position control parameter, and when the number of gradation bits is 2 bits, "0" is added to the lower 2 bits of the calculation result of step S1 and output as a shift position control parameter.
If the number of gradation bits is one, the lower three bits of the calculation result of step S1 are output as the shift position control parameter without any change.

In steps S3 and S4, a leading block value and a trailing block value to be extracted used when generating the latch clock are calculated. Hereinafter, this calculation will be described.

First, when the number of gradation bits is 8, steps S3 and S4 are skipped. Therefore, in this case, assuming that the pixels from the m-th pixel to the n-th pixel are to be extracted, the extracted start block value is m and the extracted tail block value is n.

Next, when the number of gradation bits is four, the calculation result of step S1 and the extracted tail pixel designation parameter are each divided by 2 ₁₀ in step S3. That is, it is divided by the number of pixels per 8 bits, which is an input unit. The suffix 10 indicates a decimal number. Hereinafter, the same applies. The division can be performed by shifting each parameter right by one bit. Then, the value obtained by shifting the operation result of step S1 right by one bit in step S3 is 1 in step S4.
₁₆ is added and output as an extracted head block value. The value of the extracted tail pixel designation parameter shifted right by one bit in step S3 is output as is as the extracted tail block value. Specifically, for example, as shown in FIG. 7A,
If the fourth to seventh pixels are to be extracted, the calculation result of step S1 is "11", so that the shift position control parameter is "1". Since this value directly means shifting by one pixel, this causes the barrel shifter 1 to shift by 4 bits in this case. In addition, it is found that the extracted first block value is “10”, and the fourth pixel is included in the second block, and the extracted tail block value is “11”, which is 3
It will be extracted up to the block. Therefore, in this case, up to the sixth pixel is extracted, and the seventh pixel is not extracted.

Next, a case where the number of gradation bits is 2 will be described. The calculation result of step S1 and the extracted tail pixel designation parameter are 4 _{10 in} step S3, respectively.
Divided by This division can be performed by shifting each parameter to the right by 2 bits. Then, in step S4, 1 ₁₆ is added to the value obtained by shifting the operation result of step S1 to the right by 2 bits in step S3, and the result is output as an extraction head block value. The extracted value is output as it is as the extracted tail block value. More specifically, for example, as shown in FIG. 7B, if the fourth pixel to the eighth pixel are to be extracted, the calculation result of step S1 is “11”, so the shift position control parameter is “11”. . Since this value is directly shifted by three pixels, this causes the barrel shifter 1 to shift by 6 bits in this case. In addition, the extracted top block value is “1”, and the fourth pixel is found to be in the first block. The extracted tail block value is “10”, and the second block is extracted. Therefore, in this case, 4
The blocks from the block to the eighth block are extracted as set.

Next, a case where the number of gradation bits is 1 will be described. The calculation result of step S1 and the extracted tail pixel designation parameter are 8 _{10 in} step S3, respectively.
Divided by This division can be performed by shifting each parameter to the right by 3 bits. Then, in step S4, 1 ₁₆ is added to the value obtained by shifting the operation result of step S1 to the right by 3 bits in step S3, and the result is output as an extraction head block value. The extracted value is output as it is as the extracted tail block value. More specifically, for example, as shown in FIG. 7C, if the pixels from the 11th pixel to the 25th pixel are to be extracted, the calculation result of step S1 is “010”, so the shift position control parameter is “10”. Become. Since this value directly means shifting by two pixels, this causes the barrel shifter 1 to shift by two bits in this case. Also, it is found that the extracted top block value is “10” and the eleventh pixel is included in the second block, and the tail block value after extraction is “11”, and the third block is extracted. In this case 2
The fifth pixel is in the fourth block, but up to the third block, that is, up to the 24th pixel is extracted.

FIGS. 8, 9 and 1 summarize the above.
0. 8, 9, and 10 are diagrams showing the relationship among the lower 3 bits of the extraction head pixel designation parameter, the shift position control parameter at that time, and the corresponding shift amount, and FIG. FIG. 9 shows a case where the number of bits is 4 bits, FIG. 9 shows a case where the number of gradation bits is 2 bits, and FIG. 10 shows a case where the number of gradation bits is 1 bit. 8 and 9, “−” of the extraction head pixel designation parameter indicates 0 or 1.

The calculating section 6 generates a data select signal based on the shift position control parameter value. Specifically, the shift amount of the barrel shifter 1 is k (0
≤ k ≤ 8 bits, the upper k bits are selected from the latch 2 and the lower (8-
k) A data select signal indicating that a bit is to be selected is generated and supplied to the selector 4 which has generated the data select signal. Therefore, when the number of gradation bits is one, the data select signal is as shown in FIG. In the figure, “0” indicates the latch 2
Output from the latch 3
Means to select and output.

This is schematically shown in the case of FIG. 7C as follows. In this case, since the shift amount is 2 bits, the data written in the barrel shifter 1, the latch 2, and the latch 3 are as shown in FIG. The numbers in the figure indicate the numbers of the pixels. In this case, the second block and the third block are extracted as described above, and thereafter, the barrel shifter 1 is reset. In this case, since the shift position control parameter is "010", the data select signal is "00000011". Therefore, FIG.
In the case of 2, the data of the 11th pixel to the 18th pixel is output from the data selector 4, and the data of the 19th to 24th pixels is output at the next timing.

FIG. 13 is a diagram showing the timing of various signals. The latch 2 clock and the latch 3 clock are used by the image control unit 5 to store data at another location, a data transfer clock input from a CPU (not shown), and an extracted head block value and an extracted tail block value input from the arithmetic unit 6. It is generated based on this. The latch clock of the latch 2 has a timing delayed by one clock from the latch clock of the latch 3 by the operation clock. Further, the image control unit 5 generates an effective area signal based on the generated latch clock. This valid area signal is a signal that is valid only during a period in which the latch clock is generated.

Therefore, the latch output is gated by the effective area signal, a signal obtained by delaying the latch clock by one clock with the operation clock is used as a transfer clock to the next stage, and data is taken in at the rise of this signal. Extraction processing can be realized. In addition,
FIG. 13 shows a case where four blocks are extracted.

The case of extraction has been described above. Next, the case of shift will be described. In this case, the barrel shifter 1 performs a right rotation, the area specification parameters become the shift first pixel specification parameter and the shift tail pixel specification parameter, and each line of the area in the set sub-scanning direction is shifted from the first pixel. The process is the same as the above-described extraction except that the so-called white insertion process in which the value of all white is written to the barrel shifter 1 up to the first pixel, and that the data select signal is different.

That is, the operation performed by the operation unit 6 is the same as that in the above-described extraction. Therefore, the relationship among the lower 3 bits of the shift area head pixel designation parameter, the shift position control parameter, and the shift amount is as follows. FIG.
4, FIG. 15 and FIG. 16, which are shown in FIG.
This is the same as the relationship among the lower 3 bits of the extraction head pixel designation parameter, the shift position control parameter, and the shift amount shown in FIGS. 14 shows the case where the number of gradation bits is 4 bits, FIG. 15 shows the case where the number of gradation bits is 2 bits, and FIG. 16 shows the case where the number of gradation bits is 1
Indicates a bit case. In FIGS. 14 and 15, “−” of the extraction head pixel designation parameter indicates 0 or 1.

However, the data select signal is as shown in FIG. In the drawing, “0” means that the data is selected and output from the latch 2, and “1” means that the data is selected and output from the latch 3.

The so-called white insertion processing is as follows. That is, as described above, since the shift process is a process of moving an image in a set area, it is necessary to output an all-white image from the first pixel to the first pixel to which the shift process is set. Therefore, in this case, all white data is written in the barrel shifter 1 up to the shift head block value calculated by the calculation unit 5, transferred to the latches 2 and 3, and output from the data selector 4. It has been done. This is white insertion processing.

FIG. 18 is a diagram showing the timing of various signals. This figure shows a case where four blocks are shifted, and the image control unit 5 determines the image from the first clock to the fourth clock of the supplied data transfer clock from the first block value of the shift area and the last block value of the shift area. A data transfer clock is generated only during a period corresponding to data, and only a latch clock is generated in other periods. That is, the image data is transferred by the transfer clock only in the effective image area, and only the latch clock is generated and the white data is inserted outside the effective image area. In this way, the image shift of the image data can be realized.

The barrel shifter 1 is omitted by omitting the latch 3.
It is obvious that the output of the data may be used as it is, that is, the data shifted and the data shifted last time may be used.

As is apparent from the above description, one image processing apparatus is used for the extraction process by changing the mode setting and changing the rotation mode of the barrel shifter and the data select signal of the data selector accordingly. It can also be used for shift processing, so that versatility can be provided. Further, since it is possible to cope with a plurality of gradation bit numbers, versatility can be provided.

[0045]

As apparent from the above description, according to the image processing apparatus of the first aspect, even if the number of gradation bits of one pixel of the image data is different, the processing can be performed by one image processing apparatus. The image data can be read out from the first pixel of the area where the image data is processed in units of M bits, which is a unit of block, and according to the image processing apparatus of claim 2, the number of gradation bits of one pixel of the image data is Even if the image data is different, the image data from the head pixel of the area to be processed to the last block to be processed can be read in M-bit block units, so that the number of gradation bits constituting one pixel of the image data Is variable, it is possible to perform predetermined processing according to a plurality of gradation bit numbers with one circuit configuration.

According to the image processing apparatus of the present invention, even if the number of gradation bits forming one pixel of the image data is variable, one circuit configuration can handle a plurality of gradation bit numbers. In addition, it is possible to perform a predetermined process by performing a shift process and an extraction process of image data with a simple configuration, and to efficiently perform the predetermined process even when the write and read block sizes are different. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining left rotation of a barrel shifter.

FIG. 3 is a diagram for explaining right rotation of a barrel shifter.

FIG. 4 is a diagram for explaining the operation of the data selector 4.

FIG. 5 is a diagram for explaining an extracted head block value and an extracted tail block value when M = 8 bits and the number of gradation bits is 8 bits.

FIG. 6 is a diagram for explaining a calculation process of a calculation unit.

FIG. 7: M = 8 bits, the number of gradation bits is 4 bits,
FIG. 9 is a diagram for explaining the calculation of an extracted head block value and an extracted tail block value in the case of 2 bits and 1 bit.

FIG. 8 is a diagram showing shift position control parameters when M = 8 bits and the number of gradation bits is 4 in the extraction processing.

FIG. 9 is a diagram showing shift position control parameters when M = 8 bits and the number of gradation bits is 2 bits in the extraction process.

FIG. 10 is a diagram illustrating shift position control parameters when M = 8 bits and the number of gradation bits is 1 in the extraction processing.

FIG. 11 is a diagram showing a relationship between shift position control parameters and data selector signals when M = 8 bits and the number of gradation bits is 1 in the extraction processing.

FIG. 12 is a diagram showing a specific example of an extraction process.

FIG. 13 is a diagram illustrating timings of various signals in the case of an extraction process.

FIG. 14 is a diagram showing shift position control parameters when M = 8 bits and the number of gradation bits is 4 bits in the shift processing.

FIG. 15 is a diagram showing shift position control parameters when M = 8 bits and the number of gradation bits is 2 bits in the shift processing.

FIG. 16 is a diagram showing shift position control parameters when M = 8 bits and the number of gradation bits is 1 in the shift processing.

FIG. 17 is a diagram illustrating a relationship between a shift position control parameter and a data selector signal when M = 8 bits and the number of grayscale bits is 1 in the shift processing.

FIG. 18 is a diagram illustrating timings of various signals in the case of a shift process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Barrel shifter, 2 ... Latch, 4 ... Data selector, 5 ... Image control part, 6 ... Operation part.

Claims (3)

(57) [Claims] 1. An image processing apparatus for processing pixel data in units of M-bit blocks, wherein the number of grayscale bits per pixel is N (where N is a divisor of M).
Calculating means for calculating the first block to be processed and the first bit to be processed in the block, based on the position of the first pixel in the scanning direction of the area to be processed and the M bits in block units And a reading unit for sequentially reading out the head block calculated by the calculation unit, and a block subsequent to the head block from the head bit calculated by the calculation unit in M-bit block units. Image processing device. 2. The method according to claim 1, wherein the calculating unit is configured to determine a position of a trailing pixel in a scanning direction of an area where the processing is to be performed and the number of gradation bits N
2. The image according to claim 1, wherein a last block to be processed is calculated based on the block data and the block unit M bits, and the reading unit performs reading until image data of the last block is read. Processing equipment. 3. A barrel shifter for reading image data in units of M bits and cyclically shifting the designated number of bits, latch means for latching the image data cyclically shifted by the barrel shifter, and an image cyclically shifted by the barrel shifter. Selecting means for selecting continuous M-bit image data from the data and image data adjacent to the image data and latched by the latch means, wherein the arithmetic means comprises: The number of bits to be cyclically shifted is given to the barrel shifter based on the position of the first bit to be processed in the block, and the selection means is given control information for selecting image data by M bits from the first bit. The image processing apparatus according to claim 1.