JP2730399B2 - Image data reduction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data reduction device.
About the installation.

[0002]

2. Description of the Related Art In recent years, the development of image scanners and memories has made it possible to easily store image data.
An image processing method for processing this data in various ways is required. An example is inserting image data input from an image scanner into a document created by a word processor and outputting the image data to a printer. In order to output image data to a part of a document as described above, it is necessary to appropriately reduce image data. As this reduction method, a method of thinning out a dot unit at a fixed interval or a plurality of binary data is used. There is a method to reduce those who have more black or white. For example, when thinning out a dot in a certain section (thinning out method), the CPU reads out the image data stored in the RAM from the load address and transfers the image data again to another save address in the RAM. Then, based on the programmed thinning data, the CPU does not read the data of the load address to be thinned but stores the data at the next load address and stores it in a continuous save address when re-storing the data, and performs a reduction process. .

[0003]

However, the above-mentioned reduction method requires access to all data in the image data in order to process the data in dot units, so that the processing speed is slow. For this reason, a device dedicated to image processing must be provided to increase the processing speed.

An object of the present invention is to enable high-speed reduction processing of image data without using a device dedicated to image processing.

[0005]

Means of the present invention are as follows.
Processing means for performing data processing in processing units;
Storage means for storing data, and the processing from the storage means.
Image data of a fixed number of bits corresponding to the processing unit of the means
Reading means for reading the data,
The image data of a predetermined number of bits is stored in the data of the processing means.
Data to reduce the number of bits to reduced image data
Reducing means for reducing, and the reduction reduced by the reducing means;
Predetermined bits that are adjacent to each other for small image data
Combine number of reduced image data and combine reduced
Reduced image data of a certain number of bits from image data
Combining means for sequentially extracting
You.

[0006]

[0007]

The operation of the means of the present invention is as follows. Reading hand
The stage corresponds to a unit corresponding to the processing unit of the processing unit from the storage unit.
The image data of a fixed number of bits is read, and the
Image data of a certain number of bits read by the output means
Data of a predetermined number of bits by the data processing of the processing means.
The image data is reduced to reduced image data, and
Reduced image data that has been reduced
Combine reduced image data of a certain number of bits
A fixed number of bits from the combined reduced image data
Small image data is sequentially extracted. Therefore, image processing
Image data can be reduced at high speed without using any equipment
Can be processed. [Explanation of Functional Block Diagram] FIG. 1 is a functional block diagram of the present invention. In FIG.
1 is a reducing means, and 2 is a connecting means.

[0008]

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment will be described below with reference to FIGS. FIG. 2 is a circuit configuration diagram of the embodiment. This apparatus has a CPU 3 which is a microprocessor, and an image sensor 4 for reading an image is connected to the CPU 3 via a read control unit 5 via a bus line. Furthermore, CPU
Reference numeral 3 denotes an image buffer 6 for temporarily storing image data read by the image sensor 4 via the bus line, a ROM 7 for storing a system program for processing image data by the apparatus of the present embodiment,
An external storage device including a RAM 8 for storing data before and after processing and the shift table of the present embodiment, an external storage device control unit 9 for storing image data, a hard disk (DISK) 10, and a floppy disk (FD) 11. A printing device including a printer control unit 12 and a printer 13 on which image data and system programs are printed, and an input device including a key control unit 14 and a keyboard 15 for inputting the above-described processing instructions by an operator. V / RAM 16 for outputting image data to the screen
Composed of a CRT controller 17 and a CRT 18
Each is connected to a T device.

A description will be given of a method of reducing image data in the apparatus having the above-described configuration. In this embodiment, an example in which a 16-bit CPU is used and processing is performed in 16-bit processing units will be described below.

FIGS. 3A and 3B show images before and after reduction processing of image data. FIG. 3A shows an image data image before reduction, and FIG. 3B shows image data before and after reduction processing. It is a figure at the time of contraction. FIG. 11C is a diagram showing an image after reducing and combining the entire image data by combining the reduced data in processing units. In the present embodiment, 16 bits are processed at one time. However, when this is viewed in FIG. 3, the area indicated by the symbol D1 is a processing unit composed of 16-bit data. Similarly, the areas indicated by the symbols D2, D3, and D4 are each configured by 16-bit data.
FIGS. 4A and 4B are views before and after the reduction of 16-bit data of this processing unit. That is, when the 16-bit image data is reduced at a desired reduction ratio, it can be seen from FIG.
As shown in (b), reduced data can be obtained.

First, the reduction method will be described. now,
The image buffer 6 shown in FIG.
Is stored. When the operator inputs a reduction processing instruction from the keyboard 16, the keyboard 15 supplies reduction processing instruction data to the CPU 3 via the key control unit 14 and the bus line. When this instruction data is supplied, C
The PU 3 reads the system program stored in the ROM 7 and performs reduction processing according to the program. That is,
The CPU 3 sets the processing start position data D1 of the image buffer.
Is read into the register A in the CPU 3 from the head position of one line in which is stored, and this data is reduced by the work area register D. For example, when the reduction rate is 13/16 (approximately 81%) and the upper bits are shifted leftward, three 2-bit data are OR-operated to 1 bit each.

In FIG. 4, 1-bit data is generated by performing an OR operation on data at positions of 0 bit, 1 bit, 5 bits and 6 bits, 10 bits and 11 bits.
Remain the data and slide it. The 13-bit data thus obtained and the remaining lower 3 bits generate and store white data (zero) as dummy data, and store the reduced 16-bit data in the register A again.
To be stored. At this time, the 16-bit image data is added to an OR operation circuit incorporated in the microprocessor, and the OR operation circuit OR-adds the 0-bit and 1-bit data to form 0-bit data, and forms 2 bits and 3 bits. , 4-bit data is 1 bit, 2 bits,
The 3-bit data is OR-added with 5-bit and 6-bit data to form 4-bit data. The 7-bit, 8-bit, and 9-bit data are directly changed to 5-bit, 6-bit, and 7-bit data. The data is OR-added to 8-bit data, and 12 bits, 13 bits, 14 bits
9-bit and 10-bit data, respectively,
Bits, 11 bits, and 12 bits. CPU 3 stores 16-bit data reduced by adding zero data to the remaining 3 bits to which no data is added. When the above processing is continued with the next processing data D2, further next processing data D3, and further processing data D3 and D4, and when one line is completed, the processing moves to the next line and processing is performed on the entire image data.
An image obtained by reducing each processing shown in FIG. 3B is obtained.

A 3-bit blank portion K1, shown in FIG.
By combining K2, K3, and K4, the combined image shown in FIG. 3 (c) can be obtained. However, since the processing unit is 16 bits, the actual processing is performed using the image data of the processing data D1.
After reducing the data, the image of the processed data D2
The data is reduced, the reduced data is combined with each other, the image data of the processed data D3 is further reduced, and the reduction process and the combining process are alternately performed so as to perform the combining process, thereby obtaining reduced data. .

Next, the combining process will be described. FIG.
FIG. 9 is a diagram showing a shift of reduced data for a combining process.
The position number (item A) from the reference shown on the left side of the drawing is a number indicating the position of the processing unit from the reduction processing start position (reference position), and is a number repeated in 16 units on the same line.

As shown in FIG. 3C, the reduced image data is divided into reduced data D1a (13 bits) and blank data D1b (3 bits).
The upper 3 bits of the data obtained by reducing the next processing data D2 are added to b, resulting in 16-bit data of the reduced data.

The process of combining the reduced portion of the adjacent data and the reduced portion of the newly reduced data is a combining process. In order to fill in the blank data of the adjacent data, the newly reduced data is converted to the blank space. The process of generating a portion for filling data and the process of dividing it into the remaining portion are shift processes. Item B in FIG. 5 (bit position for combining (left adjacent)) illustrates right-shifted data of the data of the position number (item A), and the hatched portion in FIG. And a blank portion indicates white data as a dummy. The shift amount shown in the B term indicates the shift number and the shift direction in the D term (the number of shifts from the reference data (adjacent to the left)). FIG. 5C (the bit position for combining (right adjacent)) also shows the left shift data, and the E term (the number of shifts from the reference data (right adjacent)) includes the shift number and the shift of this C term. The direction is shown. Here, the blank portions of the items C and E (the portions corresponding to the 1st, 6th, 11th, and 16th items of the item A) are portions that do not need the data of this portion.
The RAM 8 stores this shift data as table data in advance for each reduction ratio. That is, the CPU 3 does not shift the first divisional data D1 of one line after reducing it, but reduces the second divisional data D2 by using the upper bits that are reduced.
For example, the data is stored in the register A until the bit is OR-added.

Subsequently, the CPU 3 sets the load address in the second section data D2 to read the second section data, and reads this data D2. And CPU
No. 3 is generated by right-shifting data from the data D2 in the second section, which first fills in 3 bits generated by the reduction in the first section by OR addition. Then, the right-shifted data is OR-added to data obtained by reducing the preceding data D1 to generate 16-bit reduced data. The CPU 3 stores the 16-bit reduced image data at the save address of the RAM 8 as the first division data of one line of the image data. The remaining 9-bit reduced data and 6-bit dummy white data (zero) are generated by left shift and stored in the register A.

Subsequently, the CPU 3 reduces the data D3 to fill the 6-bit dummy portion, generates 6-bit shifted data obtained by shifting the data rightward by right shifting, and adds the shifted data to the data of the register A. The addition is performed to generate data of the second section of the reduced data. In this embodiment, the CPU 3 of 16-bit processing is used.
Since the address is 8 bits per address, the data of the register A is stored in the second section of the RAM 8 for storing the reduced data by incrementing by +2. By processing the image data up to the fifth division in this way, the total shift amount up to that point exceeds the number of bits in the processing unit. Is added to. When the 16-bit image data is reduced to 16/13, a 2-bit dummy portion is generated at this time. To fill in these 2 bits, the save address is not incremented and the image data in the seventh section is not incremented. The data is reduced, and the reduced data in the seventh section is shifted rightward to generate data for filling 2 bits of the dummy portion of the register A.

The CPU 3 adds this shift data to the register A to generate 16-bit reduced data. Here, the save address of the reduced data storage area of the RAM 8 is stored in the fifth section of the initial value +8. CPU in the same way
Reference numeral 3 stores the data in the eighth section of the image data in the sixth and seventh sections of the reduced data, and stores the data in the ninth section of the image data in the seventh and eighth sections of the reduced data. When the processing is repeated in this manner, the shift amount is again set to 1 in the eleventh division of the image data.
Since the processing is repeated, the twelfth section of the image data is processed without incrementing the save address. As a result, two bits of one part of the tenth division, one part of the data of the eleventh division, and one part (one bit) of the twelfth division of the image data
Is reduced and OR-added, and the reduced data is reduced data 9
It will be stored in the section. Therefore, next, the data in the 12th section of the image data is replaced with the 9th section of the reduced data and 1
In the 0th section, the data in the 13th section of the image data is stored in the 10th and 11th sections of the reduced data, and the data in the 14th section of the image data is stored in the 11th and 12th sections of the reduced data. The data of the fifteenth division of the image data is stored in the twelfth division and the thirteenth division of the reduced data, respectively. In the 16th division of the image data, the shift amount again goes through the number of bits of the processing unit, so that the image data of the 15th division is shifted to the left and OR-added to the 3 bits stored in the register A, and the RAM 8 It is stored in the 13th section of the above reduced data.

In the thirteenth division of the reduced data, the data of the sixteenth division of the image data is just filled with the reduced data. Therefore, the processing from the first division of the image data is performed from the seventeenth division of the image data. The same shift and OR addition as described above are performed, and the save address is stored as if the reduced data in the 17th section of the image data and the data obtained by shifting the reduced data in the 18th section to the left are slid to the 14th section of the reduced data. I do. In this manner, when one line of image data is sequentially reduced and all the data of one line are processed, the CPU 3 sets the load address at the beginning of the two lines of image data, and returns to the same manner as the first line. The image data is reduced to 13/16 by storing all the image data in line units by performing the reduction process and the combining process of the image data, and the reduced data can be stored in the RAM 8.

When the above processing is completed, the operator can output the reduced data on the RAM 8 to the printer 13 or CRT 18 in accordance with an instruction from the keyboard 15 to obtain a reduced image.

Next, the above processing will be sequentially described with reference to flowcharts. FIG. 6 is a processing flowchart of the embodiment. When the processing start data is added to the CPU 3, the CPU 3 sets the reading start position of the image data, sets the position data i of the processing unit to 1 in order to determine the reference position of the shift processing (processing S1), and sets the address to be loaded. An image data stored in the image buffer 6 is set at the head of the line, and an address for saving the data is also set in the RAM 8 for storing the reduced image data (process S2). This allows the CPU 3 to operate, for example, as shown in FIG.
A load address is set at the head of the data D1 shown in (a). Subsequently, the CPU 3 loads data with a 16-bit width from the image buffer 6 into the register A in the CPU 3 in order to perform the reduction processing (processing S3), ORs the above-described six data to shift the 13-bit data to the left. Reduced data is generated, and white data (zero) is generated in the lower three bits to obtain 16-bit reduced data (process S
4). The CPU 3 transfers this reduction processing from the register A to a work area (for example, the register C) and performs the reduction processing, and stores the reduced data after the reduction processing in the register A again. Second
In this invention, this reduction is processed by an OR operation circuit prepared in advance for each reduction ratio.

Next, the numerical value of the position data i is determined for addition processing (processing S5). Since the position data i is the first, the shift processing is not performed and the CPU 3 stores the reduced 16-bit data of the register A into 2 bits. The data is stored in the register B in order to obtain 16-bit data reduced by adding to the reduced data of the section (process S6). CP at the first position (i = 1)
U3 refers to the shift table of the RAM 8 and has no shift as shown in FIG. 5D, so that no shift processing is performed. This is because the first data of the line remains the head data even after the reduction since the reduction processing is performed to the left.

Next, the CPU 3 adds 1 to the position data i in order to read the data of the second section of the image data (process S7).
It is determined whether or not the position data is larger (step S8). Here, the position data is 2, and the position data is incremented by 1 in step S7.
Since it is not larger than 6 (NO), the process proceeds to the next process, and it is determined whether the process of one line is completed (process S9). Since the position data has just finished the first processing and there is image data and the one-line processing has not been completed (NO), the position data is second (i =
In order to process the image data of 2), the load address of the image buffer 6 is incremented by 2 and the address is set to an initial value +2 (process S10). The increment is made here because the CPU 3 processes data of 8 bits per address with 2 address data as one unit.
When the CPU 3 increments the load address by 2, the process proceeds to step S3, and loads the register A with the next position data i = 2 (second section) from the load address (initial address + 2) (process S3). ). Here, similarly to the image data with the position data i = 1, the data reduced to 13 bits is stored again in the register A (processing S4), and a determination processing S5 is performed to determine what kind of combining processing is to be performed next. To select the shift processing.
Here, since the position data i = 2, the combining process S11 is performed. That is, the CPU 3 outputs a reduced image of the register A.
The data is determined by the position data i = 2 (the second item in FIG. 5B) is shifted right by 13, the data is OR-operated with the data of the register B, and the operation data is stored in the register B (process S11). . As a result, the image data of the reduced position data j = 1 (the first division in units of 16 bits) can be stored in the register B, so that the CPU 3 stores the data of the register B in the save address of the RAM 8 (processing S12). ). Next, the save address is incremented by 2 in the same manner as in step S10 in order to transfer the save address to the next section (step S13), and the position where the next processed image data is stored is stored in the RAM 8 at the storage position j = Set to 2 (second section). And processing S
In step 11, the reduced data of the position data i = 2 stored in the register A is shifted left by 3 bits in the work area and stored in the register A again (process S14).

Note that the CPU 3 discards the portion that protrudes from the register in this shift processing, and stores white data (zero) as a dummy in a register into which data does not enter.
The CPU 3 stores the reduced data shifted to the left in step S14 in the register B in order to reduce the image data of the next third section and to perform OR addition (step S15). And CP
U3 stores a part (left part) of the position data j = 2 of the next reduced image in the register B by this processing S15. Again, the CPU 3 increments the position data i of the image buffer 6 by 1 in order to process the data of the third section in the process S7 (judgment process S8), and loads the data in the process 10 through the judgment process S9 of the end of the processing of one line. Increment the address by 2. Then, the position where the load address of the image buffer 6 is the initial value + 4, that is, the position data i =
Image data is read from the location 3 (third section) and reduced (processing S3 and processing S4). This time, since position data i = 3 (determination processing S5), processing S16 is performed. In this case, since the position data i = 3, the shift number of the item B corresponding to item 3 in FIG. 5A is set to 10 shifts to the right, and the CPU 3 shifts the data of the register A to the right by 10 and stores it in the register B in step S15. The stored reduced data and the data shifted to the right by 10 are OR-added and stored in the register B (process S16), and this data is stored in the save address (initial value + 2) (process S17).
As a result, the RAM 8 stores the 32-bit reduced data of the position data j = 1 and j = 2 by the processing so far.

Next, the CPU 3 increments the save address by 2 in order to save the next data in the third section (j = 3) of the reduced data (process S18), and then stores the data in the register A in FIG. After shifting by the shift amount (6 left shifts) of the C term corresponding to the third (process S19),
This data is stored in the register B (process S20).

When the processing of the image data is continued as described above and the position data i = 6 is selected in the processing S5 for determining the position data as the shift index, the CPU 3 executes the processing S6.
Is executed, the data in the register A is shifted by 1, OR-added with the data in the register B, and stored again in the register B (process S21). However, in this case, since the shift amount makes one round of 16 bits, the processing shifts to processing S7 for incrementing the position data i in order to load the next image data, and the CPU 3 increments the position data read from the image buffer 6 by one. (Process S7), and the process address on the line is moved (Process S8 to Process S10).
Then, it is determined what kind of shift is to be performed by reducing the image data (steps S3 to S5), and A in FIG.
Shift processing and combination processing corresponding to items 7 to 10 are repeated. Here, the CPU 3 reduces the image data in the image buffer 6 and shifts the right-shifted data to a position two less in the RAM 8 in processing units as viewed from the position of the image buffer 6 and the left-shifted data to a position one less in the RAM 8 in processing units. Store. That is, the image data of the position data i = 7 in the image buffer 6 is reduced and stored in the RAM 8 as position data j = 5 (right shift data) and j = 6 (left shift data).

In this way, the CPU 3 shifts only the image data of the position data i = 11 to the right again, and performs the position data i = 7 to 10 for the next position data i = 12 to 15.
Further, the shift data is stored at a position in the RAM 8 one to the left of the position of the image buffer 6. That is, CPU
Numeral 3 reduces the image data of the position data i = 12 in the image buffer 6 and stores it in the position of the position data j = 9 (right shift data) j = 10 (left shift data) in the RAM 8.

When the above processing is repeated and the position data i = 16 is determined in the determination processing S5, the CPU 3 executes the processing S22. Here, the CPU 3 OR-adds the image data reduced in process S4 to the right by 3 bits shown in item B corresponding to item 16 in item A of FIG. 5 with the data in register B and stores the result in register B (processing S22). This data is stored in the save address (initial value + 24) of the RAM 8 (process S23). Up to one line in the processing so far
256-bit 16-section image data is 208 bits 1
Since the data has been reduced to three sections, the reduced data in the sixteenth section is just at the end of the thirteenth section, and there is no fraction of 16 bits.

Next, the CPU 3 stores the save address in the RAM.
In step S24, the position data i is incremented by one in order to make the location for storing the reduced data on the 8th section into the 14th section (step S24). Then, here, the position data i becomes 17, and the shift process for filling the fraction goes through one round as described above. Then, since the position data i is larger than the value 16 in the determination processing S8 (YES), the position data i is set to 1 to repeat the shift processing from the reference position.
It is decremented by 6 (process S25), and the position data i is set to 1 again. Therefore, the position of the position data i = 1 becomes a new reference position for the shift.

That is, if the processing of one line is not completed in the determination processing S9 (NO), the loading of the image buffer 6 is performed.
The address is further incremented by 2 (process 10),
The shift shown in FIG. 5 is repeated with the position of the load address (initial value + 32) as a new reference position, and the combining process with the adjacent data is performed. If the processing of one line has been completed in the determination processing S9 (YES), it is determined whether or not all lines have been completed (processing S26). If not all the lines have been completed (NO), the next of the image data has been determined. The process is shifted to the left end of the line (at the left end) (process S27), and the processes from S1 to 9 are repeated again. If all the lines are completed (YES), all the processes are completed.

As described above in detail, according to the present invention, a general-purpose CPU can be used without using a device dedicated to image processing.
Is used to convert the image into pixels of the processing unit of the CPU,
In other words, if the CPU is a 16-bit CPU, it is divided into 16-bit units and the processing is performed by the registers inside the CPU, so that the reduction processing is performed at a much higher speed than the conventional image processing in which data is transferred from memory to memory in dot units. It can be performed.

In the embodiment, an example using a 16-bit CPU has been described. However, when an 8-bit CPU is used, only the shift amount shown in FIG. 5 is different, and the reduction processing and the combining processing are executed using the register of the 8-bit CPU. it can. For example, when the reduction ratio is about 75%, a reduction of 6/8 is performed. If the shift in the case of performing leftward reduction is a right shift, no shift is performed when the position data in the image buffer is the first, a 6-bit right shift is performed when the position data is second, and a 4-bit right shift is performed when the position data is third. At the fourth time, right shift by 2 bits and at the fifth time there is no shift, and thereafter the first to fourth shifts are repeated to perform the combining process. Of course, at this time, the left shift corresponds to the above-mentioned right shift without first processing, the second 2-bit left shift, the third 4-bit left shift, and the fourth 6-bit left shift. 32-bit CPU
In the case where is used, a shift table can be created in the same manner as the above-described processing, and reduced data can be generated by the reduction processing and the combining processing.

Although the embodiment has been described with respect to the leftward reduction processing, when performing leftward processing, for example, 16
13/16 or about 81 in the same manner as in the embodiment using a bit CPU.
When the reduction of% is performed rightward, the right and left are reversed in the shift diagram of FIG. That is, when the position data i = 2, 13-bit left-shifted data and 3-bit right-shifted data are generated.
By combining (by OR addition) with the data of 1 without shift, a rightward reduction process can be performed.

Of course, if a 32-bit CPU is used, the unit of one word can be selected from 8, 16 and 32 bits, so that the denominator of the reduction ratio can be 8, 16, or 32. At this time, if image data is read from an original image having the same size, a rough processed image can be obtained by processing in units of 8 bits, and a thin processed image can be obtained by processing in units of 32 bits.

[0037]

According to the present invention, in the processing unit of the processing means,
Read the corresponding fixed number of bits of image data and read
The image data of a certain number of bits that have been
Reduced by image processing and reduced image data
Data of a predetermined number of adjacent bits
Image data is combined, and the reduced image data
Sequentially extract reduced image data of a certain number of bits from the data
Use of a device dedicated to image processing.
Image data can be reduced at high speed using a general-purpose CPU
Can be processed.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of the present invention.

FIG. 2 is a system configuration diagram of an embodiment.

FIGS. 3A to 3C show images before and after image data reduction processing.

FIGS. 4A and 4B are diagrams before and after reduction of 16-bit data of a processing unit.

FIG. 5 is a diagram illustrating a shift of a combining process.

FIG. 6 is a processing flowchart of an embodiment.

[Explanation of symbols]

 1 Reduction means 2 Coupling means

Claims (1)

(57) [Claims] 1. A data processing unit for performing data processing in a predetermined processing unit.
And management means, storage means for storing image data, one corresponding from the storage means in the processing units of the processing means
Reading means for reading image data having a fixed number of bits, and image data having a certain number of bits read by the reading means.
Predetermined data by the data processing of the processing means.
And reduction means for reducing the bets of a reduction image data, One to reduced image data reduced by the reducing means
And the reduced image data of a predetermined number of adjacent bits
Data from the combined reduced image data
Combined hand that sequentially extracts reduced image data with a fixed number of bits
Image data reduction apparatus characterized by comprising a stage, a.