JP3209053U - Magnetic sensor integrated circuit, motor assembly and application apparatus - Google Patents

Abstract

A magnetic sensor integrated circuit, a motor assembly, and an application device capable of obtaining an accurate magnetic field detection signal are provided. A magnetic sensor integrated circuit includes a magnetic sensor, a signal processing unit, an output control circuit, and an output port. The magnetic sensor receives a constant current for detecting the magnetic polarity of the external magnetic field and outputs a differential signal. The signal processing unit amplifies the difference signal and removes the offset of the difference signal to obtain a magnetic field detection signal. The output control circuit causes at least one of a first state in which current flows from the output port to the outside and a second state in which current flows from the outside to the output port based on at least the magnetic field detection signal. Control to operate in one state. [Selection] Figure 1

Description

  The present disclosure relates to magnetic field detection, and more specifically to a magnetic sensor integrated circuit, a motor assembly, and an application device.

  Magnetic sensors are widely applied in modern industrial and electronic products to induce magnetic field strength for measuring physical parameters such as current, position and direction. Motors are an important field of application for magnetic sensors. The magnetic sensor can function as a rotor magnetic pole position sensor in the motor.

  Generally, a magnetic sensor can output only a magnetic field detection signal. However, the magnetic field detection signal is weak and mixed with the offset of the magnetic sensor, and it is difficult to obtain an accurate magnetic field detection signal.

  In view of the above, a magnetic sensor integrated circuit, a motor assembly, and an application device are provided.

  The technical solution of the present disclosure for achieving the above object is as follows.

Magnetic sensor integrated circuit
A rectifier circuit that converts external power into DC power;
A magnetic sensor that receives a constant current to detect the polarity of the external magnetic field and outputs a differential signal;
A signal processing unit that converts the differential signal output by the magnetic sensor into a magnetic field detection signal by amplifying the differential signal and removing the offset of the differential signal;
Based on at least the magnetic field detection signal, the magnetic sensor integrated circuit has at least one of a first state in which current flows from the output port of the magnetic sensor integrated circuit to the outside and a second state in which current flows from the outside to the output port. An output control circuit that controls to operate in a state;
including.

  Optionally, the rectifier includes a full wave rectifier bridge and a voltage stabilization unit, the full wave rectifier bridge converts external AC power to a DC voltage and powers the output control circuit, and the voltage stabilization unit The DC voltage output by the wave rectifier bridge is converted into a low voltage DC and supplied to the signal processing unit.

Optionally, the differential signal includes a magnetic field signal and an offset signal, and the signal processing unit includes a first chopping switch for modulating the magnetic field signal and the offset signal to a high frequency region and a baseband frequency, respectively, and a first chopping. The differential signal output by the switch is amplified, the magnetic field signal of the differential signal output by the first chopping switch is demodulated to the baseband frequency, and the demodulated differential signal is output.
Optionally, the signal processing unit further includes a switch capacitor filter module, the switch capacitor filter module including a first switch capacitor filter, a second switch capacitor filter, and a third switch capacitor filter. And a fourth switch-capacitor filter, wherein the first switch-capacitor filter and the second switch-capacitor filter receive the difference signal output by the first amplifier unit in the first half cycle as a first sample. The third switch capacitor filter and the fourth switch capacitor filter sample the signal (sampled signal), and the difference signal output by the first amplifier unit in the second half cycle is used as the second sample signal. Sump Ring.

  Optionally, the signal processing unit further includes a converter for converting the differential signal output by the switch capacitor filter module into a magnetic field detection signal and outputting the magnetic field detection signal to an output control circuit.

  Optionally, the integrated circuit outputs a first clock signal to the first chopping switch and the first amplifier unit, outputs a second clock signal to the switch capacitor filter module, and outputs a third clock signal. And a timing controller configured to output to the converter, wherein the second clock signal is delayed by a first predetermined time with respect to the first clock signal, and the second clock signal is The third clock signal is delayed for a second predetermined time.

  Optionally, the switched capacitor filter module further includes an adder for performing offset removal and amplification by adding the first sample signal to the second sample signal.

  Optionally, the signal processing unit further includes a second amplifier for amplifying the difference signal output by the adder.

  Accordingly, the present disclosure further provides a motor assembly, which includes an electric motor powered by alternating current power and a magnetic sensor integrated circuit.

  Accordingly, the present disclosure further provides an application device including a motor assembly.

  In order that the technical solutions according to the embodiments of the present disclosure or according to the prior art will become more apparent, the drawings according to the embodiments of the present disclosure will be briefly described below. Apparently, the drawings are merely some embodiments of the present disclosure, and those skilled in the art can obtain other drawings from these drawings without creative work.

1 is a block diagram of a magnetic sensor integrated circuit according to an embodiment of the present disclosure. FIG. 2 is a circuit diagram of a rectifier circuit according to an embodiment of the present disclosure. FIG. FIG. 6 is a structural diagram of a magnetic sensor integrated circuit according to another embodiment of the present disclosure. 3 is a schematic diagram of signals of a timing controller according to an embodiment of the present disclosure. 2 is a structural diagram of a magnetic sensor and a first chopping switch according to an embodiment of the present disclosure. FIG. FIG. 5b is a time sequence diagram of four sub-clock signals of the magnetic sensor and the first chopping switch shown in FIG. 5a. Fig. 6 is a schematic diagram of control signals for the discharge switch and the first chopping switch of Fig. 5a. FIG. 5b is a schematic signal diagram of the circuit shown in FIG. 5a. 1 is a schematic diagram of a first amplifier according to an embodiment of the present disclosure. 1 is a schematic diagram of a switched capacitor filter module according to an embodiment of the present disclosure. 4 is a schematic diagram of an adder according to an embodiment of the present disclosure. 1 is a schematic diagram of a transducer according to an embodiment of the present disclosure. 1 is a schematic diagram of a principle for determining the polarity of a magnetic field according to an embodiment of the present disclosure. 3 is a schematic diagram of an output of a periodic clock signal according to an embodiment of the present disclosure. 2 is a schematic circuit diagram of an output control circuit according to an embodiment of the present disclosure. FIG. FIG. 6 is a schematic circuit diagram of an output control circuit according to another embodiment of the present disclosure. FIG. 6 is a schematic circuit diagram of an output control circuit according to still another embodiment of the present disclosure. 6 is a schematic diagram of an output control circuit according to yet another embodiment of the present disclosure. 1 is a schematic structural diagram of a circuit of a motor assembly according to an embodiment of the present disclosure. 1 is a schematic structural diagram of a synchronous motor according to an embodiment of the present disclosure.

  The technical solutions of the embodiments of the present disclosure are clearly and completely illustrated with reference to the drawings of the embodiments of the present disclosure. Apparently, the described embodiments are very few rather than all of the embodiments of the present disclosure. Any other embodiments obtained by a person of ordinary skill in the art without creative work based on the embodiments of the present disclosure are within the scope of the present disclosure.

  As described in the background section, in the prior art, in general, a magnetic sensor integrated circuit can output only a magnetic field detection result, and an additional peripheral circuit is required to process the magnetic detection result. The Therefore, the entire circuit has a high cost and is not reliable.

  In view of this, embodiments of the present disclosure provide a magnetic sensor integrated circuit, an electric motor assembly, and an application device, and by extending the functions of a conventional magnetic sensor integrated circuit, reduce the cost of the entire circuit, and Improves overall circuit reliability. To achieve the above objective, technical solutions according to embodiments of the present disclosure will be described in detail in connection with FIGS.

  FIG. 1 shows a schematic structural diagram of a magnetic sensor integrated circuit according to an embodiment of the present disclosure, which includes an input port, a rectifier circuit 100, a magnetic sensor 200, a signal processing unit 300, an output control circuit 400, and an output port. 2 is included.

  The rectifier circuit 100 can convert external power into DC power.

  The magnetic sensor 200 can detect a polarity of an external magnetic field by receiving a constant current that is not affected by a temperature change, and output a differential signal.

  The signal processing unit 300 can convert the difference signal output by the magnetic sensor 200 into a magnetic field detection signal by amplifying the difference signal and removing the offset of the difference signal, and can output the magnetic field detection signal.

  The output control circuit 400 can control the magnetic sensor integrated circuit to operate at least in the first state or the second state. In the embodiment, the first state can be a current flow flowing from the output port 2 to the outside, and the second state can be a current flow flowing from the outside to the output port 2. In the embodiment, the differential signal includes a magnetic field signal and an offset signal.

  In an embodiment of the present disclosure, external power is supplied to the rectifier circuit via the input port, and the input port can include a first input port 11 and a second input port 12, which are connected to the external power. Connected. In embodiments of the present disclosure, the connection between the input port and the external power can be a direct connection or an indirect connection, which is not limited herein and needs to be designed based on the actual application. There is. In an embodiment of the present disclosure, the external power received by the rectifier circuit is AC power. Furthermore, the constant current that the magnetic sensor is insensitive to temperature can be supplied by a rectifier circuit, which is not limited herein.

  In an embodiment of the present disclosure, the rectifier circuit 100 may include a full wave rectifier bridge and a voltage stabilization unit coupled to the output of the full wave rectifier bridge. The full-wave rectifier bridge can convert an AC signal output by AC power into a DC signal, and the voltage stabilization unit can stabilize the DC signal output by the full-wave rectifier bridge within a predetermined range. it can. FIG. 2 shows a circuit diagram of a rectifier circuit according to an embodiment of the present disclosure, in which a full-wave rectifier bridge 110 includes a first diode 111 and a second diode 112 coupled in series, and a third diode coupled in series. 113 and a fourth diode 114 may be included. The first input terminal 11 is a common terminal between the first diode 111 and the second diode 112, and is electrically connected to the AC power VAC +, and the second input terminal 12 is a third diode. 113 is a common end between the fourth diode 114 and the fourth diode 114, and is electrically connected to the AC power VAC−.

  The input terminal of the first diode 111 is electrically connected to the input terminal of the third diode 113 to form the first output terminal V1 of the full-wave rectifier bridge 110, and the output terminal of the second diode 112 is , Electrically connected to the output of the fourth diode 114 to form the second output V2 of the full-wave rectifier bridge 110. The second output terminal V2 outputs a DC voltage of about 16V. Preferably, the output control circuit 400 is powered by a DC voltage output by the second output terminal V2 of the full wave rectifier bridge 110.

  Further, the voltage stabilization unit 120 includes a Zener diode 121, a first resistor 122, a second resistor connected between the first output terminal V1 and the second output terminal V2 of the full-wave rectifier bridge 110. A resistor 123, a Zener diode 124, and a transistor 125 are included. Both the anode of the Zener diode 121 and the anode of the Zener diode 124 are coupled to the first output V1 of the full wave rectifier bridge 110. The cathode of the Zener diode 121 and the first end of the first resistor 122 are both coupled to the second output V2 of the full wave rectifier bridge 110. The second end of the first resistor 122 is coupled to the first end of the second resistor 123 and the first end of the transistor 125. The second end of the second resistor 123 is connected to the gate of the transistor 125 and the cathode of the Zener diode 124. The second end of the transistor 125 and the anode of the Zener diode 124 each function as two output ends of the voltage regulation unit 120, that is, two output ends of the rectifier circuit. The output voltage of the first output terminal AVDD of the rectifier circuit is a DC voltage of about 5 V, and the second output terminal AVSS is grounded.

  As shown in FIG. 1, a signal processing unit 300 according to an embodiment of the present disclosure includes a first chopping switch 301, a first amplification unit 302, and a switched capacitor filter module, which are sequentially connected. 303 and converter 304. First chopping switch 301 is electrically coupled to magnetic sensor 200.

  The first chopping switch 301 can modulate the magnetic field signal and the offset signal of the differential signal output from the magnetic sensor 200 to a high frequency region and a baseband frequency, respectively.

  The first amplifier unit 302 amplifies the differential signal output from the first chopping switch 301, and converts the magnetic field signal and offset signal of the differential signal output from the first chopping switch into a high frequency region and a baseband, respectively. Demodulated to frequency and configured to output a demodulated magnetic field signal and a demodulated offset signal.

  The switch capacitor filter module 303 samples the differential signal output by the first amplifier unit 302, removes the offset of the sample signal to obtain the differential signal, amplifies the differential signal, and converts the amplified differential signal to Can be output.

  The converter 304 can convert the differential signal output from the switch capacitor filter module 303 into a magnetic field detection signal and output the magnetic field detection signal to the output control circuit 400. In an embodiment, the converter is an analog to digital conversion module.

  Furthermore, to ensure better operating performance of the magnetic sensor integrated circuit, FIG. 3 shows a schematic structural diagram of a magnetic sensor integrated circuit according to another embodiment of the present disclosure, and as shown in FIG. The integrated circuit further includes a timing controller 500. The timing controller 500 outputs the first clock signal to the first chopping switch 301 and the first amplifier unit 302, outputs the second clock signal to the switch capacitor filter module 303, and outputs the third clock. The signal is configured to be output to the converter 304. The second clock signal is delayed for a first predetermined time with respect to the first clock signal and delayed for a second predetermined time with respect to the third clock signal. The first delay time is longer than the second delay time. The frequency of the first clock signal is the chopping frequency of the first chopping switch 301, and the frequency of the second clock signal is the sampling frequency of the switch capacitor filter module 303.

  In order to guarantee the accuracy of the output signal, there is a predetermined delay between the first clock signal, the second clock signal, and the third clock signal. Optionally, in embodiments of the present disclosure, the first predetermined time may be a quarter of the period of the first clock signal and the second predetermined time is 5 nanoseconds. Further, the first clock signal, the second clock signal, and the third clock signal have the same frequency in the embodiments of the present disclosure. Optionally, reference can be made to FIG. 4, which is a schematic diagram of the signals of a timing controller according to an embodiment of the present application. The first through third clock signals as shown in FIG. 4 are simply a time series relationship between these three signals (ie, optionally, the first predetermined time is a quarter of the first clock signal. And the second clock signal can be delayed by 5 nanoseconds relative to the third clock signal) and frequency relationship (ie, the first clock signal, the second clock signal, and the third clock Note that the signals are of the same frequency) and do not represent actual signals in the operation of the magnetic sensor according to embodiments of the present application.

  In the embodiment of the present disclosure, the differential signal output by the magnetic sensor includes a magnetic field signal and an offset signal. The magnetic field signal is an ideal magnetic field voltage signal that is compatible with the external magnetic field and is detected by the magnetic sensor, and the offset signal is the intrinsic offset of the magnetic sensor. The ideal magnetic field voltage signal output by the magnetic sensor is weak, typically only a few tens of millivolts, while the offset signal is close to 10 millivolts. Therefore, in the subsequent process, it is necessary to remove the offset signal and amplify the ideal magnetic field voltage signal.

  In order to process the differential signal output by the magnetic sensor, first, the magnetic field signal of the differential signal is modulated by the first chopping switch 301 into the high frequency region. As shown in FIG. 3, the first chopping switch 301 modulates the magnetic field signal of the differential signal output by the magnetic sensor 200 to a high frequency region based on the control of the timing controller 500, and offset signal of the differential signal To the baseband frequency. Preferably, the frequency in the high frequency region is above 100K hertz and the baseband frequency is below 200Hz.

  Please refer to FIGS. 5a to 5d. FIG. 5a is a structural diagram of a magnetic sensor and a first chopping switch according to an embodiment of the present disclosure. FIG. 5b is a timing diagram of the four sub-clock signals of the magnetic sensor and the first chopping switch shown in FIG. 5a. FIG. 5c is a schematic diagram of signal control of the discharge switch and the first chopping switch shown in FIG. 5a.

  The magnetic sensor 200 includes four contact terminals. The magnetic sensor 200 includes a first terminal A and a third terminal C arranged to face each other, and a second terminal B and a fourth terminal D arranged to face each other. In the embodiment of the present disclosure, the magnetic sensor 200 is a Hall plate. The magnetic sensor 200 is driven by a first power 13 that can be supplied by the rectifier circuit 100. In the embodiment, the power 13 is a constant current source that is not affected by temperature.

  As shown in FIG. 5a, the first chopping switch 301 includes eight switches K1 to K8, which are connected to four terminals. Specifically, the first chopping switch 301 includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, and a seventh switch. Switch K7 and an eighth switch K8. The first switch K1 is connected between the first power 13 and the first terminal A. The second switch K2 is connected between the first power 13 and the second terminal B. The third switch K3 is connected between the ground terminal GND and the third terminal C. The fourth switch K4 is connected between the ground terminal GND and the fourth terminal D. The fifth switch K5 is connected between the first output terminal P and the fourth terminal D. The sixth switch K6 is connected between the first output terminal P and the third terminal C. The seventh switch K7 is connected between the second output terminal N and the second terminal B. The eighth switch K8 is connected between the second output terminal N and the first terminal A. The first clock signal includes a first sub clock signal CK2B, a second sub clock signal CK1B, a third clock signal CK2, and a fourth sub clock signal CK1. The first switch K1 and the second switch K2 are controlled by the first sub clock signal CK2B and the second sub clock signal CK1B, respectively. The third switch K3 and the fourth switch K4 are controlled by the third sub clock signal CK2 and the fourth sub clock signal CK1, respectively. The fifth switch K5 and the sixth switch K6 are controlled by the third sub clock signal CK2 and the fourth sub clock signal CK1, respectively. The seventh switch K7 and the eighth switch K8 are controlled by the third sub clock signal CK2 and the fourth sub clock signal CK1, respectively.

  In order to ensure the accuracy of the output signal, the first clock signal includes at least two non-overlapping sub-clock signals. The phase of the first sub clock signal CK2B is opposite to the phase of the third sub clock signal CK2, and the phase of the second sub clock signal CK1B is opposite to the phase of the fourth sub clock signal CK1. The third sub clock signal CK2 and the fourth sub clock signal CK1 are non-overlapping sub clock signals.

  When the first terminal A is electrically connected to the first power 13 and the third terminal C is electrically connected to the ground terminal GND, the second terminal B is connected to the second output terminal N. The fourth terminal D is electrically connected to the first output terminal P. When the second terminal B is electrically connected to the first power 13 and the fourth terminal D is electrically connected to the ground terminal GND, the first terminal A is connected to the second output terminal N. The third terminal C is electrically connected to the first output terminal P. The first output terminal P outputs the differential signal P1, and the second output terminal N outputs the differential signal N1.

  In addition to the magnetic sensor 200 and the first chopping switch 301 described, the magnetic sensor 200 includes the first discharge branch 14 connected between the first terminal A and the third terminal C, ie, the first A branch between the terminal A and the third terminal C, and a second discharge branch 15 connected between the second terminal B and the fourth terminal D, ie, the second terminal B and the fourth terminal It further includes a branch with terminal D. Before the first terminal A and the third terminal C function as power input terminals, and the second terminal B and the fourth terminal D function as magnetic detection signal output terminals, the second discharge branch 15 is electrically conductive. It is sex. Before the first terminal A and the third terminal C function as magnetic detection signal output terminals, and the second terminal B and the fourth terminal D function as power input terminals, the first discharge branch 14 is electrically conductive. It is sex.

  In a possible implementation, the first discharge branch 14 may include a first discharge switch S1 and a second discharge switch S2 connected in series. The first discharge switch S1 and the second discharge switch S2 are controlled by the first sub clock signal CK2B and the second sub clock signal CK1B, respectively. The second discharge branch 15 includes a third discharge switch S3 and a fourth discharge switch S4 connected in series. The third discharge switch S3 and the fourth discharge switch S4 are controlled by the first sub clock signal CK2B and the second sub clock signal CK1B, respectively.

  When the first terminal A and the third terminal C function as power input terminals and the second terminal B and the fourth terminal D function as magnetic field signal output terminals, the first sub-clock signal CK2B is During a period overlapping with the second sub-clock signal CK1B, the first discharge switch S1 and the second discharge switch S2 are simultaneously turned on. When the first terminal A and the third terminal C function as magnetic signal output terminals, and the second terminal B and the fourth terminal D function as power input terminals, the first sub-clock signal CK2B is During a period overlapping with the second sub-clock signal CK1B, the third discharge switch S3 and the fourth discharge switch S4 are simultaneously turned on.

  As shown in FIG. 5b, the four sub-clock signals are divided into two non-overlapping control signals, namely the third sub-clock signal CK1 and the fourth sub-clock signal CK2, and two overlapping signals, ie the second sub-clock. A signal CK1B and a first subclock signal CK2B are included. CK1 is opposite to CK1B and CK2 is opposite to CK2B. Overlapping subclock signals CK1B and CK2B are both high during the period in which CK1B and CK2B overlap, ie, during the period between the two dotted lines shown in FIG. 5b. The two non-overlapping subclock signals CK1 and CK2 and the two overlapping subclock signals CK1B and CK2B can have a frequency in the range of 100 KHz to 600 Hz including both ends, and preferably have a frequency of 400 KHz. .

  In the embodiment of the present disclosure, each of the eight switches included in the first chopping switch 301 and the four discharge switches included in the discharge branch may be a transistor. Furthermore, when CK1 is high, CK2B is high and CK2 and CK1B are low. In such a case in relation to FIG. 5c, in such a case, the second terminal B and the fourth terminal D are electrically connected to the first power 13 and the ground terminal GND, respectively, and function as power input terminals. The switch between the third terminal C and the first output terminal P is turned on, the switch between the first terminal A and the second output terminal N is turned on, and the first terminal A and the first output terminal P are switched on. 3 terminal C functions as an output terminal of the magnetic field signal. A short time immediately after CK1 shifts from the high level to the low level, that is, the time between the first two dotted lines shown in FIG. 5b is the overlapping period of the two overlapping subclock signals CK1B and CK2B. During the overlap period, both CK1B and CK2B are at a high level, and the third discharge switch S3 and the fourth discharge switch S4 between the second terminal B and the fourth terminal D are simultaneously turned on. The second terminal B is short-circuited with the fourth terminal D, so that the charge stored in the parasitic capacitor between the second terminal B and the fourth terminal D is removed. After the overlap period, when CK1 is low, CK2B is low and CK2 and CK1B are high. In this case, the first terminal A and the third terminal C are electrically connected to the first power and the ground terminal GND, respectively, and function as a power input terminal, and the second terminal B and the first output terminal The switch between P and P is turned on, the switch between the fourth terminal D and the second output terminal N is turned on, and the second terminal B and the fourth terminal D are output terminals of the magnetic field signal. Function as. A short time immediately before CK1 shifts from the low level to the high level, that is, the time between the second two dotted lines shown in FIG. 5b is an overlapping period of the two sub clock signals CK1B and CK2B. During this period, both CK1B and CK2B are at a high level, and the first discharge switch S1 and the second discharge switch S2 between the first terminal A and the third terminal C are turned on and the first discharge switch S2 is turned on. The one terminal A is short-circuited with the third terminal C, whereby the charge stored in the parasitic capacitor between the first terminal A and the third terminal C is removed.

  FIG. 5d is a schematic diagram of the signals in the circuit shown in FIG. 5a. In FIG. 5d, CK is a clock signal and Vos is an offset voltage signal of the magnetic sensor 200, which can be considered constant at any point in time of the clock signal period. Depends on specific properties. Vin and −Vin are ideal magnetic field signals output by the first chopping switch in the first half cycle and the second half cycle of the clock signal CK, that is, ideal outputs of the Hall plate 200 that are not disturbed by the offset signal, respectively. is there. As described above, during the first half cycle of the clock signal CK, the terminals A and C are electrically connected to the first power and ground, respectively, and the terminals B and D are electrically connected to the output terminal. During the second half cycle of the clock signal CK, the terminals B and D are electrically connected to the first power and ground, respectively, and the terminals A and C are electrically connected to the output terminal. During the first and second half cycles of the clock signal CK, the ideal magnetic field signal output by the first chopping switch has the same magnitude and the opposite direction. Vout is an output signal of the first chopping switch, and is a signal obtained by superimposing the offset signal Vos and the ideal magnetic field signal Vin. In this way, the magnetic field signal is modulated in the high frequency region by the first chopping switch.

  In the embodiment of the present disclosure, the ideal magnetic field voltage signal output by the magnetic sensor 200 is very weak. In general, the ideal magnetic field signal is only a few tens of millivolts and the offset signal is close to 10 millivolts. Therefore, it is necessary to remove the offset signal and then amplify the ideal magnetic field signal.

  As shown in FIG. 3, the first amplifier unit 302 according to the embodiment amplifies the differential signal output by the first chopping switch 301 based on the control of the timing controller 500, and the first chopping switch 301. The magnetic field signal of the differential signal output by the above is demodulated to a low frequency region, and the demodulated differential signal is output. In any one of the above embodiments of the present disclosure, the sensitivity of the magnetic sensor 200 is required to be high, and the magnetic field signal output by the magnetic sensor 200 may be very weak, for example, only a few tens of millivolts. There are cases. Therefore, the magnetic field signal needs to be amplified, which facilitates the subsequent processing of the magnetic field signal by the first amplifier unit 302 amplifying the magnetic field signal of the magnetic sensor 200 as much as possible. Therefore, it is necessary to have a high gain. Optionally, the gain of the first amplifier unit is 100.

  In an embodiment of the present disclosure, the first amplifier unit 302 may be a chopping-amplifier unit as shown in FIG. That is, the first amplifier unit includes a first amplifier A1, a second chopping switch Z2, and a second amplifier A2 that are sequentially connected. The first amplifier A1 and the second amplifier A2 can amplify the input signal. The second chopping switch Z2 can demodulate the magnetic field signal of the differential signal output by the first chopping switch 301 to a low frequency region. The first amplifier A1 can be a folded cascode amplifier, and the second amplifier A2 can be a single-stage amplifier.

  Referring to the integrated circuit shown in FIG. 3, under the control of the first clock signal, the first amplifier A1 and the second amplifier A2 are configured to amplify the input signal, and the second chopping switch Z2 is The magnetic field signal of the differential signal output by the first chopping switch 301 is demodulated to a low frequency region.

  In the embodiment of the present disclosure, the first amplifier A1 receives the pair of difference signals P1 and N1 output from the first chopping switch 301 and outputs a pair of difference signals. The second chopping switch Z2 directly outputs the pair of difference signals output by the first amplifier A1 in the first half cycle of each clock cycle, and the first chopping switch Z2 outputs the first difference signal in the second half cycle of each clock cycle. The two differential signals output by the amplifier A1 are exchanged, and the exchanged differential signal is output. The output signals of the second chopping switch Z2 are defined as P2 and N2.

  As shown in FIG. 3, after the previous signal processing, the switched capacitor filter module 303 according to the embodiment of the present disclosure performs the difference signal output by the first amplifier unit 302 under the control of the timing controller 500. Are sampled, the offset of the sample signal is removed to obtain a differential signal, the differential signal is amplified, and the amplified differential signal is output. Optionally, in an embodiment of the present disclosure, the sampling frequency of the switch capacitor filter module 303 can be the same as the chopping frequency of the first chopping switch, i.e. the first output by the timing controller. The frequencies of the clock signal and the second clock signal are the same. The differential signal output by the first amplifier unit 302 includes a first sub differential signal and a second sub differential signal.

  In the embodiment of the present disclosure, the switch capacitor filter module may be a switch capacitor filter module as shown in FIG. The switch capacitor filter module 303 includes a first switch capacitor filter SCF1, a second switch capacitor filter SCF2, a third switch capacitor filter SCF3, and a fourth switch capacitor filter SCF4. The first switch-capacitor filter SCF1 and the second switch-capacitor filter SCF2 sample the differential signal output by the first amplifier unit during the first half cycle as a first sample signal. The third switch-capacitor filter SCF3 and the fourth switch-capacitor filter SCF4 are configured to sample the difference signal output by the first amplifier unit during the second half cycle as the second sample signal. Composed.

  The first switch capacitor filter SCF1 and the second switch capacitor filter SCF2 receive the first sub-difference signal and the second sub-difference signal output by the first amplifier unit 302 during the previous half cycle, Each is configured to sample as a first sub-sample signal and a second sub-difference signal. The third switch-capacitor filter SCF3 and the fourth switch-capacitor filter SCF4 receive the first sub-difference signal and the second sub-difference signal output by the first amplifier unit 302 during the subsequent half cycle, Each is configured to sample as a third sub-sample signal and a fourth sub-sample signal.

  The first switch-capacitor filter SCF1 and the second switch-capacitor filter SCF2 receive the difference signals P2 and N2, respectively, during the first half cycle, the first sub-sample signal P2A and the second sub-sample signal. Sample as N2A. The third switch-capacitor filter SCF3 and the fourth switch-capacitor filter SCF4 receive the difference signals P2 and N2, respectively, during the second half period, the third sub-sample signal P2B and the fourth sub-sample signal. Sample as N2B.

  The offset is removed by adding the first subsample signal to the third subsample signal, and the offset is removed by adding the second subsample signal to the fourth subsample signal. As shown in FIG. 7a, the switched capacitor filter module is configured to remove the offset by adding the first sample signal to the second sample signal to obtain a difference signal and amplify the difference signal. Further, an adder 303b is further included. Specifically, the adder 303b adds the first subsample signal P2A to the third subsample signal P2B to remove the offset, and the second subsample signal N2A to the fourth subsample signal N2B. An offset is removed by addition to obtain a differential signal, and the differential signal is amplified. The difference signals output by the adder are defined as P3 and N3. Optionally, the adder according to an embodiment of the present disclosure is a transconductance amplifier with a gain of two.

  As shown in FIG. 7b, which is a structural diagram of an adder according to the present disclosure, the adder includes an operational amplifier A ′, a first voltage-current converter M1, a second voltage-current converter M2, and a third voltage. -Including a current converter M3. Each of the voltage-to-current converters is connected to a current source and includes two metal oxide semiconductor (MOS) transistors. In the case of the first voltage-current converter M1, the gate of one MOS transistor receives the sample signal P2A, and the output terminal of this MOS transistor is electrically coupled to the non-inverting terminal of the operational amplifier A ′, The gate of the MOS transistor is configured to receive the sample signal N2A, and the output terminal of the other MOS transistor is electrically coupled to the inverting terminal of the operational amplifier A ′. In the case of the second voltage-current converter M2, the gate of one MOS transistor is configured to receive the sample signal P2B, and the output terminal of this MOS transistor is connected to the non-inverting terminal of the operational amplifier A ′, The MOS transistor can receive the sample signal N2B, and the output terminal of the other MOS transistor is connected to the inverting terminal of the operational amplifier A ′. In the case of the third voltage-current converter M3, the gate of one MOS transistor can receive the differential signal N3 output from the operational amplifier A ′, and the output terminal of this MOS transistor is connected to the operational amplifier A ′. The other MOS transistor is electrically coupled to the non-inverting terminal, and the gate of the other MOS transistor can receive the differential signal P3 output by the operational amplifier A ′. The output terminal of this MOS transistor is the inverting terminal of the operational amplifier A ′. Connected to. The voltage-current converter of the adder converts the input sample signal into a current, and removes the offset by adding the current. The current is amplified by the operational amplifier of the adder and then output. Preferably, a source degeneration resistor is placed at the input of the adder to ensure that the MOS transistor of the voltage-current converter operates in the saturation region. That is, as shown in FIG. 7b, the series resistor R ′ is electrically connected between the source electrodes of the two MOS transistors of the voltage-current converter, and the MOS transistor in the voltage-current converter is saturated. Guarantee to work with.

  In addition, the signal processing unit further includes a second amplifier unit 305, which is connected between the switched capacitor filter module 303 and the converter 304, so as to amplify the differential signal output by the adder. Composed. The second amplifier unit outputs amplified differential signals P3 and N3. In an embodiment, the second amplifier unit is a programmable gain amplifier with a gain of 5.

  In the embodiment, the total amplification gain of the first amplifier unit, the adder, and the second amplifier with respect to the amplification of the magnetic field signal is in the range of 800 to 2000 including both ends, and preferably 1000. In other embodiments, the magnetic field signal can be amplified with the required gain by setting different gains for the first amplifier unit, the adder and the second amplifier unit.

  As shown in FIG. 3, after being processed by the switch capacitor filter module and the second amplifier unit, the differential signal needs to be converted to a magnetic field signal by the signal processing unit 300 to control the output post-natal circuit. There is. FIG. 8 shows a structural diagram of a transducer according to an embodiment of the present disclosure. The converter includes a first comparator C1, a second comparator C2, and a latch logic circuit S.

  The first comparator C1 and the second comparator C2 are connected to a pair of differential reference voltages Vh and Vl and a pair of differential signals P3 and N3 output by the second amplifier unit, respectively. The pair of differential reference voltages of the first comparator C1 and the pair of differential reference voltages of the second comparator C2 are connected in reverse. The first comparator C1 is configured to compare the voltage signal output by the second amplifier unit with the high threshold Rh, and the second comparator C2 is the voltage signal output by the second amplifier unit. Is compared to the low threshold Rl. The output terminals of the first comparator C1 and the second comparator C2 are connected to the input terminal of the latch logic circuit S.

  As shown in FIG. 9, the first comparator C1 compares the voltage signal output by the second amplifier unit with the high threshold Rh, or the strength of the external magnetic field and the predetermined operating point Bop. Is configured to output the result of the comparison between The second comparator C2 shows the result of the comparison between the voltage signal output by the second amplifier unit and the low threshold value Rl, or the result of the comparison between the strength of the external magnetic field and the predetermined release point Brp. Configured to output.

  The latch logic circuit S indicates that the comparison result output by the first comparator C1 indicates that the voltage signal output by the second amplifier unit is higher than the high threshold Rh, or the strength of the external magnetic field is a predetermined operating point Bop. The signal processing unit 300 is configured to output a signal at a first level (eg, high level) indicating the magnetic polarity of the external magnetic field.

  The latch logic circuit S indicates that the comparison result output by the second comparator C2 indicates that the voltage signal output by the second amplifier unit is lower than the low threshold value Rl or the strength of the external magnetic field is a predetermined release point Brp. To indicate that the signal processing unit 300 outputs a signal at a second level (low level) opposite the first level, representing the magnetic polarity of another type of external magnetic field. Configured.

  In the latch logic circuit S, the comparison result output by the first comparator C1 and the second comparator C2 is such that the voltage signal output by the second amplifier unit is lower than the high threshold Rh and higher than the low threshold Rl. Or when the strength of the external magnetic field does not reach the predetermined operating point Bop and indicates that it has reached the predetermined release point Brp, the signal processing unit 300 is output in the original output state. .

  The second clock signal output from the timing controller to the latch logic circuit S is delayed for a second predetermined time, for example, 5 nanoseconds, with respect to the third clock signal to avoid the switching point of the switch-capacitor filter. The signal process of the signal processing unit according to an embodiment of the present disclosure will be described in detail with reference to FIG. The left part of FIG. 10 shows the difference signal output by each module under the control of the clock signal, and the right part of FIG. 10 shows a schematic diagram of the signal corresponding to the difference signal in the frequency domain.

From the above description, it can be seen that the output signal Vout of the first chopping switch is a superposition of the offset signal Vos and the ideal magnetic field signal Vin and is equal to the difference between the difference signals P1 and N1. The difference signals P1 and N1 have the same magnitude and different directions. From the above description, it can be seen that over the first and second half cycles of the clock signal CK1, the ideal magnetic field voltage signal output by the first chopping switch has the same magnitude and different directions. As shown in the left part of FIG. 10, the signal P1 is represented as P1A and P1B in the first and second half periods of the clock signal, respectively, and the signal N1 is the first and second half periods of the clock signal. Are represented as N1A and N1B, respectively. P1A, P1B, N1A and N1B are respectively
P1A = (Vos + Vin) / 2; P1B = (Vos−Vin) / 2
N1A = −P1A = − (Vos + Vin) / 2; N1B = −P1B = − (Vos−Vin) / 2
Represented as:

In order to facilitate understanding, the coefficient 1/2 of the difference signal is omitted in the following description. A pair of difference signals P1 ′ and N1 ′ are input to the second chopping switch via the first amplifier. The signal P1 ′ is represented as P1A ′ and P1B ′ in the first and second half periods of the clock signal, respectively, and the signal N1 ′ is N1A ′ and N1B ′ in the first and second half periods of the clock signal, respectively. Represented as: Due to the bandwidth limitation of the first amplifier A1, the differential signal output through the first amplifier A1 is a triangular wave differential signal. The following equation is just a signal form. The signals are P1A ′ = A (Voff + Vin) / 2; P1B ′ = A (Voff−Vin) / 2, respectively.
N1A ′ = − P1A ′ = − A (Voff + Vin) / 2; N1B ′ = − P1B ′ = − A (Voff−Vin) / 2
Represented as:

  A is the gain of the first amplifier, and Voff is the offset of the output signal of the first amplifier, which is equal to the sum of the intrinsic offset Vos of the magnetic sensor 200 and the offset of the first amplifier. The offset Voff is variable due to the bandwidth limitation of the first amplifier A1. In order to facilitate understanding, the difference signal coefficient and the amplifier amplification coefficient are omitted in the following description.

The second chopping switch Z2 directly outputs a pair of difference signals in the first half cycle of each clock cycle, exchanges the difference signals in the second half cycle of each clock cycle, and exchanges the difference signal. Is configured to output. The differential signals output by the second chopping switch are represented as P2 and N2. Signal P2 is represented as P2A and P2B in the first and second half cycles of the clock signal, and signal N2 is represented as N2A and N2B in the first and second half cycles of the clock signal. The outputs of signals P2 and N2 are respectively
P2A = P1A ′ = (Voff + Vin); P2B = N1B ′ = − (Voff−Vin)
N2A = N1A ′ = − (Voff + Vin); N2B = P1B ′ = (Voff−Vin)

  The four switch capacitor filters of the switch capacitor filter module 303 sample each signal included in the difference signals P2 and N2 in the first and second half periods of each clock period, respectively, and two pairs of samples Output a signal. That is, the pair of sample signals acquired by the switch capacitor filter module includes P2A and P2B, and the other pair of sample signals acquired by the switch capacitor filter module includes N2A and N2B.

The four sample signals are input to the adder, and the adder outputs P3 and N3. The adder adds two pairs of each sample signal two pairs and outputs P3 and N3, where P3 = P2A + P2B = (Voff + Vin) + (− (Voff−Vin)) = 2Vin; and N3 = N2A + N2B = − (Voff + Vin) + (Voff−Vin) = − 2Vin
It is.

  It can be seen that the signals P3 and N3 output by the adder include only the amplified ideal magnetic field voltage signal and the offset signal is removed.

  Further, the magnetic sensor integrated circuit according to an embodiment of the present disclosure further includes a counter 306 connected to the converter 304. The counter can output the time detection signal (that is, the difference signal) output by the converter 304 after counting for a predetermined time. The output of the magnetic field detection signal is delayed for a predetermined time (for example, 50 microseconds) by the count of the counter 306, thereby ensuring a sufficient response time of the entire circuit.

  Based on the above embodiment, in the embodiment of the present disclosure, the output control circuit 400 includes a first switch and a second switch. The first switch and the output port are connected in a first current path, and the second switch and the output port are connected in a second current path in a direction opposite to the direction of the first current path. . The first switch and the second switch are selectively switched under the control of the magnetic field detection signal. Optionally, the first switch is a diode and the second switch is a diode or transistor, which is not limited herein and depends on the situation.

  The output control circuit 400 can control the magnetic sensor integrated circuit to operate at least in the first state or the second state. In the embodiment, the first state can be a current flow from the output port 2 to the outside, and the second state can be a current flow from the outside to the output port 2. The output control circuit 400 is powered by the DC voltage at the second output terminal V2 of the full wave rectifier bridge 110. Specifically, the magnetic sensor integrated circuit can operate in a first state where load current flows out of the output port 2, or can operate in a second state where load current flows into the output port, Or it can operate alternately in the first state and the second state. Accordingly, in another embodiment of the present disclosure, the output control circuit 400 can be further configured to respond to the control signal under predetermined conditions. The integrated circuit operates in at least one of a first state in which the load current flows out from the output port 2 and a second state in which the load current flows into the output port 2 from the outside. If the predetermined condition is not satisfied, the integrated circuit operates in the third state in which the operation in the first state or the second state is prevented. In a preferred embodiment, the appearance frequency of the third state is directly proportional to the frequency of the AC power.

  In the magnetic sensor integrated circuit according to the embodiments of the present disclosure, the type of the third state of the output control circuit 400 is as long as the output control circuit 400 is prevented from entering the first state or the second state. Can be configured on demand. For example, when the output control circuit 400 is operating in the third state, the output control circuit 400 does not respond to the magnetic field detection signal (this can be understood as being unable to acquire the magnetic field detection signal). Or the current at output port 2 is much smaller than the load current (eg, less than a quarter of the load current, in which case the current can be substantially omitted relative to the load current).

  The counter 306 can start counting in response to obtaining a predetermined trigger signal. When the count time reaches a predetermined time, this indicates that the magnetic sensor integrated circuit satisfies a predetermined condition, and the magnetic sensor integrated circuit starts operation. Specifically, the predetermined trigger signal may be generated when a specified voltage in the magnetic sensor integrated circuit increases and reaches a predetermined threshold value. In the embodiment, the specified voltage may be a supply voltage of the signal processing unit. In the third state, the output control circuit 400 enters the first state or the second state after the counter 306 has obtained a predetermined trigger signal and then counted for a predetermined time, for example, 50 microseconds.

  In the embodiment of the present disclosure, as shown in FIG. 11, the first switch 401 and the second switch 402 are a pair of complementary semiconductor switches. The first switch 401 is turned on when a low level is applied, and the second switch 402 is turned on when a high level is applied. The first switch 401 and the output port 2 are connected in the first current path, and the second switch 402 and the output port 2 are connected in the second current path. The control ends of the first switch 401 and the second switch 402 are both connected to the signal processing unit 300. The current input terminal of the first switch 401 is connected to a high voltage (for example, DC power), the current output terminal of the first switch 401 is connected to the current input terminal of the second switch 402, and the second switch A current output terminal 402 is connected to a low voltage (for example, a ground terminal). When the magnetic field detection signal output by the signal processing unit 300 is at a low level, the first switch 401 is turned on while the second switch 402 is turned off, and the load current is changed from the high voltage side to the first voltage. It flows out through the switch 401 and the output port 2. When the magnetic field detection signal output by the signal processing unit 300 is at a high level, the second switch 402 is turned on while the first switch 401 is turned off, and the load current flows into the output port 2 from the outside. And flows through the second switch 402. In the example shown in FIG. 11, the first switch 401 is a positive channel metal oxide semiconductor field effect transistor (P-type MOSFET), and the second switch 402 is a negative channel metal oxide semiconductor field effect transistor (N type MOSFET). ). In other embodiments, the first and second switches can be other types of semiconductor switches, such as other junction field effect transistors (JFETs) and metal semiconductor field effect transistors (MESFETs). It can be understood that it can be a field effect transistor.

  In another embodiment of the present disclosure, as shown in FIG. 12, the first switch 401 is turned on when a high level is applied, and the second switch 402 is a unidirectional conducting diode. The control end of the first switch 401 and the cathode of the second switch 402 are connected to the output end of the converter of the signal processing unit 300. The current input terminal of the first switch 401 is electrically connected to the output terminal of the rectifier circuit, and the current output terminal of the first switch 401 is electrically connected to the anode of the second switch 401 and the output port 2. Is done. The first switch 401 and the output port 2 are electrically connected in the first current path, and the output port 2, the second switch 402 and the signal processing unit 300 are electrically connected in the second current path. Connected. When the magnetic field detection signal output by the signal processing unit 300 is at a high level, the first switch 401 is turned on while the second switch 402 is turned off, and the load current is transferred from the rectifier circuit to the first switch. It flows to the outside through 401 and the output port 2. When the magnetic field detection signal output by the signal processing unit 300 is at a low level, the second switch 402 is turned on while the first switch 401 is turned off, and the load current flows into the output port 2 from the outside. And flows through the second switch 402. It should be understood that in other embodiments of the present disclosure, the first switch 401 and the second switch 402 can have other structures, which are not limited herein and depend on the situation. it can.

  In another embodiment of the present disclosure, the output control circuit includes a first current path through which current flows from the output port to the outside, a second current path through which current flows from the output port to the inside, a first current path, and And a switch connected to one of the second current paths. The switch is controlled by a magnetic field detection signal output by the signal processing unit, and selectively turns on the first current path and the second current path. Optionally, no switch is disposed in the other current path of the first current path and the second current path.

  As an implementation, as shown in FIG. 13a, the output control circuit 400 includes a unidirectional conductive switch 403 electrically connected to the output port 2 in the first current path. The current input terminal of the unidirectional conductive switch 403 can be connected to the output terminal of the signal processing unit 300. The output end of the signal processing unit 300 can be connected to the output port 2 via a resistor R1 in a second current path opposite to the direction of the first current path. The unidirectional conductive switch 403 is turned on when the magnetic field detection signal is at a high level, and the load current flows to the outside through the unidirectional conductive switch 403 and the output port 2. The unidirectional conductive switch 403 is turned off when the magnetic field detection signal is at a low level, and the load current flows from the outside to the output port 2 and flows through the resistor R1 and the signal processing unit 300. Alternatively, the resistor R1 in the second current path is replaced with a unidirectional conductive switch connected in reverse parallel to the unidirectional conductive switch 403, and the load current flowing out from the output port flows into the output port. It can be balanced with the load current.

  In another implementation, as shown in FIG. 13b, the output control circuit 400 includes diodes D1 and D2, and resistors R1 and R2. The diodes D1 and D2 are connected in series in the reverse direction between the output end of the signal processing unit 300 and the output port 2. Resistor R1 is connected in parallel with diodes D1 and D2. Resistor R2 is connected between power Vcc and the common end of diodes D1 and D2. The cathode of the diode D1 is connected to the output terminal of the signal processing unit 300. The diode D1 is controlled by the magnetic field detection information. When the magnetic detection signal is at a high level, the diode D1 is turned off, and the load current flows from the output port Pout to the outside through the resistor R2 and the diode D2. When the magnetic field detection signal is at a low level, the load current flows from the outside into the output port Pout and flows through the resistor R1 and the signal processing unit 300.

  A magnetic field integrated circuit according to embodiments of the present disclosure will be described in the context of a particular application as follows.

  As shown in FIG. 14, an electric motor assembly is further provided according to an embodiment of the present disclosure. The electric motor assembly includes an electric motor 2000 powered by AC power 1000, a bidirectional conductive switch 3000 connected in series to the electric motor 2000, and a magnetic sensor integrated circuit according to any one of the above embodiments of the present disclosure. 4000. The output port of the magnetic sensor integrated circuit 4000 is electrically connected to the control end of the bidirectional conductive switch 3000. Preferably, the bidirectional conductive switch 3000 may be a triode AC switch (TRIAC). It can be appreciated that the bi-directional conductive switch can be implemented with other suitable types of switches. For example, a bidirectional conductive switch can include two silicon controlled rectifiers connected in anti-parallel and a corresponding control circuit. The two silicon controlled rectifiers are controlled by the control circuit in a predetermined manner based on the output signal output from the output port of the magnetic sensor integrated circuit. Preferably, the electric motor further includes a voltage drop circuit 5000 for providing a reduced voltage to the magnetic sensor integrated circuit 4000 by reducing the voltage of the AC power 1000. The magnetic sensor integrated circuit 4000 is placed near the rotor of the electric motor 2000 to detect changes in the rotor magnetic field.

  Based on the above embodiment, in the embodiment of the present disclosure, the electric motor is a synchronous electric motor. It can be appreciated that the magnetic sensor integrated circuit according to the present disclosure applies not only to synchronous electric motors, but also to other types of permanent magnet electric motors such as DC brushless motors. As shown in FIG. 15, the synchronous motor includes a stator and a rotor 1001 that rotates with respect to the stator. The stator includes a stator core 1002 and a stator winding 1006 wound around the stator core 1002. The stator core 1002 can be made of a soft magnetic material such as pure iron, cast iron, cast steel, electric steel, or silicon steel. The rotor 1001 includes a permanent magnet. When the stator winding 1006 is connected in series with AC power, the rotor 1001 rotates at a constant speed (60 f / p) rotation / min, where f is the frequency of the AC power. , P is the number of pole pairs of the rotor. In the embodiment, the stator core 1002 has two pole portions 1004 arranged to face each other. Each of the pole portions has a polar arc surface 1005. The outer surface of the rotor 1001 faces the magnetic pole arc surface, and a substantially uniform air gap is formed between them. The basically uniform air gap in this disclosure is that the majority of the air gap between the stator and the rotor is uniform and the small portion of the air gap between the stator and the rotor is non-uniform. It shows that. Preferably, a concave start groove 1007 is disposed on the pole arc surface 1005 of the pole portion of the rotor. Portions other than the starting groove 1007 on the magnetic pole arc surface 1005 are concentric with the rotor. With the above configuration, a non-uniform magnetic field can be formed, and this is because the rotor polar axis S1 forms an angle with respect to the central axis S2 of the pole portion of the stator when the rotor is not rotating. Since it ensures tilting, the rotor can have a starting torque each time the electric motor is powered under the influence of the integrated circuit. The rotor polar axis S1 is a boundary between two magnetic poles of the rotor having different polarities. The central axis S2 of the stator pole portion 1004 is a connecting line passing through the centers of the two pole portions 1004 of the stator. In an embodiment, the stator and the rotor each have two magnetic poles. In other embodiments, the number of stator poles may differ from the number of rotor poles, and it will be understood that the stator and rotor may have more poles, eg, 4 and 5 poles. can do.

  Preferably, the magnetic sensor integrated circuit 4000 operates when the AC power 1000 is operating in a positive half cycle and the magnetic sensor detects that the magnetic field of the permanent magnet rotor has the first polarity, or AC If the power 1000 is operating in a negative half cycle and the magnetic sensor detects that the magnetic field of the permanent magnet rotor has a second polarity opposite to the first polarity, the bidirectional conductive switch 3000 is turned on. Configured to turn on. The magnetic sensor integrated circuit 4000 operates when the AC power 1000 is operated in a negative half cycle and the permanent magnet rotor has the first polarity, or when the AC power 1000 is operated in a positive half cycle, If the permanent magnet rotor has the second polarity, the bidirectional conductive switch 3000 is turned off.

  Based on the above embodiment, in the embodiment of the present disclosure, the magnetic sensor integrated circuit 400 operates with the AC power 1000 in a positive half cycle, and the magnetic sensor 200 has the first magnetic field of the permanent magnet rotor. The AC power 1000 is operating in a negative half cycle and the magnetic sensor (including the magnetic sensor and the signal processing unit connected thereto) is a permanent magnet rotor Is detected to have a second polarity opposite to the first polarity, the drive current is controlled to flow between the output port and the bidirectional conductive switch 3000, thereby the bidirectional conductive switch 3000. The AC power 1000 is operating in a negative half cycle and the permanent magnet rotor has a first polarity, or the AC power 1000 is a positive half cycle. Operation and, and when the permanent magnet rotor having a second polarity, arranged to prevent the driving current flows between the output port and the bidirectional conductive switch 3000.

  Preferably, when the output control circuit 400 detects that the signal output by the AC power 1000 is in a positive half cycle and the magnetic sensor detects that the magnetic field of the permanent magnet rotor is the first polarity, Is controlled to flow from the integrated circuit to the bidirectional conductive switch 3000, the signal output by the AC power 1000 is in a negative half cycle, and the magnetic sensor has a magnetic field of the permanent magnet rotor of the first polarity. When it is detected that the second polarity is the reverse of the above, the current is controlled to flow from the bidirectional conductive switch 3000 to the integrated circuit. If the permanent magnet rotor has the first magnetic polarity and the AC power is in the positive half cycle, current can flow out of the integrated circuit over all or part of the positive half cycle, and the permanent magnet rotation It can be appreciated that if the child has a second magnetic polarity and the AC power is in a negative half cycle, current can flow into the integrated circuit over all or part of the negative half cycle.

  In a preferred embodiment of the present disclosure, the rectifier circuit 100 has a circuit as shown in FIG. 2, and the output control circuit 400 has a circuit as shown in FIG. The current input terminal of the first switch 401 of the output control circuit 400 is connected to the second output terminal V2 of the full-wave rectifier bridge 110, and the current output terminal of the second switch 402 is connected to the ground of the full-wave rectifier bridge 110. Connected to the end. When the signal output by the AC power 1000 is in a positive half cycle and the magnetic sensor outputs a low level signal, the first switch 401 is turned on in the output control circuit 400 and the second switch 402 is The current is turned off, the AC power 1000, the electric motor 2000, the first input of the magnetic sensor integrated circuit 4000, the voltage drop circuit (not shown), the second diode 112 of the full wave rectifier bridge 110 and the output control. The first switch 401 of the circuit 400 sequentially flows and flows from the output port to the bidirectional conductive switch 3000. When the bidirectional conductive switch 3000 is turned on, the series branch formed by the voltage drop circuit 5000 and the magnetic sensor integrated circuit 4000 is short-circuited, and the magnetic sensor integrated circuit 4000 stops the output because there is no supply voltage, and the bidirectional switch Since the current flowing through the two anodes of the conductive switch 3000 is sufficiently large (greater than the holding current of the bidirectional conductive switch 3000), there is a drive current between the control pole of the bidirectional conductive switch 3000 and the first anode. The bidirectionally conductive switch 3000 remains on in the non-flowing state. When the signal output from the AC power 1000 operates in a negative half cycle and the magnetic field detection signal output from the magnetic sensor is at a high level, the first switch 401 is turned off in the output control circuit 400. The second switch 402 is turned on, and the current flows out of the AC power 1000 and flows into the output port through the bidirectional conductive switch 3000. The second switch 402 of the output control circuit 400, the full-wave rectifier The AC power 1000 is returned to the first diode 111 of the bridge 110, the first input terminal of the magnetic sensor integrated circuit 4000, and the electric motor 2000. Similarly, when the bidirectional conductive switch 3000 is on, the magnetic sensor integrated circuit 4000 is short-circuited and therefore stops outputting, and the bidirectional conductive switch 3000 may remain on. When the signal output by the AC power 1000 operates in a positive half cycle and the magnetic field detection signal output by the magnetic sensor is at a high level, or the signal output by the AC power 1000 operates in a negative half cycle When the magnetic detection signal output from the magnetic sensor is at a low level, the first switch 401 and the second switch 402 of the output control circuit 400 are turned off, and the bidirectional conductive switch 3000 is turned off. Therefore, the output control circuit 400 can control the integrated circuit based on the polarity change of the AC power 1000 and the difference signal to switch the bidirectional conductive switch 3000 on and off in a predetermined manner. In this way, the manner in which power is supplied to the stator winding 1006 is controlled, and the changing magnetic field generated by the stator matches the magnetic field position of the rotor, thereby dragging the rotor in a single direction. This ensures that the rotor rotates in a certain direction each time the electric motor is turned on.

  In the embodiment of the present disclosure, the magnetic field detection signal is a switch type detection signal. In the steady state of the electric motor, the switching frequency of the switch type detection signal is twice the frequency of the AC power.

  In the above embodiments, it can be understood that the magnetic sensor integrated circuit according to the present disclosure is described only in relation to possible applications, and the magnetic sensor of the present disclosure is not limited thereto. For example, the magnetic sensor can be applied not only to driving an electric motor but also to other uses involving magnetic field detection.

  In a motor according to another embodiment of the present disclosure, the motor can be connected in series with a bidirectional conductive switch between the two ends of the external AC power. The first series branch formed by the electric motor and the bidirectional conductive switch is connected in parallel with the second series branch formed by the voltage drop circuit and the magnetic sensor integrated circuit. The output port of the magnetic sensor integrated circuit is connected to a bidirectional conductive switch and controls the bidirectional conductive switch to turn on and off in a predetermined manner, thereby controlling the power supply to the stator windings. .

  Accordingly, an application apparatus is further provided according to an embodiment of the present disclosure. The application device includes a motor powered by AC power, a bidirectional conductive switch connected in series with the electric motor, and a magnetic sensor integrated circuit according to any of the above embodiments. The output end of the magnetic sensor integrated circuit is electrically connected to the control end of the bidirectional conductive switch. Optionally, the application device can be a pump, fan, household appliance, vehicle, etc., where the household appliance can be, for example, a washing machine, range hood, ventilator, etc.

  The above description of the disclosed embodiments enables those skilled in the art to achieve or use the present disclosure. Various modifications to the embodiments will be apparent to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure is not limited to the embodiments disclosed herein, but establishes the widest scope consistent with the principles and novel features disclosed herein.

2: Output port 11, 12: Input port 13: Power 14, 15: Discharge branch 110: Full-wave rectifier bridge 111, 112, 113, 114: Diode 120: Voltage stabilization unit 121, 124: Zener diode 122, 123: Resistor 125: Transistor 200: Magnetic sensor 301: First chopping switch 303b: Adder 400: Output control circuit 401: First switch 402: Second switch 403: Unidirectional conductive switch 1000: AC power 2000: Electricity Motor 4000: magnetic sensor integrated circuit A1: first amplifier A2: second amplifier A ′: operational amplifier Bop: operating point Brp: release point C1, C2: comparator CK1: fourth subclock signal CK2: third Subclock signal CK1B: second subclock signal CK2B: first subclock signal Block signal M1, M3, M3: Voltage-current converter Rh: High threshold Rl: Constant threshold S: Latch logic circuit SCF1: First switch capacitor filter SCF2: Second switch capacitor filter SCF3: Third switch Capacitor filter SCF4: Fourth switch Capacitor filter Vin: Ideal magnetic field signal Voff: First amplifier offset Vos: Magnetic sensor specific offset Vout: First chopping switch output signal Z2: Second chopping switch

Claims (10)

A magnetic sensor integrated circuit,
A magnetic sensor that receives a constant current and outputs a differential signal;
A signal processing unit for converting the differential signal into a magnetic field detection signal;
Based on at least the magnetic field detection signal, the magnetic sensor integrated circuit includes a first state in which current flows from the output port of the magnetic sensor integrated circuit to the outside and a second state in which current flows from the outside to the output port. An output control circuit that controls to operate in at least one of the following states:
A magnetic sensor integrated circuit comprising:   The rectifier circuit further includes a rectifier circuit for converting external power into DC power, the rectifier circuit including a full-wave rectifier bridge and a voltage stabilization unit, and the full-wave rectifier bridge converts the external AC power into DC voltage. The power is supplied to the output control circuit, and the voltage stabilization unit converts the DC voltage output by the full-wave rectifier bridge into a low voltage DC and supplies the signal processing unit with power. The magnetic sensor integrated circuit according to claim 1.   The differential signal includes a magnetic field signal and an offset signal, and the signal processing unit modulates the magnetic field signal and the offset signal to a high frequency region and a baseband frequency, respectively, and the first For amplifying the differential signal output by the chopping switch, demodulating the magnetic field signal of the differential signal output by the first chopping switch to the baseband frequency, and outputting the demodulated differential signal The magnetic sensor integrated circuit according to claim 1, further comprising: a first amplifier unit. The signal processing unit further includes a switch capacitor filter module, and the switch capacitor filter module includes a first switch capacitor filter, a second switch capacitor filter, a third switch capacitor filter, and a second switch capacitor filter. 4 switch capacitor filters,
The first switch capacitor filter and the second switch capacitor filter sample the difference signal output by the first amplifier unit in a first half cycle as a first sample signal, and And the fourth switch capacitor filter samples the difference signal output from the first amplifier unit in the second half cycle as a second sample signal. The magnetic sensor integrated circuit according to claim 3.   The signal processing unit further includes a converter for converting the differential signal output by the switch capacitor filter module into the magnetic field detection signal and outputting the magnetic field detection signal to the output control circuit. The magnetic sensor integrated circuit according to claim 4, wherein the magnetic sensor integrated circuit is characterized in that:   A first clock signal is output to the first chopping switch and the first amplifier unit, a second clock signal is output to the switch capacitor filter module, and a third clock signal is output to the converter. A timing controller for outputting, wherein the second clock signal is delayed for a first predetermined time with respect to the first clock signal, and the second clock signal is the third clock signal The magnetic sensor integrated circuit according to claim 5, wherein the magnetic sensor integrated circuit is delayed by a second predetermined time with respect to the clock signal.   5. The switch capacitor filter module further comprises an adder for performing offset removal and amplification by adding the first sample signal to the second sample signal. The magnetic sensor integrated circuit as described.   The magnetic sensor integrated circuit according to claim 7, wherein the signal processing unit further includes a second amplifier for amplifying the differential signal output by the adder.   A motor assembly comprising: a motor supplied with AC power; and the magnetic sensor integrated circuit according to claim 1.   An application apparatus comprising the motor assembly according to claim 9.

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