JP2017227626A - Magnetic sensor integrated circuit, motor assembly and application apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a magnetic sensor integrated circuit to obtain an accurate magnetic field detection signal.SOLUTION: A magnetic sensor integrated circuit includes a rectifier circuit, a magnetic field detection circuit, and a timing controller. The rectifier circuit converts an external power into a DC power. The magnetic field detection circuit senses a polarity of an external magnetic field and outputs a magnetic detection signal; and the magnetic field detection circuit includes a first chopping switch, a first amplifier unit and a switched capacitor filter module. The timing controller outputs a first clock signal to the first chopping switch and the first amplifier unit, and outputs a second clock signal delayed for the first clock signal with a first predetermined time to the switched capacitor filter module.SELECTED DRAWING: Figure 1a

Description

The present disclosure relates to magnetic field detection, and more particularly to a magnetic sensor integrated circuit, a motor assembly, and an application device.

[0002] In modern industrial and electronic products, magnetic sensors such as Hall elements are widely used to induce physical field strength to measure physical parameters such as current, position and direction. Motors are an important field of application for magnetic sensors. In a motor, the magnetic sensor can serve as a rotor polarity position sensor.

In general, a magnetic sensor can only output a magnetic field detection signal. However, the magnetic field detection signal is weak and mixed with the offset of the magnetic sensor, and it is difficult to obtain an accurate magnetic field detection signal.

[0004] In a first aspect of the present disclosure, a magnetic sensor integrated circuit is provided, which includes a rectifier circuit that converts an external power source into a DC power source, and magnetic field detection that detects the polarity of the external magnetic field and outputs a magnetic detection signal. A magnetic field detection circuit comprising a magnetic sensor, a first chopping switch, a first amplifier unit, and a switched capacitor filter module, and a timing control device, the first chopping switch and the first amplifier unit And a timing control device for outputting a second clock signal delayed by a first predetermined time with respect to the first clock signal to the switched capacitor filter module.

[0005] The magnetic sensor integrated circuit further includes a converter, the timing control device outputs a third clock signal to the converter, and the second clock signal is a second clock signal with respect to the third clock signal. It is preferable to delay by a predetermined time.

[0006] The first predetermined time is preferably longer than the second predetermined time.

[0007] The first predetermined time is preferably ¼ period of the first clock signal.

[0008] Preferably, the first, second and third clock signals have the same frequency.

[0009] The frequencies of the first, second and third clock signals are preferably 100 kHz to 600 kHz including both ends.

[0010] Preferably, the first clock signal comprises at least two non-overlapping sub-clock signals, and the second clock signal comprises at least two non-overlapping sub-clock signals.

[0011] The differential signal output by the magnetic sensor includes a magnetic field signal and an offset signal, and the signal processing unit includes a first chopping switch that modulates the magnetic field signal and the offset signal to a high frequency region and a baseband frequency, respectively. preferable.

[0012] The motor assembly includes a motor powered by an AC power source and the magnetic sensor integrated circuit described above.

[0013] The application apparatus includes the motor assembly described above.

[0014] To make the technical solutions according to the embodiments of the present disclosure or in the prior art more apparent, the drawings according to the embodiments of the present disclosure will be briefly described below. Apparently, the drawings are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings from these drawings without creative work.

1 is a block diagram of a magnetic sensor integrated circuit according to an embodiment of the present disclosure. FIG. FIG. 1b is a time sequence diagram of a clock signal of the magnetic sensor integrated circuit of FIG. 1a. FIG. 3 is a circuit diagram of a rectifier circuit according to an embodiment of the present disclosure. FIG. 3 is a structural diagram of a magnetic sensor and a first chopping switch according to an embodiment of the present disclosure. 4 is a time sequence diagram of four sub-clock signals of the magnetic sensor and the first chopping switch shown in FIG. FIG. 3B is a schematic diagram of control signals for the discharge switch and the first chopping switch shown in FIG. 3A. FIG. 3b is a schematic signal diagram of the circuit shown in FIG. 3a. FIG. 3 is a schematic diagram of a first amplifier unit according to an embodiment of the present disclosure. 1 is a schematic diagram of a switched capacitor filter module according to an embodiment of the present disclosure. FIG. FIG. 6 is a schematic circuit diagram of the switched capacitor filter module of FIG. 5. FIG. 6b is a time sequence diagram of the clock signal of FIG. 6a. FIG. 3 is a schematic diagram of an adder according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram of a converter according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram of the principle for determining the polarity of a magnetic field according to an embodiment of the present disclosure. FIG. 6 is a schematic diagram of an output of a periodic clock signal according to an embodiment of the present disclosure. 1 is a schematic diagram of a magnetic sensor integrated circuit according to an embodiment of the present disclosure. FIG. FIG. 3 is a schematic circuit diagram of an output control circuit according to an embodiment of the present disclosure. FIG. 6 is a schematic circuit diagram of an output control circuit according to another embodiment of the present disclosure. FIG. 6 is a schematic circuit diagram of an output control circuit according to still another embodiment of the present disclosure. 1 is a schematic structural diagram of a circuit of a motor assembly according to an embodiment of the present disclosure. 1 is a schematic structural diagram of a synchronous motor according to an embodiment of the present disclosure.

[0036] The technical solutions of the embodiments of the present disclosure are clearly and completely illustrated in conjunction with the drawings of the embodiments of the present disclosure. Apparently, the described embodiments are merely a few rather than all of the embodiments of the present disclosure. Any other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of the present disclosure.

[0037] As described in the background art section, in the prior art, generally, the magnetic sensor integrated circuit can output only the magnetic field detection result, and an additional peripheral circuit is required to process the magnetic field detection result. The Thus, the entire circuit is expensive and unreliable.

[0038] In view of this, the disclosed embodiments provide a magnetic sensor integrated circuit, an electric motor assembly, and an application device, and extend the function of the conventional magnetic sensor integrated circuit to reduce the cost of the entire circuit. Improve the reliability of the whole circuit. A technical solution according to an embodiment of the present disclosure for achieving the above object will be described in detail in conjunction with FIGS.

[0039] FIG. 1a is a schematic structural diagram of a magnetic sensor integrated circuit according to an embodiment of the present disclosure. The magnetic sensor integrated circuit includes a rectifier circuit 100, a magnetic field detection circuit 200, and a timing control device 300.

The rectifier circuit 100 can convert an external power source into a DC power source and a power supply for the magnetic field detection circuit 200.

[0041] The magnetic field detection circuit 200 can detect the polarity of the external magnetic field and output a magnetic detection signal. In the embodiment, the magnetic field detection circuit 200 includes an electrically connected magnetic sensor 201, a first chopping switch 202, a first amplifier unit 203, a switched capacitor filter module 204, a second amplifier unit 205, and a converter. 206 in order.

The timing control device 300 outputs the first clock signal to the first chopping switch 202 and the first amplifier unit 203, outputs the second clock signal to the switched capacitor filter module 204, and outputs the third clock signal. The clock signal can be output to the converter 206. In an embodiment, the second clock signal is delayed by a first predetermined time with respect to the first clock signal, the second clock signal is delayed by a second predetermined time with respect to the third clock signal, The first predetermined time is longer than the second predetermined time.

[0043] In an embodiment, as shown in FIG. 1b, the first, second and third clock signals may have the same frequency. The first predetermined time can be 14 periods of the first clock signal, and the second predetermined time can be several nanoseconds, such as 5 nanoseconds. FIG. 1b only shows the time series of the first, second and third clock signals and does not show the true shape of the clock signal of the magnetic sensor integrated circuit.

[0044] In the embodiment of the present disclosure, the external power supply is supplied to the rectifier circuit via the input port, and the input port is electrically connected to the external power supply. 12 is included. In the embodiments of the present disclosure, the connection between the input port and the external power supply can be a direct connection or an indirect connection, which is not limited herein and needs to be designed based on the actual application. . In an embodiment of the present disclosure, the external power source received by the rectifier circuit is an AC power source. In addition, the constant current that is unaffected by temperature changes and received by the magnetic sensor can be supplied by a rectifier circuit, which is not limited herein.

[0045] In an embodiment of the present disclosure, the rectifier circuit 100 includes a full wave rectifier bridge and a voltage stabilization unit coupled to the output of the full wave rectifier bridge. The full wave rectifier bridge can convert an AC signal output by the AC power source into a DC signal, and the voltage stabilization unit can stabilize the DC signal output by the full wave rectifier bridge within a predetermined range. . FIG. 2 is a circuit diagram of a rectifier circuit according to an embodiment of the present disclosure, in which a full-wave rectifier bridge 110 includes a first diode 111 and a second diode 112 connected in series, and a third diode connected in series. The diode 113 and the fourth diode 114 are included. The first input terminal 11 is a common terminal between the first diode 111 and the second diode 112, and is electrically connected to the AC power supply VAC +, and the second input terminal 12 is a third diode. 113 is a common end between the fourth diode 114 and the fourth diode 114, and is electrically connected to the AC power supply VAC-.

The input terminal of the first diode 111 is electrically connected to the input terminal of the third diode 113 to form the first output terminal V 1 of the full-wave rectifier bridge 110, and the second diode 112. Are connected electrically to the output of the fourth diode 114 to form the second output V2 of the full-wave rectifier bridge 110. The second output terminal V2 outputs a DC voltage of about 16V. The output control circuit 400 is preferably powered by a DC voltage output by the second output terminal V2 of the full wave rectifier bridge 110.

In addition, the voltage stabilization unit 120 includes a Zener diode 121, a first resistor, which are electrically connected between the first output terminal V1 and the second output terminal V2 of the full-wave rectifier bridge 110. 122, a second resistor 123, a Zener diode 124, and a transistor 125. The anode of the Zener diode 121 and the anode of the Zener diode 124 are both connected to the first output V1 of the full wave rectifier bridge 110. Both the cathode of the Zener diode 121 and the first end of the first resistor 122 are coupled to the second output V2 of the full wave rectifier bridge 110. The second end of the first resistor 122 is connected to the first end of the second resistor 123 and the first end of the transistor 125. The second end of the second resistor 123 is electrically connected to the gate of the transistor 125 and the cathode of the Zener diode 124. The second end of transistor 125 and the anode of zener diode 124 each serve as two outputs of voltage regulator unit 120, ie, two outputs of the rectifier circuit. The output voltage of the first output terminal AVDD of the rectifier circuit is a DC voltage of about 5V, and the second output terminal AVSS is grounded.

As shown in FIG. 1, the input terminal of the magnetic sensor 201 is electrically connected to the output terminal of the rectifier circuit 100. The magnetic sensor 201 is configured to detect the polarity of the external magnetic field and output a magnetic difference signal to the first chopping switch 202. The magnetic difference signal can comprise a magnetic field signal and an offset signal. The first chopping switch 202 can modulate the magnetic field signal and the offset signal of the differential signal output by the magnetic sensor 201 to a high frequency region and a baseband frequency, respectively, under the control of the timing control device 300. Preferably, the frequency in the high frequency region is greater than 100 KHz and the baseband frequency is less than 200 Hz.

[0049] Reference is made to FIGS. 3a to 3c. FIG. 3a is a structural diagram of a magnetic sensor and a first chopping switch according to an embodiment of the present disclosure. FIG. 3b is a timing diagram of four sub-clock signals for the magnetic sensor and the first chopping switch shown in FIG. 3a. FIG. 3c is a schematic diagram of signal control of the discharge switch and the first chopping switch shown in FIG. 3a.

[0050] The magnetic sensor 201 includes four contact terminals. The magnetic sensor 201 includes a first terminal A and a third terminal C arranged on the opposite side, and a second terminal B and a fourth terminal D arranged on the opposite side. In the embodiment of the present disclosure, the magnetic sensor 201 is a Hall plate. The magnetic sensor 200 is driven by a first power supply 13 provided by the rectifier circuit 100. In the embodiment, the first power supply 13 is a constant current source that is not affected by a temperature change.

[0051] As shown in FIG. 3a, the first chopping switch 202 includes eight switches K1 to K8 electrically connected to four terminals. Specifically, the first chopping switch 202 includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, 7 switches K7 and an eighth switch K8. The first switch K1 is electrically connected between the first power supply 13 and the first terminal A. The second switch K2 is electrically connected between the first power supply 13 and the second terminal B. The third switch K3 is electrically connected between the ground terminal GND and the third terminal C. The fourth switch K4 is electrically connected between the ground terminal GND and the fourth terminal D. The fifth switch K5 is electrically connected between the first output terminal P and the fourth terminal D. The sixth switch K6 is electrically connected between the first output terminal P and the third terminal C. The seventh switch K7 is electrically connected between the second output terminal N and the second terminal B. The eighth switch K8 is electrically connected between the second output terminal N and the first terminal A. The first clock signal includes a first sub clock signal CK2B, a second sub clock signal CK1B, a third sub clock signal CK2, and a fourth sub clock signal CK1. The first switch K1 and the second switch K2 are controlled by the first sub clock signal CK2B and the second sub clock signal CK1B, respectively. The third switch K3 and the fourth switch K4 are controlled by the third sub clock signal CK2 and the fourth sub clock signal CK1, respectively. The fifth switch K5 and the sixth switch K6 are controlled by the third sub clock signal CK2 and the fourth sub clock signal CK1, respectively. The seventh switch K7 and the eighth switch K8 are controlled by the third sub clock signal CK2 and the fourth sub clock signal CK1, respectively.

[0052] To ensure the accuracy of the output signal, the first clock signal includes at least two non-overlapping sub-clock signals. The phase of the first sub clock signal CK2B is opposite to the phase of the third sub clock signal CK2, and the phase of the second sub clock signal CK1B is opposite to the phase of the fourth sub clock signal CK1. The third sub clock signal CK2 and the fourth sub clock signal CK1 are non-overlapping sub clock signals.

[0053] When the first terminal A is electrically connected to the first power source 13 and the third terminal C is electrically connected to the ground terminal GND, the second terminal B is connected to the second output. The fourth terminal D is electrically connected to the first output terminal P. The fourth terminal D is electrically connected to the terminal N. When the second terminal B is electrically connected to the first power supply 13 and the fourth terminal D is electrically connected to the ground terminal GND, the first terminal A is connected to the second output terminal N. The third terminal C is electrically connected to the first output terminal P. The first output terminal P outputs the differential signal P1, and the second output terminal N outputs the differential signal N1.

In addition to the magnetic sensor 201 and the first chopping switch 202 described, the magnetic sensor 201 includes a first discharge branch 14 connected between the first terminal A and the third terminal C, ie, A branch between the first terminal A and the third terminal C, and a second discharge branch 15 connected between the second terminal B and the fourth terminal D, ie, the second terminal B And a branch with the fourth terminal D. Before the first terminal A and the third terminal C serve as power input terminals, and the second terminal B and the fourth terminal D serve as output terminals for the magnetic field detection signal, the second discharge branch 15 is electrically conductive. become. Before the first terminal A and the third terminal C serve as the output terminals of the magnetic field detection signal and the second terminal B and the fourth terminal D serve as the power input terminals, the first discharge branch 14 is electrically conductive. become.

[0055] In a possible implementation, the first discharge branch 14 may include a first discharge switch S1 and a second discharge switch S2 that are electrically connected in series. The first discharge switch S1 and the second discharge switch S2 are controlled by the first sub clock signal CK2B and the second sub clock signal CK1B, respectively. The second discharge branch 15 includes a third discharge switch S3 and a fourth discharge switch S4 that are electrically connected in series. The third discharge switch S3 and the fourth discharge switch S4 are controlled by the first sub clock signal CK2B and the second sub clock signal CK1B, respectively.

[0056] When the first terminal A and the third terminal C serve as power input terminals, and the second terminal B and the fourth terminal D serve as output terminals of the magnetic field signal, the first sub-clock signal CK2B is During the time overlapping with the second sub clock signal CK1B, the first discharge switch S1 and the second discharge switch S2 are simultaneously turned on. When the first terminal A and the third terminal C serve as output terminals for the magnetic field signal, and the second terminal B and the fourth terminal D serve as power input terminals, the first sub-clock signal CK2B is used as the second output terminal. During the time overlapping with the sub clock signal CK1B, the third discharge switch S3 and the fourth discharge switch S4 are simultaneously turned on.

[0057] As shown in FIG. 3b, the four sub-clock signals are divided into two non-overlapping control signals, that is, the third sub-clock signal CK1 and the fourth sub-clock signal CK2, and two overlapping signals, that is, the second sub-clock signal. The sub clock signal CK1B and the first sub clock signal CK2B. CK1 is opposite to CK1B and CK2 is opposite to CK2B. Overlapping subclock signals CK1B and CK2B are both at a high level during the time that CK1B and CK2B overlap, ie, the time between the two dotted lines shown in FIG. 3b. The two non-overlapping subclock signals CK1 and CK2 and the two overlapping subclock signals CK1B and CK2B can have a frequency in the range of 100 KHz to 600 Hz including both ends, and the frequency is preferably 400 KHz. .

[0058] In the embodiment of the present disclosure, the eight switches included in the chopping switch 202 and the four discharge switches included in the discharge branch may each be a transistor. Furthermore, when CK1 is high, CK2B is high and CK2 and CK1B are low. In such a case in conjunction with FIG. 3c, the second terminal B and the fourth terminal D are electrically connected to the first power supply 13 and the ground terminal GND, respectively, and serve as a power input terminal. A switch between the terminal C and the first output terminal P is turned on, a switch between the first terminal A and the second output terminal N is turned on, and the first terminal A and the third terminal C are turned on. Serves as the output end of the magnetic field signal. The short time immediately after CK1 transitions from the high level to the low level, that is, the time between the first two dotted lines shown in FIG. 3b is the overlap time between the two overlapping subclock signals CK1B and CK2B. In the overlap time, both CK1B and CK2B are at a high level, the third discharge switch S3 and the fourth discharge switch S4 between the second terminal B and the fourth terminal D are simultaneously turned on, Terminal B is short-circuited with the fourth terminal D, thereby removing the charge stored in the parasitic capacitor between the second terminal B and the fourth terminal D. After the overlap time, when CK1 is low, CK2B is low and CK2 and CK1B are high. In this case, the first terminal A and the third terminal C are electrically connected to the first power source and the ground terminal GND, respectively, and serve as a power input terminal, and the second terminal B and the first output terminal P are connected. The switch between the fourth terminal D and the second output terminal N is turned on, and the second terminal B and the fourth terminal D serve as output terminals for the magnetic field signal. A short time immediately before CK1 shifts from the low level to the high level, that is, the time between the second two dotted lines shown in FIG. 3b is an overlapping period of the two sub clock signals CK1B and CK2B. During this period, both CK1B and CK2B are at a high level, and the first discharge switch S1 and the second discharge switch S2 between the first terminal A and the third terminal C are turned on and the first discharge switch S2 is turned on. Terminal A is short-circuited with the third terminal C, thereby removing the charge stored in the parasitic capacitor between the first terminal A and the third terminal C.

[0059] FIG. 3d is a schematic diagram of signals of the circuit shown in FIG. 3a. In FIG. 3d, CK is the clock signal and Vos is the offset voltage signal of the magnetic sensor 201, which is assumed to be constant at any instant of the clock signal cycle and depends on the physical properties of the Hall plate 201. . Vin and −Vin are ideal magnetic field signals output by the chopping switch in the first half cycle and the second half cycle of the clock signal CK, that is, ideal outputs of the Hall plate 201 that are not disturbed by the offset signal. As described above, in the first half cycle of the clock signal CK, the terminal A and the terminal C are electrically connected to the first power supply and the ground, respectively, and the terminal B and the terminal D are electrically connected to the output terminal. . In the second half cycle of the clock signal CK, the terminal B and the terminal D are electrically connected to the first power supply and the ground, respectively, and the terminal A and the terminal C are electrically connected to the output terminal. In the first half cycle and the second half cycle of the clock signal CK, the ideal magnetic field signal output by the first chopping switch has the same magnitude and the opposite direction. Vout is the output signal of the first chopping switch, which is a signal superposition of the offset signal Vos and the ideal magnetic field signal Vin. Thus, the magnetic field signal is modulated in the high frequency region by the first chopping switch.

[0060] In an embodiment of the present disclosure, the ideal magnetic field voltage signal output by the magnetic sensor 200 is very weak. In general, the ideal magnetic field signal is only a few tens of millivolts and the offset signal is close to 10 millivolts. It is therefore necessary to remove the offset signal and subsequently amplify the ideal magnetic field signal. As shown in FIG. 1, the first amplifier unit 203 according to the embodiment amplifies the differential signal output by the first chopping switch 202 based on the control of the timing control device 300, and outputs it by the first chopping switch 202. The demodulated difference signal magnetic field signal is demodulated to a low frequency range, and the demodulated difference signal is output.

In the embodiment of the present disclosure, the first amplifier unit 203 may be a chopping amplifier unit as shown in FIG. That is, the first amplifier unit 203 includes a first amplifier A1, a second chopping switch Z2, and a second amplifier A2 that are electrically connected in series. The first amplifier A1 and the second amplifier A2 can amplify the received signal. The second chopping switch Z2 can demodulate the magnetic field signal of the differential signal output by the first chopping switch 202 to a low frequency region. The first amplifier A1 can be a folded cascode amplifier, and the second amplifier A2 can be a single stage amplifier.

[0062] Referring to the integrated circuit shown in FIG. 3, the first amplifier A1 and the second amplifier A2 are configured to amplify the received signal, and the second chopping switch Z2 includes the first clock. Under the control of the signal, the magnetic field signal of the differential signal output by the first chopping switch 202 is demodulated to a low frequency region.

In the embodiment of the present disclosure, the first amplifier A1 receives the pair of difference signals P1 and N1 output by the first chopping switch 202, and outputs a pair of difference signals. The second chopping switch Z2 directly outputs the pair of differential signals output by the first amplifier A1 in the first half cycle of each clock cycle, and exchanges the two differential signals output by the first amplifier A1. The exchanged difference signal is output in the latter half of each clock cycle. The output signals of the second chopping switch Z2 are defined as P2 and N2.

[0064] As shown in FIG. 5, after previous signal processing, under the control of the timing controller 300, the switched capacitor filter module 204 according to an embodiment of the present disclosure is output by the first amplifier unit 203. The difference signal is sampled, the offset of the sample signal is removed to obtain the difference signal, the difference signal is amplified, and the amplified difference signal is output. Optionally, in an embodiment of the present disclosure, the sampling frequency of the switched capacitor filter module 204 can be the same as the chopping frequency of the first chopping switch, i.e. the first output by the timing controller. The frequencies of the clock signal and the second clock signal are the same. The differential signal output by the first amplifier unit 203 includes a first sub differential signal and a second sub differential signal.

[0065] In an embodiment of the present disclosure, the switched capacitor filter unit may be a switched capacitor filter unit as shown in FIG. The switched capacitor filter module 204 includes a first switched capacitor filter SCF1, a second switched capacitor filter SCF2, a third switched capacitor filter SCF3, and a fourth switched capacitor filter SCF4. The first switched capacitor filter SCF1 and the second switched capacitor filter SCF2 sample the difference signal output by the first amplifier unit during the first half cycle as a first sample signal. The third switched capacitor filter SCF3 and the fourth switched capacitor filter SCF4 sample the difference signal output during the latter half cycle by the first amplifier unit as the second sample signal.

FIG. 6a shows a schematic circuit diagram of the switched capacitor filter, and FIG. 6b shows a time sequence diagram of the switched capacitor filter of FIG. 6a. Each of the first switched capacitor filter SCF1, the second capacitor filter SCF2, the third capacitor filter SCF3, and the fourth capacitor filter SCF4 includes two transmission gate switches and two capacitors (a dotted frame in FIG. 6a). Indicated).

[0067] The first switched capacitor filter SCF1 and the second switched capacitor filter SCF2 are the first sub difference signal and the second sub difference signal output by the first amplifier unit 203 in the first half cycle. The output is configured to be sampled as a first subsample signal and a second subsample signal, respectively. The third switched capacitor filter SCF3 and the fourth switched capacitor filter switch SCF4 receive the first sub differential signal output and the second sub differential signal output output by the first amplifier unit 203 in the latter half cycle. Are configured to sample as a third sub-sample signal and a fourth sub-sample signal, respectively. As shown in FIG. 6a, the sample clock signal of the switched capacitor filter module 204 includes four sub clock signals CK1 ′, CK2 ′, CK1B ′, and CK2B ′, and each transmission gate switch is represented by one sub clock signal. Be controlled.

[0068] When the difference signals P2 and N2 are received by the switched capacitor filter module 204, in the first half cycle, the first transmission gate TG1 of the first switched capacitor filter SCF1 and the second switched capacitor filter SCF2 is turned on. , The second transmission gate TG2 of the first switched capacitor filter SCF1 and the second switched capacitor filter SCF2 is turned off, and the first transmission of the third switched capacitor filter SCF3 and the fourth switched capacitor filter SCF4. The gate TG1 is turned off, and the second transmission gate TG2 of the third switched capacitor filter SCF3 and the fourth switched capacitor filter SCF4 is turned on. In the latter half cycle, the first transmission gate TG1 of the first switched capacitor filter SCF1 and the second switched capacitor filter SCF2 is turned off, and the first switched capacitor filter SCF1 and the second switched capacitor filter SCF2 are turned on. The second transmission gate TG2 is turned on, the first transmission gate TG1 of the third switched capacitor filter SCF3 and the fourth switched capacitor filter SCF4 is turned on, and the third switched capacitor filter SCF3 and the fourth switch are turned on. The second transmission gate TG2 of the capacitor capacitor SCF4 is turned off. The first and third switched capacitor filters sample the first difference signal P2 in the first half and the second half cycle, respectively, and the second and fourth switched capacitor filters obtain the second difference signal N2, Sampling is performed in the first half and second half cycles, respectively.

[0069] As shown in FIG. 6a, a plurality of metal insulator metal (MIM) capacitors are connected in parallel between the first switched capacitor filter SCF1 and the second switched capacitor SCF2. A plurality of metal insulator metal (MIM) capacitors are connected between the third switched capacitor filter SCF3 and the fourth switched capacitor filter SCF4. Two groups of capacitors are connected between the first switched capacitor filter SCF1 and the second switched capacitor SCF2, and each group of capacitors may comprise two capacitors connected in parallel. One group of capacitors is electrically connected between a common terminal of the two transmission gate switches of the first switched capacitor filter SCF1 and a common terminal of the two transmission gate switches of the second switched capacitor filter SCF2. The other group of capacitors are connected to the output terminal of the second transmission gate TG2 of the first switched capacitor filter SCF1 and the output terminal of the second transmission gate TG2 of the second switched capacitor SCF2. Can be electrically connected. Two groups of capacitors are coupled between the third switched capacitor filter SCF3 and the fourth switched capacitor SCF4, and each group of capacitors may include two capacitors coupled in parallel. One group of capacitors is electrically connected between a common terminal of the two transmission gate switches of the third switched capacitor filter SCF3 and a common terminal of the two transmission gate switches of the fourth switched capacitor filter SCF4. The other group of capacitors are connected between the output terminal of the second transmission gate TG2 of the third switched capacitor filter and the output terminal of the second transmission gate TG2 of the fourth switched capacitor SCF4. It is electrically connected between.

[0070] The frequency of the sample clock signal is the same as the frequency of the clock signal of the magnetic sensor. The sample clock signal is delayed by a predetermined time, such as a quarter period, with respect to the clock signal of the magnetic sensor, and peaks and valleys of the difference signal can be avoided.

[0071] The first switched capacitor filter SCF1 and the second switched capacitor SCF2 use the difference signals P2 and N2 as the first subsample signal P2A and the second subsample signal N2A, respectively, in the first half cycle. Sampling. The third switched capacitor filter SCF3 and the fourth switched capacitor filter SCF4 sample the difference signals P2 and N2 as the third subsample signal P2B and the fourth subsample signal N2B, respectively, in the latter half cycle. .

[0072] The offset is removed by adding a third subsample signal to the first subsample signal, and the offset is removed by adding a fourth subsample signal to the second subsample signal. As shown in FIG. 6c, the switched capacitor filter unit 204 obtains the difference signal by adding the second sample signal to the first sample signal and amplifies the difference signal to remove the offset. Further included is an adder 2041. Specifically, the adder 2041 adds the fourth subsample signal N2B to the second subsample signal N2A to remove the offset, and adds the third subsample signal P2B to the first subsample signal P2A. The offset is removed, whereby the differential signal is acquired and the differential signal is amplified. The difference signals output by the adder are defined as P3 and N3. Optionally, the adder according to an embodiment of the present disclosure is a transconductance amplifier with a gain of two.

[0073] As shown in FIG. 6c, which is a structural diagram of an adder according to an embodiment of the present disclosure, the adder includes an operational amplifier A ', a first voltage-current converter M1, and a second voltage-current converter. M2 and a third voltage-current converter M3. Each voltage-current converter is electrically connected to a current source and includes two metal oxide semiconductor (MOS) transistors. In the first voltage-current converter M1, the gate of the MOS transistor receives the sample signal P2A, and the output terminal of the MOS transistor is electrically connected to the non-inverting terminal of the operational amplifier A ′. The gate of the transistor is configured to receive the sample signal N2A, and the output terminal of another MOS transistor is electrically connected to the inverting terminal of the operational amplifier A ′. In the second voltage-current converter M2, the gate of the MOS transistor is configured to receive the sample signal P2B, the output terminal of the MOS transistor is electrically connected to the non-inverting terminal of the operational amplifier A ′, The gate of another MOS type transistor can receive the sample signal N2B, and the output terminal of the other MOS type transistor is electrically connected to the inverting terminal of the operational amplifier A ′. In the third voltage-current converter M3, the gate of the MOS transistor can receive the differential signal N3 output by the operational amplifier A ′, and the output terminal of the MOS transistor has a non-inversion of the operational amplifier A ′. And the gate of another MOS transistor can receive the differential signal P3 output by the operational amplifier A ′, and the output terminal of the MOS transistor is connected to the inverting terminal of the operational amplifier A ′. Electrically connected. The voltage-current converter of the adder converts the input sample signal into a current, and removes the offset by adding the current. The current is output after being amplified by the operational amplifier of the adder. A source-generating resistor is preferably placed at the input of the adder to ensure that the MOS transistor of the voltage-current converter operates in the saturation region. That is, as shown in FIG. 6c, a series resistor R ′ is electrically connected between the source electrodes of the two MOS transistors of the voltage-current converter, so that the MOS transistor of the voltage-current converter is connected. Ensures that it operates in the saturation region.

[0074] Further, the signal processing unit further includes a second amplifier unit 205, which is electrically connected between the switched capacitor filter module 204 and the converter 206 and output by the adder. Configured to amplify. The second amplifier unit outputs amplified differential signals P3 and N3. In an embodiment, the second amplifier unit is a programmable gain amplifier with a gain of 5.

[0075] In the embodiment, the total amplification gain of the first amplifier unit, the adder, and the second amplifier regarding the amplification of the magnetic field signal is in the range of 800 to 2000 including both ends, and is preferably 1000. . In other embodiments, the magnetic field signal can be amplified with the required gain by setting different gains for the first amplifier unit, the adder, and the second amplifier unit.

[0076] As shown in FIG. 1a, the differential signal is processed by the switched capacitor filter unit and the second amplifier unit under the control of the timing controller 300 to control the output control circuit. It needs to be converted into a magnetic field signal. FIG. 7a is a structural diagram of a transducer according to an embodiment of the present disclosure. The converter includes a first comparator C1, a second comparator C2, and a latch logic circuit S.

[0077] The first comparator C1 and the second comparator C2 are electrically connected to the pair of difference reference voltages Vh and V1 and the pair of difference signals P3 and N3, respectively, which are output by the second amplifier unit. Connected. The pair of differential reference voltages of the first comparator C1 and the pair of differential reference voltages of the second comparator C2 are electrically connected in reverse. The first comparator C1 is configured to compare the voltage signal output output by the second amplifier unit with a high threshold Rh, and the second comparator C2 is a voltage output by the second amplifier unit. It is configured to compare the signal output with a low threshold value Rl. The output terminals of the first comparator C1 and the second comparator C2 are electrically connected to the input terminal of the latch logic circuit S.

As shown in FIG. 7b, the first comparator C1 compares the voltage signal output by the second amplifier unit with the high threshold Rh, or the strength of the external magnetic field and the predetermined operating point Bop. Is configured to output a comparison result between and. The second comparator C2 outputs a comparison result between the voltage signal output by the second amplifier unit and the low threshold value R1, or a comparison result between the strength of the external magnetic field and a predetermined open point Brp. Configured as follows.

In the latch logic circuit S, the comparison result output by the first comparator C1 indicates that the voltage signal output by the second amplifier unit is greater than the high threshold Rh, or the strength of the external magnetic field is low. When indicating that the predetermined operating point Bop is reached, the signal processing unit 300 is configured to output a first level (such as high level) signal to indicate the magnetic polarity of the external magnetic field.

In the latch logic circuit S, the comparison result output by the second comparator C2 indicates that the voltage signal output by the second amplifier unit is lower than the low threshold value R1, or the strength of the external magnetic field is low. When expressing that the predetermined release point Brp has not been reached, the signal processing unit 300 outputs a signal at a second level (low level) opposite to the first level so that another type of magnetic polarity of the external magnetic field is generated. Configured to represent.

In the latch logic circuit S, the comparison result output by the first comparator C1 and the second comparator C2 indicates that the voltage signal output by the second amplifier unit is smaller than the higher threshold value Rh. The magnetic field detection circuit 200 is configured to output a signal in an initial output state when it indicates that the threshold value is greater than the low threshold value Rl or when the strength of the external magnetic field does not reach the operating point Bop and reaches the release point Brp. Is done.

The second clock signal output output from the timing controller to the latch logic circuit S is delayed by a second predetermined time, such as 5 nanoseconds, with respect to the third clock signal. Avoid filter switching points. The process of signals of the signal processing unit according to an embodiment of the present disclosure will be described in detail with reference to FIG. The left part of FIG. 8 shows the difference signal output by each module under the control of the clock signal, and the right part of FIG. 8 shows a schematic diagram of the signal corresponding to the difference signal in the frequency domain.

From the above description, the output signal Vout of the first chopping switch is a superposition of the offset signal Vos and the ideal magnetic field signal Vin, and is equal to the difference between the difference signal P1 and the difference signal N1. I understand. The difference signals P1 and N1 have the same magnitude and opposite directions. From the above description, it can be seen that the ideal magnetic field voltage signal output by the first chopping switch in the first half cycle and the second half cycle of the clock signal CK1 has the same magnitude and the opposite direction. 8, the signal P1 is represented as P1A and P1B in the first half cycle and the second half cycle of the clock signal, respectively, and the signal N1 is represented as N1A and N1B in the first half cycle and the second half cycle of the clock signal, respectively. Represent. P1A, P1B, N1A and N1B are represented as follows.
P1A = (Vos + Vin) / 2; P1B = (Vos-Vin) / 2
N1A =-P1A =-(Vos + Vin) / 2; N1B =-P1B =-(Vos-Vin) / 2.

In order to facilitate understanding, the coefficient 1/2 of the difference signal is omitted in the following description. A pair of difference signals P1 ′ and N1 ′ are input to the second chopping switch via the first amplifier. The signal P1 ′ is represented as P1A ′ and P1B ′ in the first half cycle and the second half cycle of the clock signal, respectively, and the signal N1 ′ is represented as N1A ′ and N1B ′ in the first half cycle and the second half cycle of the clock signal, respectively. Because of the bandwidth limitation of the first amplifier A1, the differential signal output through the first amplifier A1 is a triangular wave differential signal. The next formula is only the signal form. Each signal is expressed as follows.
P1A '= A (Voff + Vin) / 2; P1B' = A (Voff-Vin) / 2
N1A '=-P1A' = -A (Voff + Vin) / 2; N1B '=-P1B' = -A (Voff-Vin) / 2.

[0085] A is the gain of the first amplifier, and Voff is the offset of the output signal of the first amplifier, which is equal to the sum of the intrinsic offset Vos of the magnetic sensor 200 and the offset of the first amplifier. . The offset Voff is variable for reasons of bandwidth limitation of the first amplifier A1. In order to facilitate understanding, the difference signal coefficient and the amplifier amplification coefficient are omitted in the following description.

[0086] The second chopping switch Z2 directly outputs a pair of difference signals in the first half cycle of each clock cycle, exchanges the difference signals in the second half cycle of each clock cycle, and outputs the exchanged difference signal. Configured as follows. The differential signal output by the second chopping switch is represented as P2 and N2. Signal P2 is represented as P2A and P2B in the first and second half cycles of the clock signal, and signal N2 is represented as N2A and N2B in the first and second half cycles of the clock signal. The outputs of the signal P2 and the signal N2 are expressed as follows, respectively.
P2A = P1A '= (Voff + Vin); P2B = N1B' =-(Voff-Vin)
N2A = N1A '=-(Voff + Vin); N2B = P1B' = (Voff-Vin);

[0087] The four switched capacitor filters of the switched capacitor filter module 303 sample each signal included in the difference signals P2 and N2 in the first half cycle and the second half cycle of each clock, and output two pairs of sample signals. That is, the pair of sample signals obtained by the switched capacitor filter module includes P2A and P2B, and the other pair of sample signals obtained by the switched capacitor filter module includes N2A and N2B.

[0088] The four sample signals are input to the adder, and the adder outputs P3 and N3. The adder adds two pairs of two pairs of respective sample signals and outputs P3 and N3.
P3 = P2A + P2B = (Voff + Vin) + (-(Voff-Vin)) = 2Vin; and
N3 = N2A + N2B =-(Voff + Vin) + (Voff-Vin) = -2Vin.

It can be seen that the signals P3 and N3 output by the adder only include the amplified ideal magnetic field voltage signal, and the offset signal has been removed.

[0090] In addition, the magnetic sensor integrated circuit according to embodiments of the present disclosure further includes a counter 207 electrically connected to the transducer 206. The counter 207 can output the magnetic field detection signal (that is, the difference signal) output by the converter 206 after counting for a predetermined time. The output of the magnetic field detection signal is delayed for a predetermined time (such as 50 microseconds) by the counting action of the counter 207, thereby ensuring a sufficient response time of the entire circuit.

FIG. 9 is a block diagram of a magnetic sensor integrated circuit. The magnetic sensor integrated circuit further includes an output port 20 and an output control circuit 30 connected between the magnetic field detection circuit 200 and the output control circuit 30.

The output control circuit 30 can control the magnetic sensor integrated circuit to operate at least in the first state or the second state. In the embodiment, the first state can be a current flow from the output port 20 to the outside, and the second state can be a current flow from the outside to the output port 20. The output control circuit 30 is powered by a DC voltage at the second output terminal V2 of the full-wave rectifier bridge 110. Specifically, the magnetic sensor integrated circuit operates in a first state in which load current flows out of the output port 20, or operates in a second state in which load current flows into the output port 20, or the first state and the second state. Can be operated alternately in the state of Thus, in another embodiment of the present disclosure, the output control circuit 30 can be further configured to operate in response to a control signal under predetermined conditions. The integrated circuit operates in at least one of a first state in which the load current flows from the output port 20 to the outside and a second state in which the load current flows from the outside to the output port 20, and does not satisfy a predetermined condition The integrated circuit operates in a third state where operation in the first state or the second state is prevented. In a preferred embodiment, the frequency of occurrence of the third state is directly proportional to the frequency of the AC power source.

[0093] In the magnetic sensor integrated circuit according to the embodiment of the present disclosure, the type of the third state of the output control circuit 30 is as long as the output control circuit 30 is prevented from entering the first state or the second state. Can be configured based on user requirements. For example, when the output control circuit 30 operates in the third state, the output control circuit 30 does not respond to the magnetic field detection signal (it can be understood that the magnetic field detection signal cannot be acquired) or at the output port 20. The current is much less than the load current (eg, less than a quarter of the load current, in which case the current can be substantially omitted with respect to the load current).

The counter 207 can start counting in response to acquisition of a predetermined trigger signal. When the counting period reaches a predetermined time, it is indicated that the magnetic sensor integrated circuit satisfies the predetermined condition, and the magnetic sensor integrated circuit starts operation. Specifically, the predetermined trigger signal can be generated when a specific voltage in the magnetic sensor integrated circuit rises and reaches a predetermined threshold value. In the embodiment, the specific voltage may be a supply voltage of the signal processing unit. In the third state, the output control circuit 400 enters the first state or the second state after the counter 306 counts a predetermined time such as 50 microseconds after obtaining the predetermined trigger signal.

Based on the above embodiment, in the embodiment of the present disclosure, the output control circuit 30 includes a first switch and a second switch. The first switch and the output port are electrically connected by a first current path, and the second switch and the output port are electrically connected by a second current path in a direction opposite to the direction of the first current path. Is done. The first switch and the second switch are selectively turned on under the control of the magnetic field detection signal. Optionally, the first switch is a diode and the second switch is a diode or transistor, which is not limited herein and depends on the situation.

In the embodiment of the present disclosure, as shown in FIG. 10, the first switch 31 and the second switch 32 are a pair of complementary semiconductor switches. The first switch 31 is turned on when a low level is applied thereto, and the second switch 32 is turned on when a high level is applied thereto. The first switch 31 and the output port 20 are electrically connected through a first current path, and the second switch 402 and the output port 20 are electrically connected through a second current path. The control ends of the first switch 31 and the second switch 32 are both electrically connected to the magnetic field detection circuit 200. The current input terminal of the first switch 31 is electrically connected to a high voltage (such as a DC power supply), and the current output terminal of the first switch 31 is electrically connected to the current input terminal of the second switch 32. The current output terminal of the second switch 32 is electrically connected to a low voltage (such as a ground terminal). When the magnetic field detection signal output by the magnetic field detection circuit 200 is at a low level, the first switch 31 is turned on while the second switch 32 is turned off, and the load current is changed from the high voltage to the first switch 31 and the output port. 20 flows out. When the magnetic field detection signal output by the magnetic field detection circuit 200 is at a high level, the second switch 32 is turned on while the first switch 31 is turned off, and the load current flows from the outside to the output port 20, Flows through switch 32. In the embodiment shown in FIG. 10, the first switch 31 is a positive channel metal oxide semiconductor field effect transistor (P-type MOSFET), and the second switch 32 is a negative channel metal oxide semiconductor field effect transistor (N Type MOSFET). In other embodiments, the first and second switches can be other types of semiconductor switches, such as junction field effect transistors (JFETs) and metal semiconductor field effect transistors (MESFETs). It should be understood that a field effect transistor can be formed.

[0097] In another embodiment of the present disclosure, as shown in FIG. 11, the first switch 31 is turned on when a high level is applied thereto, and the second switch 32 is a one-way conducting diode. The control end of the first switch 31 and the cathode of the second switch 32 are electrically connected to the output end of the converter. The current input terminal of the first switch 31 is electrically connected to the output terminal of the rectifier circuit, and the current output terminal of the first switch 31 is electrically connected to the anode of the second switch 31 and the output port 20. Is done. The first switch 31 and the output port 20 are electrically connected through a first current path, and the output port 20, the second switch 32, and the magnetic field detection circuit 200 are electrically connected through a second current path. The When the magnetic field detection signal output by the magnetic field detection circuit 200 is at a high level, the first switch 31 is turned on while the second switch 32 is turned off, and the load current is supplied from the rectifier circuit to the first switch 31 and the output port. Flows out through 20. When the magnetic field detection signal output by the magnetic field detection circuit 200 is at a low level, the second switch 32 is turned on while the first switch 31 is turned off, and the load current flows from the outside to the output port 20, and the second switch 32 is turned on. Flows through switch 32. In other embodiments of the present disclosure, it should be understood that the first switch 31 and the second switch 32 can have other structures, which are not limited herein and depend on the situation. .

[0098] In another embodiment of the present disclosure, the output control circuit includes: a first current path through which current flows outward from the output port; a second current path through which current flows inward from the output port; A switch electrically connected to one of the current path and the second current path. The switch is controlled by a magnetic field detection signal output by the signal processing unit, and selectively turns on the first current path and the second current path. Optionally, no switches are placed on the other paths of the first current path and the second current path.

As an implementation, as shown in FIG. 12, the output control circuit 30 includes a one-way conductive switch 33 electrically connected to the output port 20 of the first current path. The current input terminal of the one-way conductive switch 33 can be electrically connected to the output terminal of the magnetic field detection circuit 200. The output end of the magnetic field detection circuit 200 can be electrically connected to the output port 20 via a resistor R1 in the second current path, and the direction of the second current path is the same as that of the first current path. Opposite direction. The one-way conductive switch 33 is turned on when the magnetic field detection signal is at a high level, and the load current flows to the outside through the one-way conductive switch 33 and the output port 20. The one-way conductive switch 33 is turned off when the magnetic field detection signal is at a low level, and the load current flows from the outside to the output port 20 and flows through the resistor R1 and the magnetic field detection circuit 200. Alternatively, the resistor R1 in the second current path can be replaced by a one-way conductive switch electrically connected in parallel back-to-back with the one-way conductive switch 33 so that the load current flowing out of the output port is Balance with the load current flowing into the output port.

[0100] In another implementation, as shown in FIG. 12a, the output control circuit 30 includes diodes D1 and D2, and a resistor R1 and a resistor R2. The diodes D1 and D2 are electrically connected in anti-series between the output terminal of the magnetic field detection circuit 200 and the output port 20. Resistor R1 is electrically connected in parallel with diodes D1 and D2 electrically connected in series. Resistor R2 is electrically connected between power supply Vcc and the common end of diodes D1 and D2. The cathode of the diode D1 is electrically connected to the output terminal of the magnetic field detection circuit 200. The diode D1 is controlled by the magnetic field detection information. When the magnetic detection signal is at a high level, the diode D1 is turned off, and the load current flows out from the output port Pout through the resistor R2 and the diode D2. When the magnetic field detection signal is at a low level, the load current flows from the outside to the output port Pout and flows through the resistor R1 and the magnetic field detection circuit 200.

[0101] A magnetic field integrated circuit according to an embodiment of the present disclosure will be described as follows along with specific applications.

[0102] As shown in FIG. 13, an electric motor assembly is further provided according to embodiments of the present disclosure. An electric motor assembly includes an electric motor 2000 fed by an AC power supply 1000, a bidirectional conductive switch 3000 electrically connected in series to the motor 2000, and a magnetic sensor integrated circuit according to any one of the above embodiments of the present disclosure. 4000. The output port of the magnetic sensor integrated circuit 4000 is electrically connected to the control end of the bidirectional conductive switch 3000. Bidirectional conductive switch 3000 is preferably triac (TRIAC). It should be understood that the bidirectional conductive switch can be implemented with other suitable types of switches. For example, a bidirectional conductive switch can include two silicon controlled rectifiers electrically connected in anti-parallel and corresponding control circuitry. The two silicon controlled rectifiers are controlled in a predetermined manner by the control circuit based on the output signal output from the output port of the magnetic sensor integrated circuit. The electric motor preferably further includes a voltage drop circuit 5000 that lowers the voltage of the AC power supply 1000 and supplies the drop voltage to the magnetic sensor integrated circuit 4000. The magnetic sensor integrated circuit 4000 is disposed near the rotor of the electric motor 2000 to detect a change in the magnetic field of the rotor.

[0103] Based on the above embodiment, in the embodiment of the present disclosure, the electric motor is a synchronous electric motor. It should be understood that the magnetic sensor integrated circuit according to the present disclosure applies not only to synchronous electric motors, but also to other types of permanent magnet electric motors such as DC brushless motors. As shown in FIG. 14, the synchronous motor includes a stator and a rotor 1001 that rotates with respect to the stator. The stator includes a stator core 1002 and a stator winding 1006 wound around the stator core 1002. The stator core 1002 can be made of a soft magnetic material such as pure iron, cast iron, cast steel, electric steel, or silicon steel. The rotor 1001 includes a permanent magnet. When the stator winding 1006 is connected in series with an AC power supply, the rotor 1001 rotates at a constant rotational speed (60 f / p) rmp in a steady state, where f is the frequency of the AC power supply and p is the rotor. Is the number of pole pairs. In the embodiment, the stator core 1002 has two pole portions 1004 arranged to face each other. Each pole portion has a pole arc surface 1005. The outer surface of the rotor 1001 faces the magnetic pole arc surface 1005, and a substantially uniform air gap is formed between them. The essentially uniform air gap in the present disclosure indicates that the majority of the air gap between the stator and the rotor is uniform and the small part of the air gap between the stator and the rotor is non-uniform. A concave start groove 1007 is preferably disposed on the magnetic pole arc surface 1005 of the pole portion of the rotor. Portions other than the starting groove 1007 in the magnetic pole arc surface 1005 are concentric with the rotor. With the above configuration, an inhomogeneous magnetic field can be formed, thereby ensuring that when the rotor does not rotate, the pole axis S1 of the rotor is inclined at an angle with respect to the center axis S2 of the pole part of the stator. Thus, the rotor can have a starting torque each time the motor is energized under the action of the integrated circuit. The rotor polar axis S1 is a boundary between two magnetic poles of the rotor having different polarities. A center axis S2 of the pole portion 1004 of the stator is a connection line passing through the centers of the two pole portions 1004 of the stator. In the embodiment, the stator and the rotor each have two magnetic poles. In other embodiments, it will be appreciated that the number of stator poles may differ from the number of rotor poles, and that the stator and rotor may have more poles, such as four and six poles. I want.

The output control circuit 30 operates when the AC power supply 1000 operates in a positive half cycle and the magnetic field sensor detects that the magnetic field of the permanent magnet rotor has the first polarity, or when the AC power supply 1000 is in the negative half-cycle. When the magnetic field sensor detects that the magnetic field sensor operates in a cycle and the magnetic field of the permanent magnet rotor has a second polarity opposite to the first polarity, the bidirectional conductive AC switch 3000 is configured to turn on. The output control circuit 30 operates when the AC power source 1000 operates with a negative half cycle and the permanent magnet rotor has a first polarity, or when the AC power source operates with a positive half cycle and the permanent magnet rotor has a second polarity. Is turned off, the bidirectional conductive AC switch 3000 is turned off.

Based on the above embodiment, in the embodiment of the present disclosure, the output control circuit 30 detects that the AC power supply 1000 operates in a positive half cycle and the polarity of the permanent magnet rotor is the first polarity. When the circuit 200 detects, or when the magnetic field detection circuit detects that the AC power supply 1000 operates in a negative half cycle and the polarity of the permanent magnet rotor is the second polarity opposite to the first polarity, The bidirectional conductive switch 3000 is configured to be turned on, and when the AC power supply 1000 operates in a negative half cycle and the permanent magnet rotor has the first polarity, or the AC power supply 1000 operates in a positive half cycle. In addition, when the permanent magnet rotor has the second polarity, the bidirectional conductive switch 3000 is preferably configured to be turned off.

[0106] When the magnetic sensor detects that the signal output by the AC power supply 1000 is in a positive half cycle and the magnetic field of the permanent magnet rotor is the first polarity, the output control circuit 30 outputs both signals from the integrated circuit. Controlling the current flowing through the directional switch 3000, and that the signal output by the AC power supply 100 is in a negative half cycle and that the magnetic field of the permanent magnet rotor has a second polarity opposite to the first polarity. Preferably, the magnetic sensor is configured to control the current flowing from the bidirectional conductive switch 3000 to the integrated circuit when detected. When the permanent magnet rotor has the first magnetic polarity and the AC power source is in the positive half cycle, current can flow out of the integrated circuit in all or part of the positive half cycle, and the permanent magnet rotor is in the second half. It is to be understood that current can flow into the integrated circuit in all or part of the positive half cycle when the AC power source is in the negative half cycle.

In a preferred embodiment of the present disclosure, the rectifier circuit 100 has a circuit as shown in FIG. 2, and the output control circuit 400 has a circuit as shown in FIG. The current input terminal of the first switch 31 of the output control circuit 30 is electrically connected to the second output terminal V2 of the full-wave rectifier bridge 110, and the second current output terminal of the second switch 32 is It is electrically connected to the ground end of the wave rectifier bridge 110. When the signal output from the AC power supply 1000 is in a positive half cycle and the magnetic sensor outputs a low level signal, the first switch 31 in the output control circuit 30 is turned on and the second switch 32 is turned off. The current is supplied to the AC power supply 1000, the electric motor 2000, the first input terminal of the magnetic sensor integrated circuit 4000, the voltage drop circuit (not shown), the second diode 112 of the full-wave rectifier bridge 110, and the output control circuit 400. The first flow through the first switch 31, the flow from the output port to the bidirectional conductive switch 3000, and then back to the AC power supply 1000. When the bidirectional conductive switch 3000 is turned on, the series branch formed by the voltage drop circuit 5000 and the magnetic sensor integrated circuit 4000 is short-circuited, and the magnetic sensor integrated circuit 4000 stops the output because there is no power supply, and the bidirectional conductive switch 3000 3000 has a sufficiently large current flowing through its two anodes (greater than the holding current of the bidirectional conductive switch 3000), so that the drive current is between the control pole and the first anode of the bidirectional conductive switch 3000. Stays on while no current flows. When the signal output by the AC power supply 1000 operates in a negative half cycle and the magnetic field detection signal output by the magnetic sensor is at a high level, the first switch 31 is turned off and the second switch 32 is turned on. , Current flows from the alternating current 1000 and flows to the output port through the bidirectional conductive switch 3000, the second switch 32 of the output control circuit 30, the ground output terminal of the full-wave rectifier bridge 110 and the first diode 111, The magnetic sensor integrated circuit 4000 returns to the AC power supply 100 via the first input terminal and the motor 2000. Similarly, when the bidirectional conductive switch 3000 is turned on, the magnetic sensor integrated circuit 4000 is short-circuited and stops outputting, and the bidirectional conductive switch 3000 remains on. The signal output by the AC power supply 1000 operates in a positive half cycle and the magnetic field detection signal output by the magnetic sensor is at a high level, or the signal output by the AC power supply 1000 operates in a negative half cycle and When the magnetic field detection signal is at a low level, both the first switch 31 and the second switch 32 in the output control circuit 30 are off, and the bidirectional conductive switch 3000 is off. Accordingly, the output control circuit 30 can control the integrated circuit based on the polarity change and the difference signal of the AC power supply 1000 to turn on or off the bidirectional conductive switch 3000 in a predetermined manner. In this way, the manner in which the stator winding 1006 is fed can be controlled, and the changing magnetic field generated by the stator coincides with the magnetic field position of the rotor, thereby rotating the rotor along the signal direction, so that the rotor feeds the motor. Each time it is guaranteed to rotate in a certain direction.

[0108] In the embodiment of the present disclosure, the magnetic field detection signal is a switch type detection signal. In the steady state of the electric motor, the switching frequency of the switch type detection signal is twice the frequency of the AC power supply.

[0109] In the above embodiments, it should be understood that the magnetic sensor integrated circuit according to the present disclosure is described only in conjunction with possible applications, and the magnetic sensor according to the present disclosure is not limited thereto. For example, the magnetic sensor can be applied not only to driving an electric motor but also to other applications including magnetic field detection.

[0110] In a motor according to another embodiment of the disclosure, the motor is formed by an electric motor and a bidirectional conductive switch that can be electrically connected in series with a bidirectional switch between two ends of an external AC power source. The first series branch is electrically connected in parallel with the second series branch formed by the voltage drop circuit and the magnetic sensor integrated circuit. The output port of the magnetic sensor integrated circuit is electrically connected to the bidirectional conductive switch and controls the bidirectional conductive switch to turn on or off in a preset manner, thereby controlling the feed mode of the stator winding. .

[0111] Accordingly, an application apparatus according to an embodiment of the present disclosure is further provided. The application apparatus includes a motor powered by an AC power supply, a bidirectional conductive switch electrically connected in series to the electric motor, and a magnetic sensor integrated circuit according to any one of the above embodiments. The output port of the magnetic sensor integrated circuit is electrically connected to the control end of the bidirectional conductive switch. Optionally, the application device can be a pump, fan, home appliance, vehicle and the like, and the home appliance can be, for example, a washing machine, a dishwasher, a range hood, an exhaust fan, etc. it can.

[0112] Following the description of the embodiments herein, one of ordinary skill in the art will be able to make or use the disclosure. Many improvements to the embodiments will be apparent to those skilled in the art. The general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the disclosure. Accordingly, the present disclosure is not limited to the embodiments described herein, but is to be accorded with the widest scope consistent with the principles and novel features disclosed herein.

DESCRIPTION OF SYMBOLS 100 Rectifier circuit 200 Magnetic field detection circuit 201 Magnetic sensor 202 1st chopping switch 203 1st amplifier unit 204 Switched capacitor filter module 205 1st amplifier unit 206 Converter 207 Comparator 300 Timing control apparatus

Claims (10)

A magnetic sensor integrated circuit,
A rectifier circuit for converting an external power source into a DC power source;
A magnetic field detection circuit for detecting a polarity of the external magnetic field and outputting a magnetic detection signal, comprising: a magnetic sensor; a first chopping switch; a first amplifier unit; and a switched capacitor filter module;
A timing control device, wherein a first clock signal is output to the first chopping switch and the first amplifier unit, and a second clock delayed by a first predetermined time with respect to the first clock signal And a timing control device for outputting a signal to the switched capacitor filter module.   A converter is further provided, and the timing control device outputs a third clock signal to the converter, and the second clock signal is delayed by a second predetermined time with respect to the third clock signal. Item 2. The magnetic sensor integrated circuit according to Item 1.   The magnetic sensor integrated circuit according to claim 2, wherein the first predetermined time is longer than the second predetermined time.   The magnetic sensor integrated circuit according to claim 1, wherein the first predetermined time is a ¼ period of the first clock signal.   The magnetic sensor integrated circuit according to claim 2, wherein the first, second, and third clock signals have the same frequency.   3. The magnetic sensor integrated circuit according to claim 2, wherein the frequencies of the first, second, and third clock signals are 100 kHz to 600 kHz including both ends.   The magnetic sensor integrated circuit according to claim 1, wherein the first clock signal comprises at least two non-overlapping subclock signals, and the second clock signal comprises at least two non-overlapping subclock signals.   The differential signal output by the magnetic sensor includes a magnetic field signal and an offset signal, and the first chopping switch modulates the magnetic field signal and the offset signal to a high frequency region and a baseband frequency, respectively. The magnetic sensor integrated circuit as described.   A motor assembly comprising: a motor fed by an AC power supply; and the magnetic sensor integrated circuit according to claim 1.   An application apparatus including a motor assembly, wherein the motor assembly includes a motor powered by an AC power source and the magnetic sensor integrated circuit according to any one of claims 1 to 8. Applied equipment.

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