JP3207559B2 - MOS drive type semiconductor device - Google Patents
MOS drive type semiconductor deviceInfo
- Publication number
- JP3207559B2 JP3207559B2 JP28869492A JP28869492A JP3207559B2 JP 3207559 B2 JP3207559 B2 JP 3207559B2 JP 28869492 A JP28869492 A JP 28869492A JP 28869492 A JP28869492 A JP 28869492A JP 3207559 B2 JP3207559 B2 JP 3207559B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- mos
- thickness
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 48
- 239000012535 impurity Substances 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 description 19
- 230000000903 blocking effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高耐圧を有するＭＯＳ
駆動型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS having a high withstand voltage.
The present invention relates to a driving semiconductor device.
【０００２】[0002]
【従来の技術】従来、ＭＯＳ駆動型半導体装置、例えば
ＩＧＢＴは、図７又は図８に示すような素子構造を有し
ている。図７及び図８において、１１は、Ｎ- 型ベ−ス
層、１２は、Ｐ型ベ−ス層、１３は、Ｎ型エミッタ層、
１４は、Ｐ型エミッタ層、１５は、カソ−ド電極、１６
は、アノ−ド電極、１７は、ゲ−ト電極、１８は、バッ
ファ層である。2. Description of the Related Art Conventionally, a MOS drive type semiconductor device, for example, an IGBT has an element structure as shown in FIG. 7 or FIG. 7 and 8, 11 is N − Mold base layer, 12 is a P-type base layer, 13 is an N-type emitter layer,
14 is a P-type emitter layer, 15 is a cathode electrode, 16
Is an anode electrode, 17 is a gate electrode, and 18 is a buffer layer.
【０００３】上記ＭＯＳ駆動型半導体装置では、当該半
導体素子が形成されるチップの終端部（縁部）には、一
般に、複数の拡散層１９、…から構成される多重のガ−
ドリング（プレ−ナ構造）が採用されている。これによ
り、当該半導体装置の耐圧を向上させている。In the MOS drive type semiconductor device described above, generally, a multi-layered structure composed of a plurality of diffusion layers 19 is provided at the end (edge) of a chip on which the semiconductor element is formed.
A dring (planar structure) is employed. Thereby, the withstand voltage of the semiconductor device is improved.
【０００４】しかし、上述のような多重のガ−ドリング
からなるプレ−ナ構造を採用すると、第一に、チップの
終端部において複数の拡散層１９、…（電流が流れない
領域）が大きな面積を占め、チップ上における有効面積
が減少する、という欠点がある。また、第二に、当該プ
レ−ナ構造においても、理論上得ることができる耐圧の
約８割しか耐圧を得ることができない、という欠点があ
る。However, when the planar structure composed of multiple guard rings as described above is adopted, first, a plurality of diffusion layers 19,... And the effective area on the chip is reduced. Second, the planar structure has a drawback that only about 80% of the theoretically obtainable withstand voltage can be obtained.
【０００５】[0005]
【発明が解決しようとする課題】このように、従来は、
チップの終端部において、多重のガ−ドリングからなる
プレ−ナ構造を採用しているが、かかる構造では、チッ
プ上における有効面積が減少したり、理論値よりも低い
耐圧しか得られない、という欠点がある。As described above, conventionally,
At the end of the chip, a planar structure composed of multiple guard rings is employed. However, such a structure reduces the effective area on the chip and provides a withstand voltage lower than the theoretical value. There are drawbacks.
【０００６】本発明は、上記欠点を解決すべくなされた
もので、その目的は、チップ上における有効面積を増や
し、理論値に近い電圧阻止能力を有するＭＯＳ駆動型半
導体装置を提供することである。The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a MOS-driven semiconductor device having an effective area on a chip and having a voltage blocking capability close to a theoretical value. .
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するた
め、本発明のＭＯＳ駆動型半導体装置は、第１導電型の
第１の層と、前記第１の層上に形成される第２導電型の
第２の層と、前記第２の層の表面領域に形成される第１
導電型の複数の第３の層と、前記第３の層の表面領域に
形成される第２導電型の第４の層と、前記第１の層に接
続される第１の電極と、前記第３及び第４の層に接続さ
れる第２の電極と、前記第３の層に跨がるように形成さ
れる第３の電極と、前記第２の層の終端部の表面領域に
一つのみ形成され、前記第２の電極に接続されることに
より前記第３の層の電位と同電位に保たれる第１導電型
の第５の層とを備える。In order to achieve the above object, a MOS drive type semiconductor device according to the present invention comprises a first layer of a first conductivity type and a second layer formed on the first layer. A second layer of a mold and a first layer formed in a surface region of the second layer.
A plurality of third layers of a conductivity type; a fourth layer of a second conductivity type formed in a surface region of the third layer; a first electrode connected to the first layer; A second electrode connected to the third and fourth layers, a third electrode formed so as to straddle the third layer, and a first electrode in a surface region of a terminal portion of the second layer. And a fifth layer of the first conductivity type that is connected to the second electrode and maintained at the same potential as the potential of the third layer.
【０００８】また、前記第５の層の厚さは、前記第３の
層の厚さよりも大きくなっている。前記第３の層の直下
における第１の層の厚さは、前記第５の層の直下におけ
る第１の層の厚さよりも大きくなっており、前記第２の
層の厚さがほぼ均一である。[0008] The thickness of the fifth layer is larger than the thickness of the third layer. The thickness of the first layer immediately below the third layer is greater than the thickness of the first layer immediately below the fifth layer, and the thickness of the second layer is substantially uniform. is there.
【０００９】また、前記第５の層の直下における第１の
層の導電型を第２導電型に変え、かつ、当該第２導電型
の第１の層の不純物濃度を前記第２の層の不純物濃度よ
りも高くしている。また、前記第１の層と前記第２の層
との間にバッファ層を設けたものである。前記第２の層
の終端部は、斜めに切り落とされており、かつ、当該終
端部は、樹脂によって保護されている。In addition, the conductivity type of the first layer immediately below the fifth layer is changed to the second conductivity type, and the impurity concentration of the first layer of the second conductivity type is changed to the second layer. It is higher than the impurity concentration. Further, a buffer layer is provided between the first layer and the second layer. The terminal end of the second layer is cut off diagonally, and the terminal end is protected by resin.
【００１０】[0010]
【作用】上記構成によれば、第２の層の終端部には、第
３の層と同電位の一つの第５の層が形成され、かつ、い
わゆるメサ構造を採用している。また、通電領域におけ
る第１の層の深さも大きくしている。これにより、素子
特性を劣化させることなく、チップ上における有効面積
を増やすことができ、理論値に近い電圧素子能力を有す
るＭＯＳ駆動型半導体装置を提供できる。さらに、当該
ＭＯＳ駆動型半導体装置とダイオ−ドとをモノリシック
に形成することもでき、当該半導体装置を利用した応用
装置全体の小型化に貢献できる。According to the above construction, one fifth layer having the same potential as that of the third layer is formed at the terminal end of the second layer, and a so-called mesa structure is employed. Further, the depth of the first layer in the energized region is also increased. As a result, the effective area on the chip can be increased without deteriorating element characteristics, and a MOS-driven semiconductor device having a voltage element capability close to the theoretical value can be provided. Further, the MOS drive type semiconductor device and the diode can be formed monolithically, which can contribute to downsizing of the entire application device using the semiconductor device.
【００１１】[0011]
【実施例】以下、図面を参照しながら、本発明の一実施
例について詳細に説明する。図１は、本発明の第１の実
施例に係わるＭＯＳ駆動型半導体装置（ＩＧＢＴ）を示
すものである。図１において、２１は、Ｎ- 型ベ−ス
層、２２は、Ｐ型ベ−ス層、２３は、Ｎ型エミッタ層、
２４は、Ｐ型エミッタ層、２５は、カソ−ド電極、２６
は、アノ−ド電極、２７は、ゲ−ト電極である。An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a MOS drive type semiconductor device (IGBT) according to a first embodiment of the present invention. In FIG. 1, 21 is N − Mold base layer, 22 is a P-type base layer, 23 is an N-type emitter layer,
24 is a P-type emitter layer, 25 is a cathode electrode, 26
Is an anode electrode, and 27 is a gate electrode.
【００１２】上記ＭＯＳ駆動型半導体装置は、当該半導
体素子が形成されるチップの終端部（縁部）に一つの拡
散層２８を有している。この拡散層２８は、チップの終
端部おいて当該チップを取り囲むようにして形成されて
いる。また、拡散層２８は、カソ−ド電極２５に接続さ
れており、Ｐ型ベ−ス層２２と同電位となっている。さ
らに、チップの終端面は、斜め（例えば基板主面に対し
約６０°）に切り落とされ、かつ、シリコ−ン樹脂２９
等で保護されている。なお、このシリコ−ン樹脂２９等
は、チップの終端面を斜めに切り落とす加工による破砕
層をエッチングにより除去した後に形成される。The MOS drive type semiconductor device has one diffusion layer 28 at the end (edge) of the chip on which the semiconductor element is formed. The diffusion layer 28 is formed at the terminal end of the chip so as to surround the chip. The diffusion layer 28 is connected to the cathode electrode 25 and has the same potential as the P-type base layer 22. Further, the terminal surface of the chip is cut off diagonally (for example, at about 60 ° with respect to the main surface of the substrate).
Etc. are protected. The silicon resin 29 and the like are formed after a crushed layer formed by diagonally cutting off the end surface of the chip is removed by etching.
【００１３】上記構成によれば、チップ終端部の拡散層
２８は一つであり、また、当該拡散層２８は、Ｐ型ベ−
ス層２２と同電位である。さらに、チップ終端面が斜め
に切り落とされたメサ構造を有する。これにより、チッ
プ上における有効面積を増やすことができると共に、理
論値に近い電圧阻止能力を有するＭＯＳ駆動型半導体装
置にすることができる。According to the above configuration, the number of the diffusion layer 28 at the chip end is one, and the diffusion layer 28 is a P-type base.
The potential is the same as that of the semiconductor layer 22. Further, it has a mesa structure in which the chip end surface is cut off obliquely. Thereby, the effective area on the chip can be increased, and a MOS-driven semiconductor device having a voltage blocking ability close to the theoretical value can be obtained.
【００１４】図２は、本発明の第２の実施例に係わるＭ
ＯＳ駆動型半導体装置（ＩＧＢＴ）を示すものである。
なお、図２において、図１と同じ部分には同じ符号を付
してある。FIG. 2 is a block diagram showing a second embodiment of the present invention.
1 shows an OS drive type semiconductor device (IGBT).
In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals.
【００１５】このＭＯＳ駆動型半導体装置は、チップの
終端部の拡散層２８の深さを、Ｐ型ベ−ス層２２の深さ
よりも大きくしたものである。Ｐ型ベ−ス層２２の深さ
は、一般的には約１０〜２５［μｍ］であり、この程度
の深さで２５００［Ｖ］以上の電圧阻止能力を持たせよ
うとするのは困難である。なぜなら、チップ終端部の鋭
角部は製造工程途上においてかけやすく、また、かけた
場合には拡散層２８の深さが実質的に浅くなるためであ
る。そこで、チップの終端部の拡散層２８の深さを、Ｐ
型ベ−ス層２２の深さ（約１０〜２５［μｍ］）よりも
深い、約３０〜７０［μｍ］としたものである。In this MOS drive type semiconductor device, the depth of the diffusion layer 28 at the end of the chip is greater than the depth of the P-type base layer 22. The depth of the P-type base layer 22 is generally about 10 to 25 [μm], and it is difficult to provide a voltage blocking ability of 2500 [V] or more at such a depth. It is. This is because the sharp end portion of the chip end portion is easily formed during the manufacturing process, and when formed, the depth of the diffusion layer 28 is substantially reduced. Therefore, the depth of the diffusion layer 28 at the end of the chip is set to P
The depth is about 30 to 70 [μm], which is deeper than the depth (about 10 to 25 [μm]) of the mold base layer 22.
【００１６】上記構成によれば、上記第１の実施例と同
様の効果が得られる他、さらに２５００［Ｖ］以上の電
圧阻止能力を有するＭＯＳ駆動型半導体装置を歩留りよ
く製造できる、という効果が得られる。According to the above configuration, the same effect as that of the first embodiment can be obtained, and further, a MOS drive type semiconductor device having a voltage blocking ability of 2500 [V] or more can be manufactured with high yield. can get.
【００１７】図３は、本発明の第３の実施例に係わるＭ
ＯＳ駆動型半導体装置（ＩＧＢＴ）を示すものである。
なお、図３において、図２と同じ部分には同じ符号を付
してある。FIG. 3 shows a third embodiment of the present invention.
1 shows an OS drive type semiconductor device (IGBT).
In FIG. 3, the same parts as those in FIG. 2 are denoted by the same reference numerals.
【００１８】このＭＯＳ駆動型半導体装置は、チップの
終端部の拡散層２８の深さを、Ｐ型ベ−ス層２２の深さ
よりも大きくし、電圧阻止能力の向上を図った点におい
て第２の実施例と共通する。This MOS drive type semiconductor device is characterized in that the depth of the diffusion layer 28 at the end of the chip is made larger than the depth of the P-type base layer 22 to improve the voltage blocking capability. This embodiment is common to the embodiment of FIG.
【００１９】しかし、第２の実施例では、通電領域にお
けるＮ- 型べ−ス層２１が、終端部の拡散層２８直下の
Ｎ- 型べ−ス層２１に比べて、当該拡散層２８を深くし
た分だけ厚くなってしまう。なお、通電領域におけるＮ
- 型べ−ス層２１が厚くなると、以下の不都合が生じ
る。即ち、Ｎ- 型べ−ス層２１の抵抗値 Ｒが増大する
ため、当該Ｎ- 型べ−ス層２１中の電圧降下 Ｖ（＝Ｒ
×Ｉ）もまた大きくなる。なお、電流Ｉは一定とする。
従って、当該半導体装置に発生する電力（熱エネルギ
−） Ｐ（＝Ｉ×Ｖ）が増大し、通電状態における特性
を劣化させる。However, in the second embodiment, N − The mold base layer 21 is formed of N − just below the diffusion layer 28 at the end. As compared with the mold base layer 21, the diffusion layer 28 becomes thicker by the depth. Note that N in the energization region
- When the mold base layer 21 is thick, the following disadvantages occur. In other words, N - Since the resistance value R of the mold base layer 21 increases, the N − The voltage drop V (= R) in the mold base layer 21
× I) also increases. Note that the current I is constant.
Therefore, the power (thermal energy) P (= I × V) generated in the semiconductor device increases, and the characteristics in the energized state deteriorate.
【００２０】そこで、本実施例では、通電領域における
Ｐ型エミッタ層２４の深さを、他の領域（終端部）にお
ける当該Ｐ型エミッタ層２４の深さよりも大きくしたも
のである。言い換えれば、Ｎ- 型ベ−ス層２１の厚さ
ｔを場所によらず、即ち通電領域及びチップ終端部にお
いてほぼ一定としたものである。Therefore, in the present embodiment, the depth of the P-type emitter layer 24 in the current-carrying region is made larger than the depth of the P-type emitter layer 24 in the other region (termination). In other words, N - The thickness of the mold base layer 21
t is substantially constant regardless of the location, that is, in the energized region and the chip end portion.
【００２１】上記構成によれば、上記第２の実施例と同
様の効果が得られることに加えて、さらに通電状態にお
ける特性を向上、即ちＭＯＳ駆動型半導体装置に発生す
る熱量を最小限に抑えることができる。According to the above configuration, in addition to obtaining the same effects as in the second embodiment, the characteristics in the energized state are further improved, that is, the amount of heat generated in the MOS drive type semiconductor device is minimized. be able to.
【００２２】図４は、本発明の第４の実施例に係わるＭ
ＯＳ駆動型半導体装置（ＩＧＢＴ）を示すものである。
なお、図４において、図３と同じ部分には同じ符号を付
してある。FIG. 4 is a block diagram of a fourth embodiment of the present invention.
1 shows an OS drive type semiconductor device (IGBT).
In FIG. 4, the same parts as those in FIG. 3 are denoted by the same reference numerals.
【００２３】このＭＯＳ駆動型半導体装置は、チップの
終端部において、アノ−ド電極２６側にチャネルストッ
パとしてのＮ型拡散層３０を形成したものである。この
拡散層３０は、チャネルストッパとしての役割を果たす
と共に、当該半導体素子（ＩＧＢＴ）と逆並列に接続さ
れるダイオ−ド３１としての役割を果たすものである。
また、Ｎ型拡散層３０の不純物濃度は、Ｎ- 型ベ−ス層
２１の不純物濃度よりも高くなっている。In this MOS drive type semiconductor device, an N-type diffusion layer 30 as a channel stopper is formed on the anode electrode 26 side at the end of the chip. The diffusion layer 30 functions as a channel stopper and also functions as a diode 31 connected in anti-parallel with the semiconductor element (IGBT).
The impurity concentration of the N-type diffusion layer 30 is N − It is higher than the impurity concentration of the mold base layer 21.
【００２４】上記構成によれば、上記第３の実施例と同
様の効果が得られる他、以下の効果を得ることができ
る。即ち、ＩＧＢＴなどのＭＯＳ駆動型半導体装置は、
これにダイオ−ドを逆並列に接続して使用するのが一般
的であり、本実施例によれば、当該ＩＧＢＴとダイオ−
ドをモノリシックに形成できるため、当該半導体装置を
利用した応用装置全体の小型化を達成できるメリットが
ある。According to the above configuration, the same effects as those of the third embodiment can be obtained, and the following effects can be obtained. That is, a MOS-driven semiconductor device such as an IGBT is
In general, a diode is connected in anti-parallel and used, and according to this embodiment, the IGBT and the diode are connected.
Since the semiconductor device can be formed monolithically, there is an advantage that the size of the entire application device using the semiconductor device can be reduced.
【００２５】図５及び図６は、それぞれ本発明の第５の
実施例に係わるＭＯＳ駆動型半導体装置（ＩＧＢＴ）を
示すものである。なお、図５において図３と同じ部分に
は同じ符号を付してある。また、図６において図４と同
じ部分には同じ符号を付してある。FIGS. 5 and 6 show a MOS-driven semiconductor device (IGBT) according to a fifth embodiment of the present invention. In FIG. 5, the same parts as those in FIG. 3 are denoted by the same reference numerals. In FIG. 6, the same parts as those in FIG. 4 are denoted by the same reference numerals.
【００２６】本実施例は、図３及び図４のＭＯＳ駆動型
半導体装置にバッファ層３２を設けたものであり、これ
によりＮ- 型ベ−ス層２１をさらに薄くすることがで
き、電圧降下を低くすることができる。なお、ここでは
ＩＧＢＴについて記述したが、本発明がその他のＭＯＳ
駆動型半導体装置にも適用できることは、容易に類推で
きる。[0026] This example is for a buffer layer 32 provided on the MOS-driven type semiconductor device of FIG. 3 and FIG. 4, thereby N - The mold base layer 21 can be further thinned, and the voltage drop can be reduced. Although the IGBT has been described here, the present invention is not limited to other MOS transistors.
It can be easily analogized that the present invention can also be applied to a drive type semiconductor device.
【００２７】[0027]
【発明の効果】以上、説明したように、本発明のＭＯＳ
駆動型半導体装置によれば、次のような効果を奏する。
チップ終端部には、Ｐ型ベ−ス層と同電位の一つのＰ型
拡散層が形成され、かつ、メサ構造を採用している。ま
た、通電領域におけるＰ型エミッタ領域の深さも大きく
している。これにより、素子特性を劣化させることな
く、チップ上における有効面積を増やすことができ、理
論値に近い電圧素子能力を有するＭＯＳ駆動型半導体装
置を提供できる。さらに、ＩＧＢＴとダイオ−ドをモノ
リシックに形成でき、当該半導体装置を利用した応用装
置全体の小型化に貢献できる。As described above, the MOS of the present invention is used as described above.
According to the drive type semiconductor device, the following effects can be obtained.
One P-type diffusion layer having the same potential as that of the P-type base layer is formed at the chip end, and employs a mesa structure. Further, the depth of the P-type emitter region in the current-carrying region is also increased. As a result, the effective area on the chip can be increased without deteriorating element characteristics, and a MOS-driven semiconductor device having a voltage element capability close to the theoretical value can be provided. Further, the IGBT and the diode can be formed monolithically, which contributes to the miniaturization of the whole application device using the semiconductor device.
【図１】本発明の第１の実施例に係わるＭＯＳ駆動型半
導体装置を示す断面図。FIG. 1 is a sectional view showing a MOS-driven semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施例に係わるＭＯＳ駆動型半
導体装置を示す断面図。FIG. 2 is a sectional view showing a MOS-driven semiconductor device according to a second embodiment of the present invention.
【図３】本発明の第３の実施例に係わるＭＯＳ駆動型半
導体装置を示す断面図。FIG. 3 is a sectional view showing a MOS-driven semiconductor device according to a third embodiment of the present invention.
【図４】本発明の第４の実施例に係わるＭＯＳ駆動型半
導体装置を示す断面図。FIG. 4 is a sectional view showing a MOS-driven semiconductor device according to a fourth embodiment of the present invention.
【図５】本発明の第５の実施例に係わるＭＯＳ駆動型半
導体装置を示す断面図。FIG. 5 is a sectional view showing a MOS-driven semiconductor device according to a fifth embodiment of the present invention.
【図６】本発明の第５の実施例に係わるＭＯＳ駆動型半
導体装置を示す断面図。FIG. 6 is a sectional view showing a MOS-driven semiconductor device according to a fifth embodiment of the present invention.
【図７】従来のＭＯＳ駆動型半導体装置を示す断面図。FIG. 7 is a sectional view showing a conventional MOS drive type semiconductor device.
【図８】従来のＭＯＳ駆動型半導体装置を示す断面図。FIG. 8 is a sectional view showing a conventional MOS drive type semiconductor device.
２１ …Ｎ- 型ベ−ス層、 ２２ …Ｐ型ベ−ス層、 ２３ …Ｎ型エミッタ層、 ２４ …Ｐ型エミッタ層、 ２５ …カソ−ド電極、 ２６ …アノ−ド電極、 ２７ …ゲ−ト電極、 ２８ …Ｐ型拡散層、 ２９ …シリコ−ン樹脂、 ３０ …Ｎ型拡散層、 ３１ …ダイオ−ド、 ３２ …バッファ層。21 ... N - Type base layer, 22 ... P type base layer, 23 ... N type emitter layer, 24 ... P type emitter layer, 25 ... cathode electrode, 26 ... anode electrode, 27 ... gate electrode, 28 ... P-type diffusion layer, 29 ... silicon resin, 30 ... N-type diffusion layer, 31 ... diode, 32 ... buffer layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 唐澤 大 東京都府中市東芝町１番地 株式会社東 芝府中工場内 (56)参考文献 特開 平４−229661（ＪＰ，Ａ) 特開 昭63−104480（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Dai Dai Karasawa 1 Toshiba-cho, Fuchu-shi, Tokyo Inside the Toshiba Fuchu Plant, Inc. (56) References JP-A-4-229661 (JP, A) JP-A-63 −104480 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/78
Claims (4)
上に形成される第２導電型の第２の層と、前記第２の層
の表面領域に形成される第１導電型の複数の第３の層
と、前記第３の層の表面領域に形成される第２導電型の
第４の層と、前記第１の層に接続される第１の電極と、
前記第４の層、或いは前記第３及び第４の層に接続され
る第２の電極と、前記第３の層に跨がるように絶縁層を
介して形成される第３の電極と、前記第２の層の終端部
の表面領域に一つのみ形成され、前記第２の電極に接続
されることにより前記第３の層の電位と同電位に保たれ
る第１導電型の第５の層とを具備し、前記第５の層の厚
さは、前記第３の層の厚さよりも大きくなっていること
を特徴とするＭＯＳ駆動型半導体装置。1. A first layer of a first conductivity type, a second layer of a second conductivity type formed on the first layer, and a first layer formed on a surface region of the second layer. A plurality of third layers of one conductivity type, a fourth layer of second conductivity type formed in a surface region of the third layer, a first electrode connected to the first layer,
A fourth electrode or a second electrode connected to the third and fourth layers, and a third electrode formed via an insulating layer so as to extend over the third layer; Only one is formed in the surface region of the terminal portion of the second layer, and is connected to the second electrode so as to be maintained at the same potential as the potential of the third layer. And the thickness of the fifth layer
The MOS drive type semiconductor device , wherein the thickness is larger than the thickness of the third layer .
厚さは、前記第５の層の直下における第１の層の厚さよ
りも大きくなっており、前記第２の層の厚さがほぼ均一
であることを特徴とする請求項１に記載のＭＯＳ駆動型
半導体装置。2. The thickness of the first layer immediately below the third layer is greater than the thickness of the first layer immediately below the fifth layer, and the thickness of the second layer is 2. The MOS-driven semiconductor device according to claim 1 , wherein said MOS drive type semiconductor device has a substantially uniform thickness.
導電型を第２導電型に変え、かつ、当該第２導電型の第
１の層の不純物濃度を前記第２の層の不純物濃度よりも
高くしたことを特徴とする請求項１又は２に記載のＭＯ
Ｓ駆動型半導体装置。3. The method according to claim 1, wherein the conductivity type of the first layer immediately below the fifth layer is changed to the second conductivity type, and the impurity concentration of the first layer of the second conductivity type is changed to the second layer. 3. The MO according to claim 1, wherein the impurity concentration is higher than the impurity concentration.
S drive type semiconductor device.
とされており、かつ、当該終端部は、樹脂によって保護
されていることを特徴とする請求項１乃至３のいずれか
１項に記載のＭＯＳ駆動型半導体装置。4. A terminal portion of the second layer is cut off obliquely, and the termination section, any one of claims 1 to 3, characterized in that it is protected by the resin 2. The MOS-driven semiconductor device according to 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28869492A JP3207559B2 (en) | 1992-10-27 | 1992-10-27 | MOS drive type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28869492A JP3207559B2 (en) | 1992-10-27 | 1992-10-27 | MOS drive type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06140633A JPH06140633A (en) | 1994-05-20 |
| JP3207559B2 true JP3207559B2 (en) | 2001-09-10 |
Family
ID=17733488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28869492A Expired - Lifetime JP3207559B2 (en) | 1992-10-27 | 1992-10-27 | MOS drive type semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3207559B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3275536B2 (en) | 1994-05-31 | 2002-04-15 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP3612226B2 (en) * | 1998-12-21 | 2005-01-19 | 株式会社東芝 | Semiconductor device and semiconductor module |
| JP5082211B2 (en) * | 2005-03-25 | 2012-11-28 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| JP2007184486A (en) * | 2006-01-10 | 2007-07-19 | Denso Corp | Semiconductor device |
| JP4265684B1 (en) * | 2007-11-07 | 2009-05-20 | トヨタ自動車株式会社 | Semiconductor device |
| JP5520024B2 (en) * | 2009-12-09 | 2014-06-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP6317694B2 (en) | 2015-03-16 | 2018-04-25 | 株式会社東芝 | Semiconductor device |
| JP7043750B2 (en) * | 2017-07-14 | 2022-03-30 | 株式会社デンソー | SiC- MOSFET |
-
1992
- 1992-10-27 JP JP28869492A patent/JP3207559B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06140633A (en) | 1994-05-20 |
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