JP3204346B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art In a conventional semiconductor memory device, an example of a method for continuously reading out data of a plurality of words at high speed (hereinafter referred to as page access) is shown in FIGS.

In FIG. 3, a memory cell 25 storing data and a memory cell row selecting decode circuit 2 are shown.
3, a memory cell column selecting decode circuit 24, a number of sense amplifiers 26 for detecting and amplifying potential changes of the selected memory cells, and a number of data holding circuits for holding data amplified by the sense amplifiers 26. 27, an output circuit 28 for outputting data to the outside, an address circuit 21 for generating a signal for activating the memory cell row and column selection decode circuits 23 and 24, and all sense amplifiers 26 in an operating state. And a page access address circuit 22 for generating a signal for selecting the data holding circuit 27.

Here, in the case of an n-word page access, n sense amplifiers 26 and data holding circuits 27 are provided for each external output terminal.

Next, this operation will be described with reference to FIG. Address signal 2 generated by address circuit 21
9 activates the memory cell column and row selection decode circuits 23 and 24, and selects n memory cells per external output terminal.

At this time, the page access address circuit 22
The n sense amplifiers 26 are activated by the sense amplifier activation signal 31 from the CPU, and the potential change of the selected memory cell is detected and amplified by the n sense amplifiers 26, respectively. The amplified data is held by n data holding circuits 27 connected to.

Next, any one of the n data holding circuits 27 for one external output terminal is arbitrarily selected according to the output of the page access address circuit 22.
Data of n words can be continuously output at a high speed.

[0008]

A conventional n-word page access type ROM requires n sense amplifiers 26 for one external output terminal. Of the sense amplifier 26 was required.

As a result, the current flowing when all the sense amplifiers 26 are in the operating state becomes 16 × n, which causes an increase in power consumption.

There is another problem that the chip area is increased by disposing 16 × n sense amplifiers 26 on the chip.

[0011]

According to the present invention, there is provided a semiconductor memory device comprising: an address circuit for receiving a signal from an external input terminal to generate an address signal; a decode circuit activated by the address signal; A memory cell that stores data, a sense amplifier that detects and amplifies a potential change of the memory cell selected by the decode circuit, a data holding circuit that holds data amplified by the sense amplifier, the semiconductor memory instrumentation page access method and a page access address circuit for generating a signal for selecting a plurality of said data holding circuit
In each of the plurality of sense amplifiers.
The first select circuit and the second select circuit are connected,
A first holding circuit and a second holding circuit
Combining second holding circuit, the inputs one signal of a page access address circuit has an address dividing circuit for generating the two signals newly, the signal of the address dividing circuit, the first and second select Any of the circuits
Select the selected data of the memory cell to be input to the sense amplifier by selecting the select circuit, and select the second data by the signal of the address dividing circuit.
Data of one of the first and second data holding circuits
By selecting a holding circuit, data of the selected data holding circuit is sent to the output circuit .

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 showing a block diagram of a semiconductor memory device according to one embodiment of the present invention, and FIG. 2 showing a timing chart, this embodiment shows an address circuit 1, a page access address circuit 2, Cell row selection decode circuit 3
, A memory cell column selection decode circuit 4, a memory cell 5, an address division circuit 6, a select circuit 7, a sense amplifier 8, a data holding circuit 9, and an output circuit 10.
And

Here, in the case of an n-word page access, n select circuits 7, n / 2 are provided for one external output terminal.
, And n data holding circuits 9.

The signals include an address signal 11, an address division signal (Ax, Ax (inverted value)) 12, and a page access address signal 13.

Next, the operation of the semiconductor memory device will be described. By the address signal 11 from the address circuit 1,
The memory cell row selection decode circuit 3 and the memory cell column selection circuit 4 are activated, and each of the external output terminals sets n memory cells 5 to a selected state.

The change in potential of the selected n memory cells 5 is transmitted to the n select circuits 7 via the memory cell column selection decode circuit 4. The address division circuit 6
A change in the uppermost signal of the page access address circuit 2 is detected, and the signals Ax and A of the address division signal 12 having different phases are detected.
x (reverse value). The address division signal 12
Are input to S1 and S2 of the select circuit 7 and L1 and L2 of the data holding circuit 9, respectively.

In the section of the first address signal 11,
The sense amplifier 8 is always operating, and is activated by selecting the S1 of the select circuit 7 and the L1 of the data holding circuit 9 by the Ax signal of the address division signal 12, and the memory cell selected through the S1 of the select circuit 7 5 is detected and amplified by the sense amplifier 8 and the data is held by L1 of the data holding circuit 9.

At this time, S2 of the select circuit 7 and the data holding circuit L2 are connected to the Ax (inverted value) of the address division signal 12.
Deactivated by signal.

Next, S2 of the select circuit 7 and L2 of the data holding circuit 9 are selected and activated by the Ax (inverted value) signal of the address division signal 12, and the select circuit 7 is activated.
The potential change of the memory cell 5 selected through S2 is detected and amplified by the sense amplifier 8, and the data is held by L2 of the data holding circuit 9.

At this time, S1 of the select circuit 7 and L1 of the data holding circuit 9 are inactivated by the Ax signal of the address division signal 12.

The n data holding circuits 9 are connected to one output circuit 10, and the n data holding circuits 9 are continuously selected by the page access address signal 13 from the page access address circuit 2, whereby n data holding circuits 9 are selected. Word data can be output continuously and at high speed.

In the embodiment described above, the signal of the page access address circuit 2 detected by the address dividing circuit 6 is not always the highest signal.

[0023]

As is apparent from the above description, according to the semiconductor memory device of the present invention, the select circuit and the data holding circuit are divided by the two signals (Ax, Ax (inverted value)) divided by the address dividing circuit. By selecting n /
Since the change in potential of the n selected memory cells can be detected and amplified by the two sense amplifiers, the sense amplifiers can be reduced to half of the conventional one, so that all the sense amplifiers are in the operating state. In this case, the current that flows can be halved, the power consumption can be halved, and the chip area can be reduced by the reduced sense amplifier.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart of this embodiment.

FIG. 3 is a block diagram of a conventional read only memory (ROM) with page access.

FIG. 4 is a timing diagram of a conventional memory.

[Explanation of symbols]

 1, 21 address circuit 2, 22 page access address circuit 3, 23 memory cell row selection decode circuit 4, 24 memory cell column selection decode circuit 5, 25 memory cell 6 address division circuit 7 select circuit 8, 26 sense amplifier 9, 27 Data holding circuit 10, 28 Output circuit 11, 29 Address signal 12 Address division signal 13 Page access address signal 30 Page access address signal 31 Sense amplifier activation signal

Continuation of the front page (56) References JP-A-4-157693 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 16/02 G11C 11/41

Claims (2)

(57) [Claims] An address circuit for generating an address signal by inputting a signal from an external input terminal; a decode circuit activated by the address signal; a memory cell storing data; A sense amplifier for detecting and amplifying a potential change of the selected memory cell, a data holding circuit for holding data amplified by the sense amplifier, and a signal for selecting a plurality of the data holding circuits. Page access addressing circuit and a page access type semiconductor memory
In the storage device, a first select is provided to each of the plurality of sense amplifiers.
And a second select circuit.
A first holding circuit and a second holding circuit for each of the amplifiers
Combine inputs one signal of the page access address circuit has an address dividing circuit newly generates two signals, the signal of the address dividing circuit, the first and second
Select one of the two select circuits
By-option, and select the selected data of the memory cell to be input to the sense amplifier, by a signal of the address dividing circuit, the first and second
Any one of the two data holding circuits
Wherein the data of the selected data holding circuit is sent to the output circuit by selecting ( i). 2. The semiconductor memory device according to claim 1, wherein the number of said sense amplifiers is half that of said select circuit or said data holding circuit.